From c0eae8b2bbe0a94fd6961d0802edf8c6f68227d0 Mon Sep 17 00:00:00 2001 From: Tom Rix Date: Thu, 30 Oct 2025 07:23:52 -0700 Subject: [PATCH] tensile ignore cache check --- Tensile/Common.py | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/Tensile/Common.py b/Tensile/Common.py index a4a8bb524da0..140d4dbe58c2 100644 --- a/Tensile/Common.py +++ b/Tensile/Common.py @@ -2104,17 +2104,7 @@ def GetAsmCaps(isaVersion: IsaVersion, hipVersion: SemanticVersion, cachedAsmCap derivedAsmCaps["SupportedSource"] = True - ignoreCacheCheck = globalParameters["IgnoreAsmCapCache"] - - # disable cache checking for < rocm 5.3 - if len(hipVersion) >= 2: - ignoreCacheCheck = ignoreCacheCheck or \ - hipVersion.major < 5 or \ - (hipVersion.major == 5 and hipVersion.minor <= 2) - - if not derivedAsmCaps["SupportedISA"] and cachedAsmCaps[isaVersion]["SupportedISA"]: - printWarning("Architecture {} not supported by ROCm {}".format(isaVersion, globalParameters['HipClangVersion']), DeveloperWarning) - ignoreCacheCheck = True + ignoreCacheCheck = True # check if derived caps matches asm cap cache if not ignoreCacheCheck: -- 2.52.0