module RgGen::SystemVerilog::RAL::RegisterCommon
Private Instance Methods
array_indices()
click to toggle source
# File lib/rggen/systemverilog/ral/register_common.rb, line 9 def array_indices if component.array? index_table = component.array_size.map { |size| (0...size).to_a } index_table[0].product(*index_table[1..-1]) else [nil] end end
default_offset_address(index)
click to toggle source
# File lib/rggen/systemverilog/ral/register_common.rb, line 28 def default_offset_address(index) component.offset_address + component.byte_size(false) * index end
hdl_path(array_index)
click to toggle source
# File lib/rggen/systemverilog/ral/register_common.rb, line 32 def hdl_path(array_index) [ "g_#{component.name}", *Array(array_index).map { |i| "g[#{i}]" }, *unit_instance_name ].join('.') end
offset_address(index)
click to toggle source
# File lib/rggen/systemverilog/ral/register_common.rb, line 18 def offset_address(index) address = if register? && helper.offset_address instance_exec(index, &helper.offset_address) else default_offset_address(index) end hex(address, register_block.local_address_width) end
unit_instance_name()
click to toggle source
# File lib/rggen/systemverilog/ral/register_common.rb, line 40 def unit_instance_name register? && 'u_register' || nil end