module RgGen::SystemVerilog::RTL::IndirectIndex
Private Instance Methods
index_fields()
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# File lib/rggen/systemverilog/rtl/indirect_index.rb, line 9 def index_fields @index_fields ||= register.collect_index_fields(register_block.bit_fields) end
index_values()
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# File lib/rggen/systemverilog/rtl/indirect_index.rb, line 18 def index_values loop_variables = register.local_loop_variables register.index_entries.zip(index_fields).map do |entry, field| if entry.array_index? loop_variables.shift[0, field.width] else hex(entry.value, field.width) end end end
index_width()
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# File lib/rggen/systemverilog/rtl/indirect_index.rb, line 14 def index_width @index_width ||= index_fields.sum(&:width) end
indirect_index_assignment()
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# File lib/rggen/systemverilog/rtl/indirect_index.rb, line 29 def indirect_index_assignment assign(indirect_index, concat(index_fields.map(&:value))) end