module RgGen::SystemVerilog::RTL::BitFieldIndex

Constants

EXPORTED_METHODS

Public Class Methods

included(feature) click to toggle source
# File lib/rggen/systemverilog/rtl/bit_field_index.rb, line 11
def self.included(feature)
  feature.module_eval do
    EXPORTED_METHODS.each { |m| export m }
  end
end

Public Instance Methods

array_size() click to toggle source
# File lib/rggen/systemverilog/rtl/bit_field_index.rb, line 30
def array_size
  (inside_loop? || nil) &&
    [
      *register_files.flat_map(&:array_size),
      *register.array_size,
      *bit_field.sequence_size
    ].compact
end
local_index() click to toggle source
# File lib/rggen/systemverilog/rtl/bit_field_index.rb, line 17
def local_index
  create_identifier(local_index_name)
end
local_indices() click to toggle source
# File lib/rggen/systemverilog/rtl/bit_field_index.rb, line 21
def local_indices
  [*register.local_indices, local_index_name]
end
loop_variables() click to toggle source
# File lib/rggen/systemverilog/rtl/bit_field_index.rb, line 25
def loop_variables
  (inside_loop? || nil) &&
    [*register.loop_variables, local_index].compact
end

Private Instance Methods

inside_loop?() click to toggle source
# File lib/rggen/systemverilog/rtl/bit_field_index.rb, line 46
def inside_loop?
  register.inside_loop? || bit_field.sequential?
end
local_index_name() click to toggle source
# File lib/rggen/systemverilog/rtl/bit_field_index.rb, line 41
def local_index_name
  (bit_field.sequential? || nil) &&
    loop_index((register.loop_variables&.size || 0) + 1)
end