module RgGen::SystemVerilog::RTL::IndirectIndex

Private Instance Methods

index_fields() click to toggle source
# File lib/rggen/systemverilog/rtl/indirect_index.rb, line 9
def index_fields
  @index_fields ||=
    register.collect_index_fields(register_block.bit_fields)
end
index_values() click to toggle source
# File lib/rggen/systemverilog/rtl/indirect_index.rb, line 18
def index_values
  loop_variables = register.local_loop_variables
  register.index_entries.zip(index_fields).map do |entry, field|
    if entry.array_index?
      loop_variables.shift[0, field.width]
    else
      hex(entry.value, field.width)
    end
  end
end
index_width() click to toggle source
# File lib/rggen/systemverilog/rtl/indirect_index.rb, line 14
def index_width
  @index_width ||= index_fields.sum(&:width)
end
indirect_index_assignment() click to toggle source
# File lib/rggen/systemverilog/rtl/indirect_index.rb, line 29
def indirect_index_assignment
  assign(indirect_index, concat(index_fields.map(&:value)))
end