module RgGen::SystemVerilog::Common::Utility

Public Instance Methods

create_blank_file(path) click to toggle source
# File lib/rggen/systemverilog/common/utility.rb, line 9
def create_blank_file(path)
  SourceFile.new(path)
end

Private Instance Methods

all_bits_0() click to toggle source
# File lib/rggen/systemverilog/common/utility.rb, line 52
def all_bits_0
  "'0"
end
all_bits_1() click to toggle source
# File lib/rggen/systemverilog/common/utility.rb, line 48
def all_bits_1
  "'1"
end
argument(name, attribute = {}) click to toggle source
# File lib/rggen/systemverilog/common/utility.rb, line 90
def argument(name, attribute = {})
  DataObject.new(:argument, attribute.merge(name: name)).declaration
end
array(expressions = nil, default: nil) click to toggle source
# File lib/rggen/systemverilog/common/utility.rb, line 31
def array(expressions = nil, default: nil)
  default_item = default && "default: #{default}"
  "'#{concat([*Array(expressions), default_item].compact)}"
end
assign(lhs, rhs) click to toggle source
# File lib/rggen/systemverilog/common/utility.rb, line 19
def assign(lhs, rhs)
  "assign #{lhs} = #{rhs};"
end
bin(value, width = nil) click to toggle source
# File lib/rggen/systemverilog/common/utility.rb, line 56
def bin(value, width = nil)
  if width
    width = bit_width(value, width)
    format("%d'b%0*b", width, width, value)
  else
    format("'b%b", value)
  end
end
bit_width(value, width) click to toggle source
# File lib/rggen/systemverilog/common/utility.rb, line 84
def bit_width(value, width)
  bit_length = value.bit_length
  bit_length = 1 if bit_length.zero?
  [width, bit_length].max
end
concat(expressions) click to toggle source
# File lib/rggen/systemverilog/common/utility.rb, line 23
def concat(expressions)
  "{#{Array(expressions).join(', ')}}"
end
create_identifier(name) click to toggle source
# File lib/rggen/systemverilog/common/utility.rb, line 15
def create_identifier(name)
  name && Identifier.new(name)
end
dec(value, width = nil) click to toggle source
# File lib/rggen/systemverilog/common/utility.rb, line 65
def dec(value, width = nil)
  if width
    width = bit_width(value, width)
    format("%0d'd%d", width, value)
  else
    format("'d%d", value)
  end
end
function_call(name, expressions = nil) click to toggle source
# File lib/rggen/systemverilog/common/utility.rb, line 36
def function_call(name, expressions = nil)
  "#{name}(#{Array(expressions).join(', ')})"
end
hex(value, width = nil) click to toggle source
# File lib/rggen/systemverilog/common/utility.rb, line 74
def hex(value, width = nil)
  if width
    width = bit_width(value, width)
    print_width = (width + 3) / 4
    format("%0d'h%0*x", width, print_width, value)
  else
    format("'h%x", value)
  end
end
macro_call(name, expressions = nil) click to toggle source
# File lib/rggen/systemverilog/common/utility.rb, line 40
def macro_call(name, expressions = nil)
  if (expression_array = Array(expressions)).empty?
    "`#{name}"
  else
    "`#{name}(#{expression_array.join(', ')})"
  end
end
repeat(count, expression) click to toggle source
# File lib/rggen/systemverilog/common/utility.rb, line 27
def repeat(count, expression)
  "{#{count}{#{expression}}}"
end