class CPU

A generic CPU description

A generic CPU description

Attributes

abus[R]

The address bus

ack[R]

The acknowledge

allocator[R]

Allocator assotiated with the bus of the CPU

clk[R]

The clock.

dbus[R]

The data bus

req[R]

The request

rst[R]

The reset.

rwb[R]

The read/!write selection

Public Class Methods

new(dwidth,awidth,clk,rst) click to toggle source

Creates a new generic CPU whose data bus is dwidth bit wide, address bus is awidth bit wide, clock is clk, reset rst.

# File lib/HDLRuby/hdr_samples/sw_encrypt_cpu_bench.rb, line 28
def initialize(dwidth,awidth,clk,rst)
    # Check and set the word and address bus widths
    awidth = awidth.to_i
    dwidth = dwidth.to_i
    @awidth = awidth
    @dwidth = dwidth
    # Check and set the signals.
    @clk = clk.to_ref
    @rst = rst.to_ref
    # The allocator of the CPU
    @allocator = Allocator.new(0..(2**@addr),@data)

    # Declare the address and data buses and the
    # rwb/req/ack control signals
    abus,dbus    = nil,nil
    rwb,req,ack  = nil,nil,nil
    # Declares the data and address bus.
    HDLRuby::High.cur_system.open do
        abus = [awidth].input(HDLRuby.uniq_name)
        dbus = [dwidth].input(HDLRuby.uniq_name)
        rwb  = input(HDLRuby.uniq_name)
        req  = input(HDLRuby.uniq_name)
        ack  = output(HDLRuby.uniq_name)
    end
    @abus,@dbus    = abus,dbus
    @rwb,@req,@ack = rwb,req,ack
end

Public Instance Methods

connect(sig) click to toggle source

Connect signal sig to the bus allocating an address to access it.

# File lib/HDLRuby/hdr_samples/sw_encrypt_cpu_bench.rb, line 57
def connect(sig)
    # Allocates the signal in the address space.
    @allocator.allocate(sig)
end
controller() click to toggle source

Generates the bus controller.

# File lib/HDLRuby/hdr_samples/sw_encrypt_cpu_bench.rb, line 63
def controller
    clk,rst,req,ack = @clk,@rst,@req,@ack
    abus,dbus,rwb   = @abus,@dbus,@rwb
    allocator       = @allocator
    HDLRuby::High.cur_system.open do
        par(clk) do
            # Bus controller
            hcase(abus)
            hif(req) do
                ack <= 1
                allocator.each do |sig,addr|
                    hwhen(addr) do
                        hif(rwb) { dbus <= sig }
                        helse    { sig <= dbus }
                    end
                end
            end
            helse do
                ack <= 0
            end
        end
    end

    ## Generates a read of sig executing +ruby_block+ on the result.
    def read(sig,&ruby_block)
        addr = @allocator.get(sig)
        hif(ack == 0) do
            @abus <= addr
            @rwb <= 1
            @req <= 1
        helse
            @req <= 0
            ruby_block.call(@dbus)
        end
    end

    ## Generates a write +val+ to +sig+ executing +ruby_block+
    #  in case of success.
    def write(val,sig,&ruby_block)
        addr = @allocator.get(sig)
        hif(ack == 0) do
            @abus <= addr
            @dbus <= val
            @rwb <= 0
            @req <= 1
        helse
            @req <= 0
            ruby_block.call
        end
    end
end
read(sig,&ruby_block) click to toggle source

Generates a read of sig executing ruby_block on the result.

# File lib/HDLRuby/hdr_samples/sw_encrypt_cpu_bench.rb, line 87
def read(sig,&ruby_block)
    addr = @allocator.get(sig)
    hif(ack == 0) do
        @abus <= addr
        @rwb <= 1
        @req <= 1
    helse
        @req <= 0
        ruby_block.call(@dbus)
    end
end
write(val,sig,&ruby_block) click to toggle source

Generates a write val to sig executing ruby_block in case of success.

# File lib/HDLRuby/hdr_samples/sw_encrypt_cpu_bench.rb, line 101
def write(val,sig,&ruby_block)
    addr = @allocator.get(sig)
    hif(ack == 0) do
        @abus <= addr
        @dbus <= val
        @rwb <= 0
        @req <= 1
    helse
        @req <= 0
        ruby_block.call
    end
end