module HDLRuby::Low

Adds methods for allocating addresses to signals in Code objects.

Adds methods for allocating addresses to signals in Code objects and integrate the result into C code.

Low-level libraries for describing digital hardware.

Library for describing the basic structures of the hardware component.

Make HDLRuby::Low objects mutable trough “!” methods.

NOTE: * should be used with care, since it can comprimize the internal

  structures.
* this is a work in progress.

Adds methods for finding objects through names.

NOTE: For now only resolve name reference.

Provides a new boolean type and converts the comparison and operations on it to this new type.

NOTE: * this transformation is a prerequired for supporting target

  language like VHDL that do not consider boolean to be identical
  to bit.
* Boolean is weak in type promotion, e.g.: boolean & bit = bit

Explicitely seperate variables from signals in an HDLRuby::Low description.

NOTE: variable and signal are to be taken in the VHDL meaning.

Ensures that there is no conversion of bit types to vector types.

NOTE: Used for instance for converting to old versions of VHDL where

bit types cannot be casted to vector types.

Ensures that there is no read on output port by adding intermediate inner signal.

NOTE: Used for instance for converting to old versions of VHDL that

include HDLRuby::Low

Constants

Base
Bignum
Hdecorator

Gives a decorator the HDLRuby object.

Integer

Standard vector types.

Natural
Real
VERILOG_BASE_TYPES

The list of base types used both in verilog and HDLRuby

VERILOG_REGS

The list of signals that are actually verilog regs.

Private Class Methods

v_string(str) click to toggle source

Converts string str to a Verilog-compatible string.

# File lib/HDLRuby/hruby_verilog.rb, line 21
def self.v_string(str)
    str = str.gsub(/\n/,"\\n")
    str.gsub!(/\t/,"\\t")
    return str
end