Type:
name: signed
Type:
name: void
Type:
name: bit
TypeVector:
name: integer base: signed range: - 31 - 0
SystemT:
name: memH::T_ inputs: - SignalI: name: clk type: bit - SignalI: name: rwb type: bit - SignalI: name: addr type: TypeVector: name: '' base: bit range: - 15 - 0 outputs: [] inouts: - SignalI: name: data type: TypeVector: name: '' base: bit range: - 7 - 0 scope: Scope: name: '' scopes: [] inners: - SignalI: name: content type: TypeVector: name: '' base: TypeVector: name: '' base: bit range: - 7 - 0 range: - 65535 - 0 systemIs: [] connections: [] behaviors: - Behavior: events: - Event: type: posedge ref: RefName: type: bit ref: RefThis: type: void name: clk block: Block: mode: par name: '' inners: [] statements: - If: condition: RefName: type: bit ref: RefThis: type: void name: rwb 'yes': Block: mode: par name: '' inners: [] statements: - Transmit: left: RefName: type: TypeVector: name: '' base: bit range: - 7 - 0 ref: RefThis: type: void name: data right: RefIndex: type: bit ref: RefName: type: TypeVector: name: '' base: TypeVector: name: '' base: bit range: - 7 - 0 range: - 65535 - 0 ref: RefThis: type: void name: content index: RefName: type: TypeVector: name: '' base: bit range: - 15 - 0 ref: RefThis: type: void name: addr 'no': Block: mode: par name: '' inners: [] statements: - Transmit: left: RefIndex: type: bit ref: RefName: type: TypeVector: name: '' base: TypeVector: name: '' base: bit range: - 7 - 0 range: - 65535 - 0 ref: RefThis: type: void name: content index: RefName: type: TypeVector: name: '' base: bit range: - 15 - 0 ref: RefThis: type: void name: addr right: RefName: type: TypeVector: name: '' base: bit range: - 7 - 0 ref: RefThis: type: void name: data noifs: []
SystemT:
name: memL::T_ inputs: - SignalI: name: clk type: bit - SignalI: name: rwb type: bit - SignalI: name: addr type: TypeVector: name: '' base: bit range: - 15 - 0 outputs: [] inouts: - SignalI: name: data type: TypeVector: name: '' base: bit range: - 7 - 0 scope: Scope: name: '' scopes: [] inners: - SignalI: name: content type: TypeVector: name: '' base: TypeVector: name: '' base: bit range: - 7 - 0 range: - 65535 - 0 systemIs: [] connections: [] behaviors: - Behavior: events: - Event: type: posedge ref: RefName: type: bit ref: RefThis: type: void name: clk block: Block: mode: par name: '' inners: [] statements: - If: condition: RefName: type: bit ref: RefThis: type: void name: rwb 'yes': Block: mode: par name: '' inners: [] statements: - Transmit: left: RefName: type: TypeVector: name: '' base: bit range: - 7 - 0 ref: RefThis: type: void name: data right: RefIndex: type: bit ref: RefName: type: TypeVector: name: '' base: TypeVector: name: '' base: bit range: - 7 - 0 range: - 65535 - 0 ref: RefThis: type: void name: content index: RefName: type: TypeVector: name: '' base: bit range: - 15 - 0 ref: RefThis: type: void name: addr 'no': Block: mode: par name: '' inners: [] statements: - Transmit: left: RefIndex: type: bit ref: RefName: type: TypeVector: name: '' base: TypeVector: name: '' base: bit range: - 7 - 0 range: - 65535 - 0 ref: RefThis: type: void name: content index: RefName: type: TypeVector: name: '' base: bit range: - 15 - 0 ref: RefThis: type: void name: addr right: RefName: type: TypeVector: name: '' base: bit range: - 7 - 0 ref: RefThis: type: void name: data noifs: []
SystemT:
name: mem16_16_longI::T_ inputs: - SignalI: name: clk type: bit - SignalI: name: rwb type: bit - SignalI: name: addr type: TypeVector: name: '' base: bit range: - 15 - 0 outputs: [] inouts: - SignalI: name: data type: TypeVector: name: '' base: bit range: - 15 - 0 scope: Scope: name: '' scopes: [] inners: [] systemIs: - SystemI: name: memL systemT: memL::T_ - SystemI: name: memH systemT: memH::T_ connections: - Connection: left: RefName: type: bit ref: RefName: type: void ref: RefThis: type: void name: memL name: clk right: RefName: type: bit ref: RefThis: type: void name: clk - Connection: left: RefName: type: bit ref: RefName: type: void ref: RefThis: type: void name: memL name: rwb right: RefName: type: bit ref: RefThis: type: void name: rwb - Connection: left: RefName: type: TypeVector: name: '' base: bit range: - 15 - 0 ref: RefName: type: void ref: RefThis: type: void name: memL name: addr right: RefName: type: TypeVector: name: '' base: bit range: - 15 - 0 ref: RefThis: type: void name: addr - Connection: left: RefName: type: TypeVector: name: '' base: bit range: - 7 - 0 ref: RefName: type: void ref: RefThis: type: void name: memL name: data right: RefRange: type: TypeVector: name: '' base: bit range: - Value: type: integer content: 7 - Value: type: integer content: 0 ref: RefName: type: TypeVector: name: '' base: bit range: - 15 - 0 ref: RefThis: type: void name: data range: - Value: type: integer content: 7 - Value: type: integer content: 0 - Connection: left: RefName: type: bit ref: RefName: type: void ref: RefThis: type: void name: memH name: clk right: RefName: type: bit ref: RefThis: type: void name: clk - Connection: left: RefName: type: bit ref: RefName: type: void ref: RefThis: type: void name: memH name: rwb right: RefName: type: bit ref: RefThis: type: void name: rwb - Connection: left: RefName: type: TypeVector: name: '' base: bit range: - 15 - 0 ref: RefName: type: void ref: RefThis: type: void name: memH name: addr right: RefName: type: TypeVector: name: '' base: bit range: - 15 - 0 ref: RefThis: type: void name: addr - Connection: left: RefName: type: TypeVector: name: '' base: bit range: - 7 - 0 ref: RefName: type: void ref: RefThis: type: void name: memH name: data right: RefRange: type: TypeVector: name: '' base: bit range: - Value: type: integer content: 15 - Value: type: integer content: 8 ref: RefName: type: TypeVector: name: '' base: bit range: - 15 - 0 ref: RefThis: type: void name: data range: - Value: type: integer content: 15 - Value: type: integer content: 8 behaviors: []