class CPUSimu
Simulates an 8-bit data 8-bit address CPU
Public Class Methods
new(clk,rst)
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Creates a new CPU
simulator.
Calls superclass method
CPU::new
# File lib/HDLRuby/hdr_samples/sw_encrypt_cpusim_bench.rb, line 124 def initialize(clk,rst) super(8,8,clk,rst) # The read and write control signals. @read_action = inner(HDLRuby.uniq_name) @write_action = inner(HDLRuby.uniq_name) @value = [8].inner(HDLRuby.uniq_name) # The CPU simulator code. this = self read_action,write_action = @read_action, @write_action value = @value par(this.posedge) do hif(this.rst) do read_action <= 0 write_action <= 0 end helse do hif(read_action) do this.hw_read(this.target,value) do read_action <= 0 end end helsif(write_action) do this.hw_write(this.target,write_value) do write_action <= 0 end end end end # The runtime code. code c: [ "unsigned char mem_read(unsigned char addr) { unsigned char res; write8(1,",@read_action,"); wait_cond8(0,",@read_action,"); return read8(",@value,"); } void mem_write(unsigned char val, unsigned char addr) { unsigned char res; write8(1,",@write_action,"); write8(val,",@value,"); wait_cond8(0,",@write_action,"); } "], h: "extern unsigned char mem_read(unsigned char addr); extern void mem_write(unsigned char val, unsigned char addr); " end
Public Instance Methods
read(code,sig)
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Generates a read of signal sig
.
# File lib/HDLRuby/hdr_samples/sw_encrypt_cpusim_bench.rb, line 179 def read(code,sig) # Generate the resulting SW access. return ["mem_read(",code,"0x#{self.allocator.get(sig).to_s(16)})"] end
Also aliased as: hw_read
write(val,sig)
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Generates a write of val
to signal sig
.
# File lib/HDLRuby/hdr_samples/sw_encrypt_cpusim_bench.rb, line 185 def write(val,sig) # Generate the resulting SW access. return ["mem_write(,",code,",#{val},#{self.allocator.get(sig).to_s(16)})"] end
Also aliased as: hw_write