Type:
name: void
Type:
name: bit
SystemT:
name: reg_makeI::T_ inputs: - SignalI: name: clk type: bit - SignalI: name: rst type: bit - SignalI: name: d type: TypeVector: name: '' base: bit range: - 7 - 0 outputs: - SignalI: name: q type: TypeVector: name: '' base: bit range: - 7 - 0 - SignalI: name: qb type: TypeVector: name: '' base: bit range: - 7 - 0 inouts: [] scope: Scope: name: '' scopes: [] inners: [] systemIs: [] connections: - Connection: left: RefName: type: TypeVector: name: '' base: bit range: - 7 - 0 ref: RefThis: type: void name: qb right: Unary: type: TypeVector: name: '' base: bit range: - 7 - 0 operator: "~" child: RefName: type: TypeVector: name: '' base: bit range: - 7 - 0 ref: RefThis: type: void name: q behaviors: - Behavior: events: - Event: type: posedge ref: RefName: type: bit ref: RefThis: type: void name: clk block: Block: mode: par name: '' inners: [] statements: - Transmit: left: RefName: type: TypeVector: name: '' base: bit range: - 7 - 0 ref: RefThis: type: void name: q right: Binary: type: TypeVector: name: '' base: bit range: - 7 - 0 operator: "&" left: RefName: type: TypeVector: name: '' base: bit range: - 7 - 0 ref: RefThis: type: void name: d right: Concat: type: TypeTuple: name: '' types: - bit - bit - bit - bit - bit - bit - bit expressions: - Unary: type: bit operator: "~" child: RefName: type: bit ref: RefThis: type: void name: rst - Unary: type: bit operator: "~" child: RefName: type: bit ref: RefThis: type: void name: rst - Unary: type: bit operator: "~" child: RefName: type: bit ref: RefThis: type: void name: rst - Unary: type: bit operator: "~" child: RefName: type: bit ref: RefThis: type: void name: rst - Unary: type: bit operator: "~" child: RefName: type: bit ref: RefThis: type: void name: rst - Unary: type: bit operator: "~" child: RefName: type: bit ref: RefThis: type: void name: rst - Unary: type: bit operator: "~" child: RefName: type: bit ref: RefThis: type: void name: rst