class OrigenARM::Cores::CortexM::BaseController

Public Class Methods

new(options = {}) click to toggle source
Calls superclass method OrigenARM::Cores::BaseController::new
# File lib/origen_arm/cores/cortexm/base_cortexm/cortexm_controller.rb, line 7
def initialize(options = {})
  super
end

Public Instance Methods

core_reg_to_dcrdr(reg, options) click to toggle source

Reads the core register and places its contents in the DCRDR, but does not invoke and tester-level compares. @note This is a shortcut to a reg.read! call that masks all the bits. @todo Implement Raise condition. @raise [OrigenARM::CoreRegisterError] If reg is not a core register. @note See the implementation of write_register for additional details on the internals. @note All core registers are 32-bits. Any contents in the DCRDR will be overwritten.

# File lib/origen_arm/cores/cortexm/base_cortexm/cortexm_controller.rb, line 120
def core_reg_to_dcrdr(reg, options)
  if reg_wrapped_by_dcrsr?(reg)
    pp("Copying Core Register to DCRDR: DCRDR <- #{reg.name}.data") do
      reg(:dcrsr).bits(:regwnr).write(0)
      reg(:dcrsr).bits(:reg_sel).write(reg.address)
      reg(:dcrsr).write!
      tester.cycle(repeat: read_debug_register_delay)
    end
  else
    Origen.app.fail!(
      message:   'Method #core_reg_to_dcrdr can only be run with the core debug registers. ' \
               "Given register #{reg.is_a?(Register) ? reg.name : reg.to_s} is not classified as a core register.",
      exception: OrigenARM::CoreRegisterError
    )
  end
end
enter_debug_mode_delay!() click to toggle source

Delays for the core to to enter debug mode. @note The delay (in cycles) can be set by initializing the core

subblock parameter <code>:enter_debug_mode_delay_cycles</code>.

@note If the DUT provides the same method, that method

will be used in place of this one.
# File lib/origen_arm/cores/cortexm/base_cortexm/cortexm_controller.rb, line 16
def enter_debug_mode_delay!
  if dut.respond_to?('enter_debug_mode_delay!'.to_sym)
    cc 'Using DUT-defined #enter_debug_mode_delay! for core to enter debug mode'
    dut.enter_debug_mode_delay!
  else
    cc "Delaying #{enter_debug_mode_delay_cycles} cycles for core to enter debug mode"
    tester.cycle(repeat: enter_debug_mode_delay_cycles)
  end
end
exit_debug_mode_delay!() click to toggle source

Delays for the core to to exit debug mode. @note The delay (in cycles) can be set by initializing the core

subblock parameter <code>:exit_debug_mode_delay_cycles</code>.

@note If the DUT provides the same method, that method

will be used in place of this one.
# File lib/origen_arm/cores/cortexm/base_cortexm/cortexm_controller.rb, line 31
def exit_debug_mode_delay!
  if dut.respond_to?('exit_debug_mode_delay!'.to_sym)
    cc 'Using DUT-defined #exit_debug_mode_delay! for core to exit debug mode'
    dut.exit_debug_mode_delay!
  else
    cc "Delaying #{exit_debug_mode_delay_cycles} cycles for core to exit debug mode"
    tester.cycle(repeat: exit_debug_mode_delay_cycles)
  end
end
in_debug_mode(with_core_halted: false) { || ... } click to toggle source

Runs the given block in debug mode, exiting debug mode upon completion. @param with_core_halted [true, false] Indicates if the core should be halted while executing the given blocck.

If true, the core will be released upon debug mode exit.

@note This is equivalent to:

-> <code>enter_debug_mode(halt_core: with_core_halted)</code> <br>
-> <code>...</code> <br>
-> <code>exit_debug_mode(release_core: with_core_halted)</code>

@example Perform a write/read-expect operation on dut.core(:reg1)

dut.core.in_debug_mode do
  dut.core.reg(:reg7).write!(0x7)
  dut.core.reg(:reg7).read!(0x7)
end
# File lib/origen_arm/cores/cortexm/base_cortexm/cortexm_controller.rb, line 53
def in_debug_mode(with_core_halted: false)
  enter_debug_mode(halt_core: with_core_halted)
  yield
  exit_debug_mode(release_core: with_core_halted)
end
read_register(reg, options = {}) click to toggle source

Certain registers within the core must be written in certain ways. Override the reg.read! and reg.write! methods to have Origen handle this. @note This doesn't protect from the user copying the register to a different namepace,

nor from using the address directly.

@note This method will use the toplevel's reg.read!.

This is just wraps the write process for certain registers.

@see Link: <a href='

# File lib/origen_arm/cores/cortexm/base_cortexm/cortexm_controller.rb, line 101
def read_register(reg, options = {})
  if reg_wrapped_by_dcrsr?(reg)
    pp("Reading and Comparing Core Register: DCRDR <- #{reg.name}.data (expecting #{reg.data}") do
      core_reg_to_dcrdr(reg, options)
      reg(:dcrdr).read!(reg.data)
    end
  else
    # Nothing special about this registers. Write it as normal.
    parent.read_register(reg, options)
  end
end
reg_wrapped_by_dcrsr?(reg) click to toggle source

Checks if the register given is either a general_purpose_register, special_purpose_register, or a floating_point_register.

Read and writes to these regsters are wrapped around the DHRCR and DHRSR registers. @raise NoRegisterError If reg could not be converted to a register within the selected core. @note Register type indication is done per regster, when adding registers. This method just checks that field.

# File lib/origen_arm/cores/cortexm/base_cortexm/cortexm_controller.rb, line 142
def reg_wrapped_by_dcrsr?(reg)
  # If reg isn't an Origen register, convert it to one.
  r = reg.is_a?(Origen::Registers::Reg) ? reg : self.reg(reg)

  # The register type is a custom field stored in the registers metadata.
  r.meta[:general_purpose_register] || r.meta[:special_purpose_register] || r.meta[:floating_point_register]
end
with_debug_mode(with_core_halted: false)
Alias for: in_debug_mode