module BaseChip::Hierarchy::InstanceMethods
Public Instance Methods
classes( &blk)
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# File lib/base_chip/hierarchy.rb, line 51 def classes( &blk) ; source_language(:classes , &blk) ; end
configure()
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Calls superclass method
# File lib/base_chip/hierarchy.rb, line 30 def configure return if @configured @directory ||= "#{parent.directory}/#{name}" super end
default_directory_structure()
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# File lib/base_chip/hierarchy.rb, line 61 def default_directory_structure return if default_directory_structure_called @default_directory_structure_called = true rtl { |source| source.directories [ "#{source.block.name }/rtl" , "#{source.block.name}/#{source.configuration.name }/rtl" ] } top_rtl { |source| source.directories [ "#{source.block.name}/top_rtl" , "#{source.block.name}/#{source.configuration.name}/top_rtl" ] } gates { |source| source.directories [ "#{source.block.name }/gates" , "#{source.block.name}/#{source.configuration.name }/gates" ] } top_gates { |source| source.directories [ "#{source.block.name}/top_gates" , "#{source.block.name}/#{source.configuration.name}/top_gates" ] } testbench { |source| source.directories [ "#{source.block.name }/testbench" , "#{source.block.name}/#{source.configuration.name }/testbench" ] } top_testbench { |source| source.directories [ "#{source.block.name}/top_testbench" , "#{source.block.name}/#{source.configuration.name}/top_testbench" ] } stimulus { |source| source.directories [ "#{source.block.name }/stimulus" , "#{source.block.name}/#{source.configuration.name }/stimulus" ] } top_stimulus { |source| source.directories [ "#{source.block.name}/top_stimulus" , "#{source.block.name}/#{source.configuration.name}/top_stimulus" ] } # FIXME include directory verilog { |language| language.append_directories(language.directories.map {|d| "#{d}/#{language.name}"}); language.globs %w{*.def *.v *.vbh *.sv } } classes { |language| language. directories(language.directories.map {|d| "#{d}/#{language.name}"}); language.globs %w{ *.sv } } vhdl { |language| language. directories(language.directories.map {|d| "#{d}/#{language.name}"}); language.globs %w{ *.v *.vhd *.vhdl} } systemc { |language| language. directories(language.directories.map {|d| "#{d}/#{language.name}"}); language.globs %w{*.c } } headers { |language| language. directories(language.directories.map {|d| "#{d}/#{language.name}"}); language.globs %w{*.* } } end
default_directory_structure_called()
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# File lib/base_chip/hierarchy.rb, line 56 def default_directory_structure_called return true if @default_directory_structure_called return true if parent && parent.default_directory_structure_called false end
discover_actions()
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# File lib/base_chip/hierarchy.rb, line 37 def discover_actions ; file_glob("#{@directory}/base_chip/actions/*.rb" , /base_chip\/actions\/(\w+)\.rb$/ , :action ) end
discover_recipes()
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# File lib/base_chip/hierarchy.rb, line 39 def discover_recipes ; file_glob("#{@directory}/base_chip/recipes/*.rb" ) end
discover_test_lists()
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# File lib/base_chip/hierarchy.rb, line 38 def discover_test_lists ; file_glob("#{@directory}/base_chip/test_lists/*.rb" , /base_chip\/test_lists\/(\w+)\.rb$/ , :test_list ) end
discover_tools()
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# File lib/base_chip/hierarchy.rb, line 36 def discover_tools ; file_glob("#{@directory}/base_chip/tools/*.rb" , /base_chip\/tools\/(\w+)\.rb$/ , :tool ) end
gates( &blk)
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# File lib/base_chip/hierarchy.rb, line 43 def gates( &blk) ; source_type( :gates , &blk) ; end
headers( &blk)
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# File lib/base_chip/hierarchy.rb, line 54 def headers( &blk) ; source_language(:headers , &blk) ; end
rtl( &blk)
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# File lib/base_chip/hierarchy.rb, line 41 def rtl( &blk) ; source_type( :rtl , &blk) ; end
stimulus( &blk)
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# File lib/base_chip/hierarchy.rb, line 47 def stimulus( &blk) ; source_type( :stimulus , &blk) ; end
systemc( &blk)
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# File lib/base_chip/hierarchy.rb, line 53 def systemc( &blk) ; source_language(:systemc , &blk) ; end
testbench( &blk)
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# File lib/base_chip/hierarchy.rb, line 45 def testbench( &blk) ; source_type( :testbench , &blk) ; end
top_gates( &blk)
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# File lib/base_chip/hierarchy.rb, line 44 def top_gates( &blk) ; source_type(:top_gates , &blk) ; end
top_rtl( &blk)
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# File lib/base_chip/hierarchy.rb, line 42 def top_rtl( &blk) ; source_type(:top_rtl , &blk) ; end
top_stimulus( &blk)
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# File lib/base_chip/hierarchy.rb, line 48 def top_stimulus( &blk) ; source_type(:top_stimulus , &blk) ; end
top_testbench( &blk)
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# File lib/base_chip/hierarchy.rb, line 46 def top_testbench( &blk) ; source_type(:top_testbench , &blk) ; end
verilog( &blk)
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# File lib/base_chip/hierarchy.rb, line 50 def verilog( &blk) ; source_language(:verilog , &blk) ; end
vhdl( &blk)
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# File lib/base_chip/hierarchy.rb, line 52 def vhdl( &blk) ; source_language(:vhdl , &blk) ; end