Processor Counter Monitor
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![]() ![]() | Interface to access client bandwidth counters |
![]() ![]() | Implementation of a POSIX thread that periodically saves the current state of counters and exposes them to other threads |
![]() ![]() | The bulk of PCM implementation |
![]() ![]() | Main CPU counters header |
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![]() ![]() | Interface to access memory mapped IO registers |
![]() ![]() | Low level interface to access hardware model specific registers |
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![]() ![]() | Low level interface to access PCI configuration space |
![]() ![]() | Example of using CPU counters: implements a performance counter monitoring utility for Intel Core, Offcore events |
![]() ![]() | Example of using CPU counters: implements a performance counter monitoring utility for memory controller channels and DIMMs (ranks) + PMM memory traffic |
![]() ![]() | Example of using CPU counters: implements a performance counter monitoring utility for NUMA (remote and local memory accesses counting). Example for programming offcore response events |
![]() ![]() | Example of using uncore CBo counters: implements a performance counter monitoring utility for monitoring PCIe bandwidth |
![]() ![]() | Example of using CPU counters: implements a graphical plugin for KDE ksysguard |
![]() ![]() | Example of using CPU counters: implements a performance counter monitoring utility for Intel Transactional Synchronization Extensions |
![]() ![]() | Example of using CPU counters: implements a simple performance counter monitoring utility |
![]() ![]() | Two use-cases: realtime data structure performance analysis and memory-bandwidth aware scheduling |
![]() ![]() | Internal type and constant definitions |
![]() ![]() | Some common utility routines |
![]() ![]() | Provides 64-bit "virtual" counters from underlying 32-bit HW counters |