/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * Based on code from the open source mt76 driver with minor modifications.
 *
 * Copyright (C) 2021 Severin von Wnuck-Lipinski <severinvonw@outlook.de>
 *
 * Special thanks to the authors of the mt76 driver:
 *
 * Copyright (C) Felix Fietkau <nbd@nbd.name>
 * Copyright (C) Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
 * Copyright (C) Stanislaw Gruszka <stf_xl@wp.pl>
 */

#pragma once

#include <linux/types.h>

#define MT_ASIC_VERSION 0x0000

#define MT_CMB_CTRL 0x0020
#define MT_CMB_CTRL_XTAL_RDY BIT(22)
#define MT_CMB_CTRL_PLL_LD BIT(23)

#define MT_EFUSE_CTRL 0x0024
#define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
#define MT_EFUSE_CTRL_MODE GENMASK(7, 6)
#define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)
#define MT_EFUSE_CTRL_LDO_ON_TIME GENMASK(15, 14)
#define MT_EFUSE_CTRL_AIN GENMASK(25, 16)
#define MT_EFUSE_CTRL_KICK BIT(30)
#define MT_EFUSE_CTRL_SEL BIT(31)

#define MT_EFUSE_DATA_BASE 0x0028
#define MT_EFUSE_DATA(n) (MT_EFUSE_DATA_BASE + ((n) << 2))

#define MT_COEXCFG0 0x0040
#define MT_COEXCFG0_COEX_EN BIT(0)

#define MT_WLAN_FUN_CTRL 0x0080
#define MT_WLAN_FUN_CTRL_WLAN_EN BIT(0)
#define MT_WLAN_FUN_CTRL_WLAN_CLK_EN BIT(1)
#define MT_WLAN_FUN_CTRL_WLAN_RESET_RF BIT(2)

#define MT_COEXCFG3 0x004c

#define MT_LDO_CTRL_0 0x006c
#define MT_LDO_CTRL_1 0x0070

#define MT_WLAN_FUN_CTRL_CSR_F20M_CKEN BIT(3)

#define MT_WLAN_FUN_CTRL_PCIE_CLK_REQ BIT(4)
#define MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL BIT(5)
#define MT_WLAN_FUN_CTRL_INV_ANT_SEL BIT(6)
#define MT_WLAN_FUN_CTRL_WAKE_HOST BIT(7)

#define MT_WLAN_FUN_CTRL_THERM_RST BIT(8)
#define MT_WLAN_FUN_CTRL_THERM_CKEN BIT(9)

#define MT_XO_CTRL0 0x0100
#define MT_XO_CTRL1 0x0104
#define MT_XO_CTRL2 0x0108
#define MT_XO_CTRL3 0x010c
#define MT_XO_CTRL4 0x0110

#define MT_XO_CTRL5 0x0114
#define MT_XO_CTRL5_C2_VAL GENMASK(14, 8)

#define MT_XO_CTRL6 0x0118
#define MT_XO_CTRL6_C2_CTRL GENMASK(14, 8)

#define MT_XO_CTRL7 0x011c

#define MT_IOCFG_6 0x0124

#define MT_USB_U3DMA_CFG 0x9018
#define MT_USB_DMA_CFG_RX_BULK_AGG_TOUT GENMASK(7, 0)
#define MT_USB_DMA_CFG_RX_BULK_AGG_LMT GENMASK(15, 8)
#define MT_USB_DMA_CFG_UDMA_TX_WL_DROP BIT(16)
#define MT_USB_DMA_CFG_WAKE_UP_EN BIT(17)
#define MT_USB_DMA_CFG_RX_DROP_OR_PAD BIT(18)
#define MT_USB_DMA_CFG_TX_CLR BIT(19)
#define MT_USB_DMA_CFG_TXOP_HALT BIT(20)
#define MT_USB_DMA_CFG_RX_BULK_AGG_EN BIT(21)
#define MT_USB_DMA_CFG_RX_BULK_EN BIT(22)
#define MT_USB_DMA_CFG_TX_BULK_EN BIT(23)
#define MT_USB_DMA_CFG_EP_OUT_VALID GENMASK(29, 24)
#define MT_USB_DMA_CFG_RX_BUSY BIT(30)
#define MT_USB_DMA_CFG_TX_BUSY BIT(31)

#define MT_WLAN_MTC_CTRL 0x010148
#define MT_WLAN_MTC_CTRL_MTCMOS_PWR_UP BIT(0)
#define MT_WLAN_MTC_CTRL_PWR_ACK BIT(12)
#define MT_WLAN_MTC_CTRL_PWR_ACK_S BIT(13)
#define MT_WLAN_MTC_CTRL_BBP_MEM_PD GENMASK(19, 16)
#define MT_WLAN_MTC_CTRL_PBF_MEM_PD BIT(20)
#define MT_WLAN_MTC_CTRL_FCE_MEM_PD BIT(21)
#define MT_WLAN_MTC_CTRL_TSO_MEM_PD BIT(22)
#define MT_WLAN_MTC_CTRL_BBP_MEM_RB BIT(24)
#define MT_WLAN_MTC_CTRL_PBF_MEM_RB BIT(25)
#define MT_WLAN_MTC_CTRL_FCE_MEM_RB BIT(26)
#define MT_WLAN_MTC_CTRL_TSO_MEM_RB BIT(27)
#define MT_WLAN_MTC_CTRL_STATE_UP BIT(28)

#define MT_INT_SOURCE_CSR 0x0200
#define MT_INT_MASK_CSR 0x0204

#define MT_INT_RX_DONE(n) BIT(n)
#define MT_INT_RX_DONE_ALL GENMASK(1, 0)
#define MT_INT_TX_DONE_ALL GENMASK(13, 4)
#define MT_INT_TX_DONE(n) BIT((n) + 4)
#define MT_INT_RX_COHERENT BIT(16)
#define MT_INT_TX_COHERENT BIT(17)
#define MT_INT_ANY_COHERENT BIT(18)
#define MT_INT_MCU_CMD BIT(19)
#define MT_INT_TBTT BIT(20)
#define MT_INT_PRE_TBTT BIT(21)
#define MT_INT_TX_STAT BIT(22)
#define MT_INT_AUTO_WAKEUP BIT(23)
#define MT_INT_GPTIMER BIT(24)
#define MT_INT_RXDELAYINT BIT(26)
#define MT_INT_TXDELAYINT BIT(27)

#define MT_WPDMA_GLO_CFG 0x0208
#define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0)
#define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1)
#define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2)
#define MT_WPDMA_GLO_CFG_RX_DMA_BUSY BIT(3)
#define MT_WPDMA_GLO_CFG_DMA_BURST_SIZE GENMASK(5, 4)
#define MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE BIT(6)
#define MT_WPDMA_GLO_CFG_BIG_ENDIAN BIT(7)
#define MT_WPDMA_GLO_CFG_HDR_SEG_LEN GENMASK(15, 8)
#define MT_WPDMA_GLO_CFG_CLK_GATE_DIS BIT(30)
#define MT_WPDMA_GLO_CFG_RX_2B_OFFSET BIT(31)

#define MT_WPDMA_RST_IDX 0x020c

#define MT_WPDMA_DELAY_INT_CFG 0x0210

#define MT_WMM_AIFSN 0x0214
#define MT_WMM_AIFSN_MASK GENMASK(3, 0)
#define MT_WMM_AIFSN_SHIFT(n) ((n) * 4)

#define MT_WMM_CWMIN 0x0218
#define MT_WMM_CWMIN_MASK GENMASK(3, 0)
#define MT_WMM_CWMIN_SHIFT(n) ((n) * 4)

#define MT_WMM_CWMAX 0x021c
#define MT_WMM_CWMAX_MASK GENMASK(3, 0)
#define MT_WMM_CWMAX_SHIFT(n) ((n) * 4)

#define MT_WMM_TXOP_BASE 0x0220
#define MT_WMM_TXOP(n) (MT_WMM_TXOP_BASE + (((n) / 2) << 2))
#define MT_WMM_TXOP_SHIFT(n) (((n) & 1) * 16)
#define MT_WMM_TXOP_MASK GENMASK(15, 0)

#define MT_FCE_DMA_ADDR 0x0230
#define MT_FCE_DMA_LEN 0x0234
#define MT_USB_DMA_CFG 0x0238

#define MT_TSO_CTRL 0x0250
#define MT_HEADER_TRANS_CTRL_REG 0x0260

#define MT_US_CYC_CFG 0x02a4
#define MT_US_CYC_CNT GENMASK(7, 0)

#define MT_TX_RING_BASE 0x0300
#define MT_RX_RING_BASE 0x03c0

#define MT_PBF_SYS_CTRL 0x0400
#define MT_PBF_SYS_CTRL_MCU_RESET BIT(0)
#define MT_PBF_SYS_CTRL_DMA_RESET BIT(1)
#define MT_PBF_SYS_CTRL_MAC_RESET BIT(2)
#define MT_PBF_SYS_CTRL_PBF_RESET BIT(3)
#define MT_PBF_SYS_CTRL_ASY_RESET BIT(4)

#define MT_PBF_CFG 0x0404
#define MT_PBF_CFG_TX0Q_EN BIT(0)
#define MT_PBF_CFG_TX1Q_EN BIT(1)
#define MT_PBF_CFG_TX2Q_EN BIT(2)
#define MT_PBF_CFG_TX3Q_EN BIT(3)
#define MT_PBF_CFG_RX0Q_EN BIT(4)
#define MT_PBF_CFG_RX_DROP_EN BIT(8)

#define MT_PBF_TX_MAX_PCNT 0x0408
#define MT_PBF_RX_MAX_PCNT 0x040c

#define MT_BCN_OFFSET_BASE 0x041c
#define MT_BCN_OFFSET(n) (MT_BCN_OFFSET_BASE + ((n) << 2))

#define MT_RXQ_STA 0x0430
#define MT_TXQ_STA 0x0434
#define MT_RF_CSR_CFG 0x0500
#define MT_RF_CSR_CFG_DATA GENMASK(7, 0)
#define MT_RF_CSR_CFG_REG_ID GENMASK(14, 8)
#define MT_RF_CSR_CFG_REG_BANK GENMASK(17, 15)
#define MT_RF_CSR_CFG_WR BIT(30)
#define MT_RF_CSR_CFG_KICK BIT(31)

#define MT_RF_BYPASS_0 0x0504
#define MT_RF_BYPASS_1 0x0508
#define MT_RF_SETTING_0 0x050c

#define MT_RF_MISC 0x0518
#define MT_RF_DATA_WRITE 0x0524

#define MT_RF_CTRL 0x0528
#define MT_RF_CTRL_ADDR GENMASK(11, 0)
#define MT_RF_CTRL_WRITE BIT(12)
#define MT_RF_CTRL_BUSY BIT(13)
#define MT_RF_CTRL_IDX BIT(16)

#define MT_RF_DATA_READ 0x052c

#define MT_COM_REG0 0x0730
#define MT_COM_REG1 0x0734
#define MT_COM_REG2 0x0738
#define MT_COM_REG3 0x073c

#define MT_LED_CTRL 0x0770
#define MT_LED_CTRL_REPLAY(n) BIT(0 + (8 * (n)))
#define MT_LED_CTRL_POLARITY(n) BIT(1 + (8 * (n)))
#define MT_LED_CTRL_TX_BLINK_MODE(n) BIT(2 + (8 * (n)))
#define MT_LED_CTRL_KICK(n) BIT(7 + (8 * (n)))

#define MT_LED_TX_BLINK_0 0x0774
#define MT_LED_TX_BLINK_1 0x0778

#define MT_LED_S0_BASE 0x077c
#define MT_LED_S0(n) (MT_LED_S0_BASE + 8 * (n))
#define MT_LED_S1_BASE 0x0780
#define MT_LED_S1(n) (MT_LED_S1_BASE + 8 * (n))
#define MT_LED_STATUS_OFF GENMASK(31, 24)
#define MT_LED_STATUS_ON GENMASK(23, 16)
#define MT_LED_STATUS_DURATION GENMASK(15, 8)

#define MT_FCE_PSE_CTRL 0x0800
#define MT_FCE_PARAMETERS 0x0804
#define MT_FCE_CSO 0x0808

#define MT_FCE_L2_STUFF 0x080c
#define MT_FCE_L2_STUFF_HT_L2_EN BIT(0)
#define MT_FCE_L2_STUFF_QOS_L2_EN BIT(1)
#define MT_FCE_L2_STUFF_RX_STUFF_EN BIT(2)
#define MT_FCE_L2_STUFF_TX_STUFF_EN BIT(3)
#define MT_FCE_L2_STUFF_WR_MPDU_LEN_EN BIT(4)
#define MT_FCE_L2_STUFF_MVINV_BSWAP BIT(5)
#define MT_FCE_L2_STUFF_TS_CMD_QSEL_EN GENMASK(15, 8)
#define MT_FCE_L2_STUFF_TS_LEN_EN GENMASK(23, 16)
#define MT_FCE_L2_STUFF_OTHER_PORT GENMASK(25, 24)

#define MT_FCE_WLAN_FLOW_CONTROL1 0x0824

#define MT_TX_CPU_FROM_FCE_BASE_PTR 0x09a0
#define MT_TX_CPU_FROM_FCE_MAX_COUNT 0x09a4
#define MT_TX_CPU_FROM_FCE_CPU_DESC_IDX 0x09a8
#define MT_FCE_PDMA_GLOBAL_CONF 0x09c4
#define MT_FCE_SKIP_FS 0x0a6c

#define MT_PAUSE_ENABLE_CONTROL1 0x0a38

#define MT_MAC_CSR0 0x1000

#define MT_MAC_SYS_CTRL 0x1004
#define MT_MAC_SYS_CTRL_RESET_CSR BIT(0)
#define MT_MAC_SYS_CTRL_RESET_BBP BIT(1)
#define MT_MAC_SYS_CTRL_ENABLE_TX BIT(2)
#define MT_MAC_SYS_CTRL_ENABLE_RX BIT(3)

#define MT_MAC_ADDR_DW0 0x1008
#define MT_MAC_ADDR_DW1 0x100c
#define MT_MAC_ADDR_DW1_U2ME_MASK GENMASK(23, 16)

#define MT_MAC_BSSID_DW0 0x1010
#define MT_MAC_BSSID_DW1 0x1014
#define MT_MAC_BSSID_DW1_ADDR GENMASK(15, 0)
#define MT_MAC_BSSID_DW1_MBSS_MODE GENMASK(17, 16)
#define MT_MAC_BSSID_DW1_MBEACON_N GENMASK(20, 18)
#define MT_MAC_BSSID_DW1_MBSS_LOCAL_BIT BIT(21)
#define MT_MAC_BSSID_DW1_MBSS_MODE_B2 BIT(22)
#define MT_MAC_BSSID_DW1_MBEACON_N_B3 BIT(23)
#define MT_MAC_BSSID_DW1_MBSS_IDX_BYTE GENMASK(26, 24)

#define MT_MAX_LEN_CFG 0x1018
#define MT_MAX_LEN_CFG_AMPDU GENMASK(13, 12)

#define MT_LED_CFG 0x102c

#define MT_AMPDU_MAX_LEN_20M1S 0x1030
#define MT_AMPDU_MAX_LEN_20M2S 0x1034
#define MT_AMPDU_MAX_LEN_40M1S 0x1038
#define MT_AMPDU_MAX_LEN_40M2S 0x103c
#define MT_AMPDU_MAX_LEN 0x1040

#define MT_WCID_DROP_BASE 0x106c
#define MT_WCID_DROP(n) (MT_WCID_DROP_BASE + ((n) >> 5) * 4)
#define MT_WCID_DROP_MASK(n) BIT((n) % 32)

#define MT_BCN_BYPASS_MASK 0x108c

#define MT_MAC_APC_BSSID_BASE 0x1090
#define MT_MAC_APC_BSSID_L(n) (MT_MAC_APC_BSSID_BASE + ((n) * 8))
#define MT_MAC_APC_BSSID_H(n) (MT_MAC_APC_BSSID_BASE + ((n) * 8 + 4))
#define MT_MAC_APC_BSSID_H_ADDR GENMASK(15, 0)
#define MT_MAC_APC_BSSID0_H_EN BIT(16)

#define MT_XIFS_TIME_CFG 0x1100
#define MT_XIFS_TIME_CFG_CCK_SIFS GENMASK(7, 0)
#define MT_XIFS_TIME_CFG_OFDM_SIFS GENMASK(15, 8)
#define MT_XIFS_TIME_CFG_OFDM_XIFS GENMASK(19, 16)
#define MT_XIFS_TIME_CFG_EIFS GENMASK(28, 20)
#define MT_XIFS_TIME_CFG_BB_RXEND_EN BIT(29)

#define MT_BKOFF_SLOT_CFG 0x1104
#define MT_BKOFF_SLOT_CFG_SLOTTIME GENMASK(7, 0)
#define MT_BKOFF_SLOT_CFG_CC_DELAY GENMASK(11, 8)

#define MT_CH_TIME_CFG 0x110c
#define MT_CH_TIME_CFG_TIMER_EN BIT(0)
#define MT_CH_TIME_CFG_TX_AS_BUSY BIT(1)
#define MT_CH_TIME_CFG_RX_AS_BUSY BIT(2)
#define MT_CH_TIME_CFG_NAV_AS_BUSY BIT(3)
#define MT_CH_TIME_CFG_EIFS_AS_BUSY BIT(4)
#define MT_CH_TIME_CFG_MDRDY_CNT_EN BIT(5)
#define MT_CH_CCA_RC_EN BIT(6)
#define MT_CH_TIME_CFG_CH_TIMER_CLR GENMASK(9, 8)
#define MT_CH_TIME_CFG_MDRDY_CLR GENMASK(11, 10)

#define MT_PBF_LIFE_TIMER 0x1110

#define MT_BEACON_TIME_CFG 0x1114
#define MT_BEACON_TIME_CFG_INTVAL GENMASK(15, 0)
#define MT_BEACON_TIME_CFG_TIMER_EN BIT(16)
#define MT_BEACON_TIME_CFG_SYNC_MODE GENMASK(18, 17)
#define MT_BEACON_TIME_CFG_TBTT_EN BIT(19)
#define MT_BEACON_TIME_CFG_BEACON_TX BIT(20)
#define MT_BEACON_TIME_CFG_TSF_COMP GENMASK(31, 24)

#define MT_TBTT_SYNC_CFG 0x1118
#define MT_TSF_TIMER_DW0 0x111c
#define MT_TSF_TIMER_DW1 0x1120
#define MT_TBTT_TIMER 0x1124
#define MT_TBTT_TIMER_VAL GENMASK(16, 0)

#define MT_INT_TIMER_CFG 0x1128
#define MT_INT_TIMER_CFG_PRE_TBTT GENMASK(15, 0)
#define MT_INT_TIMER_CFG_GP_TIMER GENMASK(31, 16)

#define MT_INT_TIMER_EN 0x112c
#define MT_INT_TIMER_EN_PRE_TBTT_EN BIT(0)
#define MT_INT_TIMER_EN_GP_TIMER_EN BIT(1)

#define MT_CH_IDLE 0x1130
#define MT_CH_BUSY 0x1134
#define MT_EXT_CH_BUSY 0x1138
#define MT_ED_CCA_TIMER 0x1140

#define MT_MAC_STATUS 0x1200
#define MT_MAC_STATUS_TX BIT(0)
#define MT_MAC_STATUS_RX BIT(1)

#define MT_PWR_PIN_CFG 0x1204
#define MT_AUX_CLK_CFG 0x120c

#define MT_BB_PA_MODE_CFG0 0x1214
#define MT_BB_PA_MODE_CFG1 0x1218
#define MT_RF_PA_MODE_CFG0 0x121c
#define MT_RF_PA_MODE_CFG1 0x1220

#define MT_RF_PA_MODE_ADJ0 0x1228
#define MT_RF_PA_MODE_ADJ1 0x122c

#define MT_DACCLK_EN_DLY_CFG 0x1264

#define MT_EDCA_CFG_BASE 0x1300
#define MT_EDCA_CFG_AC(n) (MT_EDCA_CFG_BASE + ((n) << 2))
#define MT_EDCA_CFG_TXOP GENMASK(7, 0)
#define MT_EDCA_CFG_AIFSN GENMASK(11, 8)
#define MT_EDCA_CFG_CWMIN GENMASK(15, 12)
#define MT_EDCA_CFG_CWMAX GENMASK(19, 16)

#define MT_TX_PWR_CFG_0 0x1314
#define MT_TX_PWR_CFG_1 0x1318
#define MT_TX_PWR_CFG_2 0x131c
#define MT_TX_PWR_CFG_3 0x1320
#define MT_TX_PWR_CFG_4 0x1324
#define MT_TX_PIN_CFG 0x1328
#define MT_TX_PIN_CFG_TXANT GENMASK(3, 0)
#define MT_TX_PIN_CFG_RXANT GENMASK(11, 8)
#define MT_TX_PIN_RFTR_EN BIT(16)
#define MT_TX_PIN_TRSW_EN BIT(18)

#define MT_TX_BAND_CFG 0x132c
#define MT_TX_BAND_CFG_UPPER_40M BIT(0)
#define MT_TX_BAND_CFG_5G BIT(1)
#define MT_TX_BAND_CFG_2G BIT(2)

#define MT_HT_FBK_TO_LEGACY 0x1384
#define MT_TX_MPDU_ADJ_INT 0x1388

#define MT_TX_PWR_CFG_7 0x13d4
#define MT_TX_PWR_CFG_8 0x13d8
#define MT_TX_PWR_CFG_9 0x13dc

#define MT_TX_SW_CFG0 0x1330
#define MT_TX_SW_CFG1 0x1334
#define MT_TX_SW_CFG2 0x1338

#define MT_TXOP_CTRL_CFG 0x1340
#define MT_TXOP_TRUN_EN GENMASK(5, 0)
#define MT_TXOP_EXT_CCA_DLY GENMASK(15, 8)
#define MT_TXOP_ED_CCA_EN BIT(20)

#define MT_TX_RTS_CFG 0x1344
#define MT_TX_RTS_CFG_RETRY_LIMIT GENMASK(7, 0)
#define MT_TX_RTS_CFG_THRESH GENMASK(23, 8)
#define MT_TX_RTS_FALLBACK BIT(24)

#define MT_TX_TIMEOUT_CFG 0x1348
#define MT_TX_TIMEOUT_CFG_ACKTO GENMASK(15, 8)

#define MT_TX_RETRY_CFG 0x134c
#define MT_TX_LINK_CFG 0x1350
#define MT_TX_CFACK_EN BIT(12)
#define MT_VHT_HT_FBK_CFG0 0x1354
#define MT_VHT_HT_FBK_CFG1 0x1358
#define MT_LG_FBK_CFG0 0x135c
#define MT_LG_FBK_CFG1 0x1360

#define MT_PROT_CFG_RATE GENMASK(15, 0)
#define MT_PROT_CFG_CTRL GENMASK(17, 16)
#define MT_PROT_CFG_NAV GENMASK(19, 18)
#define MT_PROT_CFG_TXOP_ALLOW GENMASK(25, 20)
#define MT_PROT_CFG_RTS_THRESH BIT(26)

#define MT_CCK_PROT_CFG 0x1364
#define MT_OFDM_PROT_CFG 0x1368
#define MT_MM20_PROT_CFG 0x136c
#define MT_MM40_PROT_CFG 0x1370
#define MT_GF20_PROT_CFG 0x1374
#define MT_GF40_PROT_CFG 0x1378

#define MT_PROT_RATE GENMASK(15, 0)
#define MT_PROT_CTRL_RTS_CTS BIT(16)
#define MT_PROT_CTRL_CTS2SELF BIT(17)
#define MT_PROT_NAV_SHORT BIT(18)
#define MT_PROT_NAV_LONG BIT(19)
#define MT_PROT_TXOP_ALLOW_CCK BIT(20)
#define MT_PROT_TXOP_ALLOW_OFDM BIT(21)
#define MT_PROT_TXOP_ALLOW_MM20 BIT(22)
#define MT_PROT_TXOP_ALLOW_MM40 BIT(23)
#define MT_PROT_TXOP_ALLOW_GF20 BIT(24)
#define MT_PROT_TXOP_ALLOW_GF40 BIT(25)
#define MT_PROT_RTS_THR_EN BIT(26)
#define MT_PROT_RATE_CCK_11 0x0003
#define MT_PROT_RATE_OFDM_6 0x2000
#define MT_PROT_RATE_OFDM_24 0x2004
#define MT_PROT_RATE_DUP_OFDM_24 0x2084
#define MT_PROT_RATE_SGI_OFDM_24 0x2104
#define MT_PROT_TXOP_ALLOW_ALL GENMASK(25, 20)
#define MT_PROT_TXOP_ALLOW_BW20 (MT_PROT_TXOP_ALLOW_ALL & \
	~MT_PROT_TXOP_ALLOW_MM40 & \
	~MT_PROT_TXOP_ALLOW_GF40)

#define MT_EXP_ACK_TIME 0x1380

#define MT_TX_PWR_CFG_0_EXT 0x1390
#define MT_TX_PWR_CFG_1_EXT 0x1394

#define MT_TX_FBK_LIMIT 0x1398
#define MT_TX_FBK_LIMIT_MPDU_FBK GENMASK(7, 0)
#define MT_TX_FBK_LIMIT_AMPDU_FBK GENMASK(15, 8)
#define MT_TX_FBK_LIMIT_MPDU_UP_CLEAR BIT(16)
#define MT_TX_FBK_LIMIT_AMPDU_UP_CLEAR BIT(17)
#define MT_TX_FBK_LIMIT_RATE_LUT BIT(18)

#define MT_TX0_RF_GAIN_CORR 0x13a0
#define MT_TX1_RF_GAIN_CORR 0x13a4
#define MT_TX0_RF_GAIN_ATTEN 0x13a8

#define MT_TX_ALC_CFG_0 0x13b0
#define MT_TX_ALC_CFG_0_CH_INIT_0 GENMASK(5, 0)
#define MT_TX_ALC_CFG_0_CH_INIT_1 GENMASK(13, 8)
#define MT_TX_ALC_CFG_0_LIMIT_0 GENMASK(21, 16)
#define MT_TX_ALC_CFG_0_LIMIT_1 GENMASK(29, 24)

#define MT_TX_ALC_CFG_1 0x13b4
#define MT_TX_ALC_CFG_1_TEMP_COMP GENMASK(5, 0)

#define MT_TX_ALC_CFG_2 0x13a8
#define MT_TX_ALC_CFG_2_TEMP_COMP GENMASK(5, 0)

#define MT_TX_ALC_CFG_3 0x13ac
#define MT_TX_ALC_CFG_4 0x13c0
#define MT_TX_ALC_CFG_4_LOWGAIN_CH_EN BIT(31)

#define MT_TX_ALC_VGA3 0x13c8

#define MT_TX_PROT_CFG6 0x13e0
#define MT_TX_PROT_CFG7 0x13e4
#define MT_TX_PROT_CFG8 0x13e8

#define MT_PIFS_TX_CFG 0x13ec

#define MT_RX_FILTR_CFG 0x1400

#define MT_RX_FILTR_CFG_CRC_ERR BIT(0)
#define MT_RX_FILTR_CFG_PHY_ERR BIT(1)
#define MT_RX_FILTR_CFG_PROMISC BIT(2)
#define MT_RX_FILTR_CFG_OTHER_BSS BIT(3)
#define MT_RX_FILTR_CFG_VER_ERR BIT(4)
#define MT_RX_FILTR_CFG_MCAST BIT(5)
#define MT_RX_FILTR_CFG_BCAST BIT(6)
#define MT_RX_FILTR_CFG_DUP BIT(7)
#define MT_RX_FILTR_CFG_CFACK BIT(8)
#define MT_RX_FILTR_CFG_CFEND BIT(9)
#define MT_RX_FILTR_CFG_ACK BIT(10)
#define MT_RX_FILTR_CFG_CTS BIT(11)
#define MT_RX_FILTR_CFG_RTS BIT(12)
#define MT_RX_FILTR_CFG_PSPOLL BIT(13)
#define MT_RX_FILTR_CFG_BA BIT(14)
#define MT_RX_FILTR_CFG_BAR BIT(15)
#define MT_RX_FILTR_CFG_CTRL_RSV BIT(16)

#define MT_AUTO_RSP_CFG 0x1404
#define MT_AUTO_RSP_EN BIT(0)
#define MT_AUTO_RSP_PREAMB_SHORT BIT(4)
#define MT_LEGACY_BASIC_RATE 0x1408
#define MT_HT_BASIC_RATE 0x140c

#define MT_HT_CTRL_CFG 0x1410
#define MT_RX_PARSER_CFG 0x1418
#define MT_RX_PARSER_RX_SET_NAV_ALL BIT(0)

#define MT_EXT_CCA_CFG 0x141c
#define MT_EXT_CCA_CFG_CCA0 GENMASK(1, 0)
#define MT_EXT_CCA_CFG_CCA1 GENMASK(3, 2)
#define MT_EXT_CCA_CFG_CCA2 GENMASK(5, 4)
#define MT_EXT_CCA_CFG_CCA3 GENMASK(7, 6)
#define MT_EXT_CCA_CFG_CCA_MASK GENMASK(11, 8)
#define MT_EXT_CCA_CFG_ED_CCA_MASK GENMASK(15, 12)

#define MT_TX_SW_CFG3 0x1478

#define MT_PN_PAD_MODE 0x150c

#define MT_TXOP_HLDR_ET 0x1608
#define MT_TXOP_HLDR_TX40M_BLK_EN BIT(1)

#define MT_PROT_AUTO_TX_CFG 0x1648
#define MT_PROT_AUTO_TX_CFG_PROT_PADJ GENMASK(11, 8)
#define MT_PROT_AUTO_TX_CFG_AUTO_PADJ GENMASK(27, 24)

#define MT_RX_STAT_0 0x1700
#define MT_RX_STAT_0_CRC_ERRORS GENMASK(15, 0)
#define MT_RX_STAT_0_PHY_ERRORS GENMASK(31, 16)

#define MT_RX_STAT_1 0x1704
#define MT_RX_STAT_1_CCA_ERRORS GENMASK(15, 0)
#define MT_RX_STAT_1_PLCP_ERRORS GENMASK(31, 16)

#define MT_RX_STAT_2 0x1708
#define MT_RX_STAT_2_DUP_ERRORS GENMASK(15, 0)
#define MT_RX_STAT_2_OVERFLOW_ERRORS GENMASK(31, 16)

#define MT_TX_STA_0 0x170c
#define MT_TX_STA_1 0x1710
#define MT_TX_STA_2 0x1714

#define MT_TX_STAT_FIFO 0x1718
#define MT_TX_STAT_FIFO_VALID BIT(0)
#define MT_TX_STAT_FIFO_SUCCESS BIT(5)
#define MT_TX_STAT_FIFO_AGGR BIT(6)
#define MT_TX_STAT_FIFO_ACKREQ BIT(7)
#define MT_TX_STAT_FIFO_WCID GENMASK(15, 8)
#define MT_TX_STAT_FIFO_RATE GENMASK(31, 16)

#define MT_TX_AGG_STAT 0x171c

#define MT_TX_AGG_CNT_BASE0 0x1720
#define MT_MPDU_DENSITY_CNT 0x1740
#define MT_TX_AGG_CNT_BASE1 0x174c

#define MT_TX_STAT_FIFO_EXT 0x1798
#define MT_TX_STAT_FIFO_EXT_RETRY GENMASK(7, 0)
#define MT_TX_STAT_FIFO_EXT_PKTID GENMASK(15, 8)

#define MT_WCID_TX_RATE_BASE 0x1c00
#define MT_WCID_TX_RATE(i) (MT_WCID_TX_RATE_BASE + ((i) << 3))

#define MT_BBP_CORE_BASE 0x2000
#define MT_BBP_IBI_BASE 0x2100
#define MT_BBP_AGC_BASE 0x2300
#define MT_BBP_TXC_BASE 0x2400
#define MT_BBP_RXC_BASE 0x2500
#define MT_BBP_TXO_BASE 0x2600
#define MT_BBP_TXBE_BASE 0x2700
#define MT_BBP_RXFE_BASE 0x2800
#define MT_BBP_RXO_BASE 0x2900
#define MT_BBP_DFS_BASE 0x2a00
#define MT_BBP_TR_BASE 0x2b00
#define MT_BBP_CAL_BASE 0x2c00
#define MT_BBP_DSC_BASE 0x2e00
#define MT_BBP_PFMU_BASE 0x2f00

#define MT_BBP(type, n) (MT_BBP_##type##_BASE + ((n) << 2))

#define MT_BBP_CORE_R1_BW GENMASK(4, 3)

#define MT_BBP_AGC_R0_CTRL_CHAN GENMASK(9, 8)
#define MT_BBP_AGC_R0_BW GENMASK(14, 12)

/* AGC, R4/R5 */
#define MT_BBP_AGC_LNA_HIGH_GAIN GENMASK(21, 16)
#define MT_BBP_AGC_LNA_MID_GAIN GENMASK(13, 8)
#define MT_BBP_AGC_LNA_LOW_GAIN GENMASK(5, 0)

/* AGC, R6/R7 */
#define MT_BBP_AGC_LNA_ULOW_GAIN GENMASK(5, 0)

/* AGC, R8/R9 */
#define MT_BBP_AGC_LNA_GAIN_MODE GENMASK(7, 6)
#define MT_BBP_AGC_GAIN GENMASK(14, 8)

#define MT_BBP_AGC20_RSSI0 GENMASK(7, 0)
#define MT_BBP_AGC20_RSSI1 GENMASK(15, 8)

#define MT_BBP_TXBE_R0_CTRL_CHAN GENMASK(1, 0)

#define MT_WCID_ADDR_BASE 0x1800
#define MT_WCID_ADDR(n) (MT_WCID_ADDR_BASE + (n) * 8)

#define MT_SRAM_BASE 0x4000

#define MT_WCID_KEY_BASE 0x8000
#define MT_WCID_KEY(n) (MT_WCID_KEY_BASE + (n) * 32)

#define MT_WCID_IV_BASE 0xa000
#define MT_WCID_IV(n) (MT_WCID_IV_BASE + (n) * 8)

#define MT_WCID_ATTR_BASE 0xa800
#define MT_WCID_ATTR(n) (MT_WCID_ATTR_BASE + (n) * 4)

#define MT_WCID_ATTR_PAIRWISE BIT(0)
#define MT_WCID_ATTR_PKEY_MODE GENMASK(3, 1)
#define MT_WCID_ATTR_BSS_IDX GENMASK(6, 4)
#define MT_WCID_ATTR_RXWI_UDF GENMASK(9, 7)
#define MT_WCID_ATTR_PKEY_MODE_EXT BIT(10)
#define MT_WCID_ATTR_BSS_IDX_EXT BIT(11)
#define MT_WCID_ATTR_WAPI_MCBC BIT(15)
#define MT_WCID_ATTR_WAPI_KEYID GENMASK(31, 24)

#define MT_SKEY_BASE_0 0xac00
#define MT_SKEY_BASE_1 0xb400
#define MT_SKEY_0(bss, idx) (MT_SKEY_BASE_0 + (4 * (bss) + (idx)) * 32)
#define MT_SKEY_1(bss, idx) (MT_SKEY_BASE_1 + (4 * ((bss) & 7) + (idx)) * 32)

#define MT_SKEY_MODE_BASE_0 0xb000
#define MT_SKEY_MODE_BASE_1 0xb3f0
#define MT_SKEY_MODE_0(bss) (MT_SKEY_MODE_BASE_0 + (((bss) / 2) << 2))
#define MT_SKEY_MODE_1(bss) (MT_SKEY_MODE_BASE_1 + ((((bss) & 7) / 2) << 2))
#define MT_SKEY_MODE_MASK GENMASK(3, 0)
#define MT_SKEY_MODE_SHIFT(bss, idx) (4 * ((idx) + 4 * ((bss) & 1)))

#define MT_BEACON_BASE 0xc000

#define MT_TEMP_SENSOR 0x01d000
#define MT_TEMP_SENSOR_VAL GENMASK(6, 0)

#define MT_MCU_RESET_CTL 0x070c
#define MT_MCU_INT_LEVEL 0x0718
#define MT_MCU_COM_REG0 0x0730
#define MT_MCU_COM_REG1 0x0734
#define MT_MCU_COM_REG2 0x0738
#define MT_MCU_COM_REG3 0x073c

#define MT_MCU_MEMMAP_WLAN 0x410000

#define MT_TXD_INFO_LEN GENMASK(15, 0)
#define MT_TXD_INFO_NEXT_VLD BIT(16)
#define MT_TXD_INFO_TX_BURST BIT(17)
#define MT_TXD_INFO_80211 BIT(19)
#define MT_TXD_INFO_TSO BIT(20)
#define MT_TXD_INFO_CSO BIT(21)
#define MT_TXD_INFO_WIV BIT(24)
#define MT_TXD_INFO_QSEL GENMASK(26, 25)
#define MT_TXD_INFO_DPORT GENMASK(29, 27)
#define MT_TXD_INFO_TYPE GENMASK(31, 30)

#define MT_RX_FCE_INFO_LEN GENMASK(13, 0)
#define MT_RX_FCE_INFO_SELF_GEN BIT(15)
#define MT_RX_FCE_INFO_CMD_SEQ GENMASK(19, 16)
#define MT_RX_FCE_INFO_EVT_TYPE GENMASK(23, 20)
#define MT_RX_FCE_INFO_PCIE_INTR BIT(24)
#define MT_RX_FCE_INFO_QSEL GENMASK(26, 25)
#define MT_RX_FCE_INFO_D_PORT GENMASK(29, 27)
#define MT_RX_FCE_INFO_TYPE GENMASK(31, 30)

#define MT_MCU_MSG_LEN GENMASK(15, 0)
#define MT_MCU_MSG_CMD_SEQ GENMASK(19, 16)
#define MT_MCU_MSG_CMD_TYPE GENMASK(26, 20)
#define MT_MCU_MSG_PORT GENMASK(29, 27)
#define MT_MCU_MSG_TYPE GENMASK(31, 30)
#define MT_MCU_MSG_TYPE_CMD BIT(30)

#define MT_FCE_DMA_ADDR 0x0230
#define MT_FCE_DMA_LEN 0x0234

#define MT_TX_CPU_FROM_FCE_CPU_DESC_IDX 0x09a8

#define MT_PKTID_RATE GENMASK(4, 0)
#define MT_PKTID_AC GENMASK(6, 5)

#define MT_RXINFO_BA BIT(0)
#define MT_RXINFO_DATA BIT(1)
#define MT_RXINFO_NULL BIT(2)
#define MT_RXINFO_FRAG BIT(3)
#define MT_RXINFO_UNICAST BIT(4)
#define MT_RXINFO_MULTICAST BIT(5)
#define MT_RXINFO_BROADCAST BIT(6)
#define MT_RXINFO_MYBSS BIT(7)
#define MT_RXINFO_CRCERR BIT(8)
#define MT_RXINFO_ICVERR BIT(9)
#define MT_RXINFO_MICERR BIT(10)
#define MT_RXINFO_AMSDU BIT(11)
#define MT_RXINFO_HTC BIT(12)
#define MT_RXINFO_RSSI BIT(13)
#define MT_RXINFO_L2PAD BIT(14)
#define MT_RXINFO_AMPDU BIT(15)
#define MT_RXINFO_DECRYPT BIT(16)
#define MT_RXINFO_BSSIDX3 BIT(17)
#define MT_RXINFO_WAPI_KEY BIT(18)
#define MT_RXINFO_PN_LEN GENMASK(21, 19)
#define MT_RXINFO_SW_FTYPE0 BIT(22)
#define MT_RXINFO_SW_FTYPE1 BIT(23)
#define MT_RXINFO_PROBE_RESP BIT(24)
#define MT_RXINFO_BEACON BIT(25)
#define MT_RXINFO_DISASSOC BIT(26)
#define MT_RXINFO_DEAUTH BIT(27)
#define MT_RXINFO_ACTION BIT(28)
#define MT_RXINFO_TCP_SUM_ERR BIT(30)
#define MT_RXINFO_IP_SUM_ERR BIT(31)

#define MT_RXWI_CTL_WCID GENMASK(7, 0)
#define MT_RXWI_CTL_KEY_IDX GENMASK(9, 8)
#define MT_RXWI_CTL_BSS_IDX GENMASK(12, 10)
#define MT_RXWI_CTL_UDF GENMASK(15, 13)
#define MT_RXWI_CTL_MPDU_LEN GENMASK(29, 16)
#define MT_RXWI_CTL_EOF BIT(31)

#define MT_RXWI_TID GENMASK(3, 0)
#define MT_RXWI_SN GENMASK(15, 4)

#define MT_RXWI_RATE_INDEX GENMASK(5, 0)
#define MT_RXWI_RATE_LDPC BIT(6)
#define MT_RXWI_RATE_BW GENMASK(8, 7)
#define MT_RXWI_RATE_SGI BIT(9)
#define MT_RXWI_RATE_STBC BIT(10)
#define MT_RXWI_RATE_LDPC_EXSYM BIT(11)
#define MT_RXWI_RATE_PHY GENMASK(15, 13)

#define MT_RATE_INDEX_VHT_IDX GENMASK(3, 0)
#define MT_RATE_INDEX_VHT_NSS GENMASK(5, 4)

#define MT_TX_PWR_ADJ GENMASK(3, 0)

#define MT_TXWI_FLAGS_FRAG BIT(0)
#define MT_TXWI_FLAGS_MMPS BIT(1)
#define MT_TXWI_FLAGS_CFACK BIT(2)
#define MT_TXWI_FLAGS_TS BIT(3)
#define MT_TXWI_FLAGS_AMPDU BIT(4)
#define MT_TXWI_FLAGS_MPDU_DENSITY GENMASK(7, 5)
#define MT_TXWI_FLAGS_TXOP GENMASK(9, 8)
#define MT_TXWI_FLAGS_NDPS BIT(10)
#define MT_TXWI_FLAGS_RTSBWSIG BIT(11)
#define MT_TXWI_FLAGS_NDP_BW GENMASK(13, 12)
#define MT_TXWI_FLAGS_SOUND BIT(14)
#define MT_TXWI_FLAGS_TX_RATE_LUT BIT(15)

#define MT_TXWI_ACK_CTL_REQ BIT(0)
#define MT_TXWI_ACK_CTL_NSEQ BIT(1)
#define MT_TXWI_ACK_CTL_BA_WINDOW GENMASK(7, 2)

#define MT_EE_ANTENNA_DUAL BIT(15)

#define MT_EE_NIC_CONF_0_RX_PATH GENMASK(3, 0)
#define MT_EE_NIC_CONF_0_TX_PATH GENMASK(7, 4)
#define MT_EE_NIC_CONF_0_PA_TYPE GENMASK(9, 8)
#define MT_EE_NIC_CONF_0_PA_INT_2G BIT(8)
#define MT_EE_NIC_CONF_0_PA_INT_5G BIT(9)
#define MT_EE_NIC_CONF_0_PA_IO_CURRENT BIT(10)
#define MT_EE_NIC_CONF_0_BOARD_TYPE GENMASK(13, 12)

#define MT_EE_NIC_CONF_1_HW_RF_CTRL BIT(0)
#define MT_EE_NIC_CONF_1_TEMP_TX_ALC BIT(1)
#define MT_EE_NIC_CONF_1_LNA_EXT_2G BIT(2)
#define MT_EE_NIC_CONF_1_LNA_EXT_5G BIT(3)
#define MT_EE_NIC_CONF_1_TX_ALC_EN BIT(13)

#define MT_EE_NIC_CONF_2_ANT_OPT BIT(3)
#define MT_EE_NIC_CONF_2_ANT_DIV BIT(4)
#define MT_EE_NIC_CONF_2_XTAL_OPTION GENMASK(10, 9)

#define MT_VEND_TYPE_CFG BIT(30)

#define MT_CMD_HDR_LEN 4

enum mt76_vendor_req {
	MT_VEND_DEV_MODE = 0x01,
	MT_VEND_WRITE = 0x02,
	MT_VEND_POWER_ON = 0x04,
	MT_VEND_MULTI_WRITE = 0x06,
	MT_VEND_MULTI_READ = 0x07,
	MT_VEND_READ_EEPROM = 0x09,
	MT_VEND_WRITE_FCE = 0x42,
	MT_VEND_WRITE_CFG = 0x46,
	MT_VEND_READ_CFG = 0x47,
	MT_VEND_READ_EXT = 0x63,
	MT_VEND_WRITE_EXT = 0x66,
	MT_VEND_FEATURE_SET = 0x91,
};

enum mt76_dma_msg_port {
	MT_WLAN_PORT,
	MT_CPU_RX_PORT,
	MT_CPU_TX_PORT,
	MT_HOST_PORT,
	MT_VIRTUAL_CPU_RX_PORT,
	MT_VIRTUAL_CPU_TX_PORT,
	MT_DISCARD,
};

enum mt76_mcu_cmd {
	MT_CMD_FUN_SET_OP = 1,
	MT_CMD_LOAD_CR = 2,
	MT_CMD_INIT_GAIN_OP = 3,
	MT_CMD_DYNC_VGA_OP = 6,
	MT_CMD_TDLS_CH_SW = 7,
	MT_CMD_BURST_WRITE = 8,
	MT_CMD_READ_MODIFY_WRITE = 9,
	MT_CMD_RANDOM_READ = 10,
	MT_CMD_BURST_READ = 11,
	MT_CMD_RANDOM_WRITE = 12,
	MT_CMD_LED_MODE_OP = 16,
	MT_CMD_POWER_SAVING_OP = 20,
	MT_CMD_WOW_CONFIG = 21,
	MT_CMD_WOW_QUERY = 22,
	MT_CMD_WOW_FEATURE = 24,
	MT_CMD_CARRIER_DETECT_OP = 28,
	MT_CMD_RADOR_DETECT_OP = 29,
	MT_CMD_SWITCH_CHANNEL_OP = 30,
	MT_CMD_CALIBRATION_OP = 31,
	MT_CMD_BEACON_OP = 32,
	MT_CMD_ANTENNA_OP = 33,
};

enum mt76_mcu_function {
	MT_Q_SELECT = 1,
	MT_BW_SETTING = 2,
	MT_USB2_SW_DISCONNECT = 2,
	MT_USB3_SW_DISCONNECT = 3,
	MT_LOG_FW_DEBUG_MSG = 4,
	MT_GET_FW_VERSION = 5,
};

enum mt76_mcu_cr_mode {
	MT_RF_CR,
	MT_BBP_CR,
	MT_RF_BBP_CR,
	MT_HL_TEMP_CR_UPDATE,
};

enum mt76_mcu_power_mode {
	MT_RADIO_OFF = 0x30,
	MT_RADIO_ON = 0x31,
	MT_RADIO_OFF_AUTO_WAKEUP = 0x32,
	MT_RADIO_OFF_ADVANCE = 0x33,
	MT_RADIO_ON_ADVANCE = 0x34,
};

enum mt76_mcu_calibration {
	MT_MCU_CAL_R = 1,
	MT_MCU_CAL_TEMP_SENSOR,
	MT_MCU_CAL_RXDCOC,
	MT_MCU_CAL_RC,
	MT_MCU_CAL_SX_LOGEN,
	MT_MCU_CAL_LC,
	MT_MCU_CAL_TX_LOFT,
	MT_MCU_CAL_TXIQ,
	MT_MCU_CAL_TSSI,
	MT_MCU_CAL_TSSI_COMP,
	MT_MCU_CAL_DPD,
	MT_MCU_CAL_RXIQC_FI,
	MT_MCU_CAL_RXIQC_FD,
	MT_MCU_CAL_PWRON,
	MT_MCU_CAL_TX_SHAPING,
};

enum mt76_eeprom_mode {
	MT_EE_READ,
	MT_EE_PHYSICAL_READ,
};

enum mt76_eeprom_field {
	MT_EE_CHIP_ID = 0x0000,
	MT_EE_VERSION = 0x0002,
	MT_EE_MAC_ADDR = 0x0004,
	MT_EE_PCI_ID = 0x000a,
	MT_EE_ANTENNA = 0x0022,
	MT_EE_CFG1_INIT = 0x0024,
	MT_EE_NIC_CONF_0 = 0x0034,
	MT_EE_NIC_CONF_1 = 0x0036,
	MT_EE_COUNTRY_REGION_5GHZ = 0x0038,
	MT_EE_COUNTRY_REGION_2GHZ = 0x0039,
	MT_EE_FREQ_OFFSET = 0x003a,
	MT_EE_NIC_CONF_2 = 0x0042,

	MT_EE_XTAL_TRIM_1 = 0x003a,
	MT_EE_XTAL_TRIM_2 = 0x009e,

	MT_EE_LNA_GAIN = 0x0044,
	MT_EE_RSSI_OFFSET_2G_0 = 0x0046,
	MT_EE_RSSI_OFFSET_2G_1 = 0x0048,
	MT_EE_LNA_GAIN_5GHZ_1 = 0x0049,
	MT_EE_RSSI_OFFSET_5G_0 = 0x004a,
	MT_EE_RSSI_OFFSET_5G_1 = 0x004c,
	MT_EE_LNA_GAIN_5GHZ_2 = 0x004d,

	MT_EE_TX_POWER_DELTA_BW40 = 0x0050,
	MT_EE_TX_POWER_DELTA_BW80 = 0x0052,

	MT_EE_TX_POWER_EXT_PA_5G = 0x0054,

	MT_EE_TX_POWER_0_START_2G = 0x0056,
	MT_EE_TX_POWER_1_START_2G = 0x005c,

#define MT_TX_POWER_GROUP_SIZE_5G 5
#define MT_TX_POWER_GROUPS_5G 6
	MT_EE_TX_POWER_0_START_5G = 0x0062,
	MT_EE_TSSI_SLOPE_2G = 0x006e,

	MT_EE_TX_POWER_0_GRP3_TX_POWER_DELTA = 0x0074,
	MT_EE_TX_POWER_0_GRP4_TSSI_SLOPE = 0x0076,

	MT_EE_TX_POWER_1_START_5G = 0x0080,

	MT_EE_TX_POWER_CCK = 0x00a0,
	MT_EE_TX_POWER_OFDM_2G_6M = 0x00a2,
	MT_EE_TX_POWER_OFDM_2G_24M = 0x00a4,
	MT_EE_TX_POWER_OFDM_5G_6M = 0x00b2,
	MT_EE_TX_POWER_OFDM_5G_24M = 0x00b4,
	MT_EE_TX_POWER_HT_MCS0 = 0x00a6,
	MT_EE_TX_POWER_HT_MCS4 = 0x00a8,
	MT_EE_TX_POWER_HT_MCS8 = 0x00aa,
	MT_EE_TX_POWER_HT_MCS12 = 0x00ac,
	MT_EE_TX_POWER_VHT_MCS0 = 0x00ba,
	MT_EE_TX_POWER_VHT_MCS4 = 0x00bc,
	MT_EE_TX_POWER_VHT_MCS8 = 0x00be,

	MT_EE_2G_TARGET_POWER = 0x00d0,
	MT_EE_TEMP_OFFSET = 0x00d1,
	MT_EE_5G_TARGET_POWER = 0x00d2,
	MT_EE_TSSI_BOUND1 = 0x00d4,
	MT_EE_TSSI_BOUND2 = 0x00d6,
	MT_EE_TSSI_BOUND3 = 0x00d8,
	MT_EE_TSSI_BOUND4 = 0x00da,
	MT_EE_FREQ_OFFSET_COMPENSATION = 0x00db,
	MT_EE_TSSI_BOUND5 = 0x00dc,
	MT_EE_TX_POWER_BYRATE_BASE = 0x00de,

	MT_EE_TSSI_SLOPE_5G = 0x00f0,
	MT_EE_RF_TEMP_COMP_SLOPE_5G = 0x00f2,
	MT_EE_RF_TEMP_COMP_SLOPE_2G = 0x00f4,

	MT_EE_RF_2G_TSSI_OFF_TXPOWER = 0x00f6,
	MT_EE_RF_2G_RX_HIGH_GAIN = 0x00f8,
	MT_EE_RF_5G_GRP0_1_RX_HIGH_GAIN = 0x00fa,
	MT_EE_RF_5G_GRP2_3_RX_HIGH_GAIN = 0x00fc,
	MT_EE_RF_5G_GRP4_5_RX_HIGH_GAIN = 0x00fe,

	MT_EE_BT_RCAL_RESULT = 0x0138,
	MT_EE_BT_VCDL_CALIBRATION = 0x013c,
	MT_EE_BT_PMUCFG = 0x013e,

	MT_EE_USAGE_MAP_START = 0x01e0,
	MT_EE_USAGE_MAP_END = 0x01fc,
};

enum mt76_phy_type {
	MT_PHY_TYPE_CCK,
	MT_PHY_TYPE_OFDM,
	MT_PHY_TYPE_HT,
	MT_PHY_TYPE_HT_GF,
	MT_PHY_TYPE_VHT,
	MT_PHY_TYPE_HE_SU = 8,
	MT_PHY_TYPE_HE_EXT_SU,
	MT_PHY_TYPE_HE_TB,
	MT_PHY_TYPE_HE_MU,
};

enum mt76_phy_bandwidth {
	MT_PHY_BW_20,
	MT_PHY_BW_40,
	MT_PHY_BW_80,
};

enum mt76_cal_channel_group {
	MT_CH_5G_JAPAN,
	MT_CH_5G_UNII_1,
	MT_CH_5G_UNII_2,
	MT_CH_5G_UNII_2E_1,
	MT_CH_5G_UNII_2E_2,
	MT_CH_5G_UNII_3,
};

enum mt76_qsel {
	MT_QSEL_MGMT,
	MT_QSEL_HCCA,
	MT_QSEL_EDCA,
	MT_QSEL_EDCA_2,
};

enum mt76_cipher_type {
	MT_CIPHER_NONE,
	MT_CIPHER_WEP40,
	MT_CIPHER_WEP104,
	MT_CIPHER_TKIP,
	MT_CIPHER_AES_CCMP,
	MT_CIPHER_CKIP40,
	MT_CIPHER_CKIP104,
	MT_CIPHER_CKIP128,
	MT_CIPHER_WAPI,
};

struct mt76_fw_header {
	__le32 ilm_len;
	__le32 dlm_len;
	__le16 build_ver;
	__le16 fw_ver;
	u8 pad[4];
	char build_time[16];
} __packed;

struct mt76_rxwi {
	__le32 rxinfo;
	__le32 ctl;
	__le16 tid_sn;
	__le16 rate;
	u8 rssi[4];
	__le32 bbp_rxinfo[4];
} __packed;

struct mt76_txwi {
	__le16 flags;
	__le16 rate;
	u8 ack_ctl;
	u8 wcid;
	__le16 len_ctl;
	__le32 iv;
	__le32 eiv;
	u8 aid;
	u8 txstream;
	u8 ctl2;
	u8 pktid;
} __packed;
