rte_pmd_cnxk.h

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/* SPDX-License-Identifier: BSD-3-Clause
 * Copyright(C) 2022 Marvell.
 */

#ifndef _PMD_CNXK_H_
#define _PMD_CNXK_H_

#include <rte_compat.h>
#include <rte_ethdev.h>
#include <rte_ether.h>
#include <rte_security.h>

enum rte_pmd_cnxk_sec_action_alg {
    RTE_PMD_CNXK_SEC_ACTION_ALG0,
    RTE_PMD_CNXK_SEC_ACTION_ALG1,
    RTE_PMD_CNXK_SEC_ACTION_ALG2,
    RTE_PMD_CNXK_SEC_ACTION_ALG3,
    RTE_PMD_CNXK_SEC_ACTION_ALG4,
};

enum rte_pmd_cnxk_cpt_q_stats_type {
    RTE_PMD_CNXK_CPT_Q_STATS_INL_DEV,
    RTE_PMD_CNXK_CPT_Q_STATS_KERNEL,
    RTE_PMD_CNXK_CPT_Q_STATS_ETHDEV,
};

struct rte_pmd_cnxk_cpt_q_stats {
    uint64_t enc_pkts;
    uint64_t enc_bytes;
    uint64_t dec_pkts;
    uint64_t dec_bytes;
};

struct rte_pmd_cnxk_sec_action {
    uint32_t sa_index;
    bool sa_xor;
    uint16_t sa_hi, sa_lo;
    enum rte_pmd_cnxk_sec_action_alg alg;
    bool is_non_inp;
    uint16_t profile_id;
    bool use_custom_profile;
};

#define RTE_PMD_CNXK_CTX_MAX_CKEY_LEN      32
#define RTE_PMD_CNXK_CTX_MAX_OPAD_IPAD_LEN 128

#define RTE_PMD_CNXK_AR_WIN_SIZE_MIN        64
#define RTE_PMD_CNXK_AR_WIN_SIZE_MAX        4096
#define RTE_PMD_CNXK_LOG_MIN_AR_WIN_SIZE_M1 5

#define RTE_PMD_CNXK_AR_WINBITS_SZ (RTE_ALIGN_CEIL(RTE_PMD_CNXK_AR_WIN_SIZE_MAX, 64) / 64)

union rte_pmd_cnxk_ipsec_outer_ip_hdr {
    struct {
        uint32_t dst_addr;
        uint32_t src_addr;
    } ipv4;
    struct {
        uint8_t src_addr[16];
        uint8_t dst_addr[16];
    } ipv6;
};

struct rte_pmd_cnxk_ipsec_inb_ctx_update_reg {
    uint64_t ar_base;
    uint64_t ar_valid_mask;
    uint64_t hard_life;
    uint64_t soft_life;
    uint64_t mib_octs;
    uint64_t mib_pkts;
    uint64_t ar_winbits[RTE_PMD_CNXK_AR_WINBITS_SZ];
};

union rte_pmd_cnxk_ipsec_outb_iv {
    uint64_t u64[2];
    uint8_t iv_dbg[16];
    struct {
        uint8_t iv_dbg1[4];
        uint8_t salt[4];

        uint32_t rsvd;
        uint8_t iv_dbg2[4];
    } s;
};

struct rte_pmd_cnxk_ipsec_outb_ctx_update_reg {
    union {
        struct {
            uint64_t reserved_0_2 : 3;
            uint64_t address : 57;
            uint64_t mode : 4;
        } s;
        uint64_t u64;
    } err_ctl;

    uint64_t esn_val;
    uint64_t hard_life;
    uint64_t soft_life;
    uint64_t mib_octs;
    uint64_t mib_pkts;
};

struct rte_pmd_cnxk_ipsec_inb_sa {
    union {
        struct {
            uint64_t ar_win : 3;
            uint64_t hard_life_dec : 1;
            uint64_t soft_life_dec : 1;

            uint64_t count_glb_octets : 1;
            uint64_t count_glb_pkts : 1;
            uint64_t count_mib_bytes : 1;

            uint64_t count_mib_pkts : 1;
            uint64_t hw_ctx_off : 7;

            uint64_t ctx_id : 16;

            uint64_t orig_pkt_fabs : 1;
            uint64_t orig_pkt_free : 1;
            uint64_t pkind : 6;

            uint64_t rsvd0 : 1;
            uint64_t et_ovrwr : 1;
            uint64_t pkt_output : 2;
            uint64_t pkt_format : 1;
            uint64_t defrag_opt : 2;
            uint64_t x2p_dst : 1;

            uint64_t ctx_push_size : 7;
            uint64_t rsvd1 : 1;

            uint64_t ctx_hdr_size : 2;
            uint64_t aop_valid : 1;
            uint64_t rsvd2 : 1;
            uint64_t ctx_size : 4;
        } s;
        uint64_t u64;
    } w0;

    union {
        struct {
            uint64_t orig_pkt_aura : 20;
            uint64_t rsvd3 : 4;
            uint64_t orig_pkt_foff : 8;
            uint64_t cookie : 32;
        } s;
        uint64_t u64;
    } w1;

    union {
        struct {
            uint64_t valid : 1;
            uint64_t dir : 1;
            uint64_t rsvd11 : 1;
            uint64_t rsvd4 : 1;
            uint64_t ipsec_mode : 1;
            uint64_t ipsec_protocol : 1;
            uint64_t aes_key_len : 2;

            uint64_t enc_type : 3;
            uint64_t life_unit : 1;
            uint64_t auth_type : 4;

            uint64_t encap_type : 2;
            uint64_t et_ovrwr_ddr_en : 1;
            uint64_t esn_en : 1;
            uint64_t tport_l4_incr_csum : 1;
            uint64_t ip_hdr_verify : 2;
            uint64_t udp_ports_verify : 1;

            uint64_t l3hdr_on_err : 1;
            uint64_t rsvd6 : 6;
            uint64_t rsvd12 : 1;

            uint64_t spi : 32;
        } s;
        uint64_t u64;
    } w2;

    uint64_t rsvd7;

    uint8_t cipher_key[RTE_PMD_CNXK_CTX_MAX_CKEY_LEN];

    union {
        struct {
            uint32_t rsvd8;
            uint8_t salt[4];
        } s;
        uint64_t u64;
    } w8;
    uint64_t rsvd9;

    union {
        struct {
            uint64_t rsvd10 : 32;
            uint64_t udp_src_port : 16;
            uint64_t udp_dst_port : 16;
        } s;
        uint64_t u64;
    } w10;

    union rte_pmd_cnxk_ipsec_outer_ip_hdr outer_hdr;

    uint8_t hmac_opad_ipad[RTE_PMD_CNXK_CTX_MAX_OPAD_IPAD_LEN];

    struct rte_pmd_cnxk_ipsec_inb_ctx_update_reg ctx;
};

struct rte_pmd_cnxk_ipsec_outb_sa {
    union {
        struct {
            uint64_t esn_en : 1;
            uint64_t ip_id : 1;
            uint64_t rsvd0 : 1;
            uint64_t hard_life_dec : 1;
            uint64_t soft_life_dec : 1;

            uint64_t count_glb_octets : 1;
            uint64_t count_glb_pkts : 1;
            uint64_t count_mib_bytes : 1;

            uint64_t count_mib_pkts : 1;
            uint64_t hw_ctx_off : 7;

            uint64_t ctx_id : 16;
            uint64_t rsvd1 : 16;

            uint64_t ctx_push_size : 7;
            uint64_t rsvd2 : 1;

            uint64_t ctx_hdr_size : 2;
            uint64_t aop_valid : 1;
            uint64_t rsvd3 : 1;
            uint64_t ctx_size : 4;
        } s;
        uint64_t u64;
    } w0;

    union {
        struct {
            uint64_t rsvd4 : 32;
            uint64_t cookie : 32;
        } s;
        uint64_t u64;
    } w1;

    union {
        struct {
            uint64_t valid : 1;
            uint64_t dir : 1;
            uint64_t rsvd11 : 1;
            uint64_t rsvd5 : 1;
            uint64_t ipsec_mode : 1;
            uint64_t ipsec_protocol : 1;

            uint64_t aes_key_len : 2;

            uint64_t enc_type : 3;
            uint64_t life_unit : 1;
            uint64_t auth_type : 4;

            uint64_t encap_type : 2;
            uint64_t ipv4_df_src_or_ipv6_flw_lbl_src : 1;
            uint64_t dscp_src : 1;
            uint64_t iv_src : 2;
            uint64_t ipid_gen : 1;
            uint64_t rsvd6 : 1;

            uint64_t rsvd7 : 7;
            uint64_t rsvd12 : 1;

            uint64_t spi : 32;
        } s;
        uint64_t u64;
    } w2;

    uint64_t rsvd8;

    uint8_t cipher_key[RTE_PMD_CNXK_CTX_MAX_CKEY_LEN];

    union rte_pmd_cnxk_ipsec_outb_iv iv;

    union {
        struct {
            uint64_t rsvd9 : 4;
            uint64_t ipv4_df_or_ipv6_flw_lbl : 20;

            uint64_t dscp : 6;
            uint64_t rsvd10 : 2;

            uint64_t udp_dst_port : 16;

            uint64_t udp_src_port : 16;
        } s;
        uint64_t u64;
    } w10;

    union rte_pmd_cnxk_ipsec_outer_ip_hdr outer_hdr;

    uint8_t hmac_opad_ipad[RTE_PMD_CNXK_CTX_MAX_OPAD_IPAD_LEN];

    struct rte_pmd_cnxk_ipsec_outb_ctx_update_reg ctx;
};

union rte_pmd_cnxk_ipsec_hw_sa {
    struct rte_pmd_cnxk_ipsec_inb_sa inb;
    struct rte_pmd_cnxk_ipsec_outb_sa outb;
};

union rte_pmd_cnxk_cpt_res_s {
    struct rte_pmd_cpt_cn10k_res_s {
        uint64_t compcode : 7;
        uint64_t doneint : 1;
        uint64_t uc_compcode : 8;
        uint64_t rlen : 16;
        uint64_t spi : 32;

        uint64_t esn;
    } cn10k;

    struct rte_pmd_cpt_cn9k_res_s {
        uint64_t compcode : 8;
        uint64_t uc_compcode : 8;
        uint64_t doneint : 1;
        uint64_t reserved_17_63 : 47;

        uint64_t reserved_64_127;
    } cn9k;

    uint64_t u64[2];
};

struct rte_pmd_cnxk_ipsec_inb_cfg {
    uint16_t param1;
    uint16_t param2;
};

struct rte_pmd_cnxk_inl_dev_q;

__rte_experimental
int rte_pmd_cnxk_hw_sa_read(uint16_t portid, void *sess, union rte_pmd_cnxk_ipsec_hw_sa *data,
                uint32_t len, bool inb);
__rte_experimental
int rte_pmd_cnxk_hw_sa_write(uint16_t portid, void *sess, union rte_pmd_cnxk_ipsec_hw_sa *data,
                 uint32_t len, bool inb);

__rte_experimental
union rte_pmd_cnxk_cpt_res_s *rte_pmd_cnxk_inl_ipsec_res(struct rte_mbuf *mbuf);

__rte_experimental
union rte_pmd_cnxk_ipsec_hw_sa *rte_pmd_cnxk_hw_session_base_get(uint16_t portid, bool inb);

__rte_experimental
union rte_pmd_cnxk_ipsec_hw_sa *rte_pmd_cnxk_inl_inb_prof_sa_base_get(uint16_t portid,
                                       uint16_t profile_id);

__rte_experimental
int rte_pmd_cnxk_sa_flush(uint16_t portid, union rte_pmd_cnxk_ipsec_hw_sa *sess, bool inb);

__rte_experimental
struct rte_pmd_cnxk_inl_dev_q *rte_pmd_cnxk_inl_dev_qptr_get(void);

__rte_experimental
uint16_t rte_pmd_cnxk_inl_dev_submit(struct rte_pmd_cnxk_inl_dev_q *qptr, void *inst,
                     uint16_t nb_inst);

__rte_experimental
int rte_pmd_cnxk_cpt_q_stats_get(uint16_t portid, enum rte_pmd_cnxk_cpt_q_stats_type type,
                 struct rte_pmd_cnxk_cpt_q_stats *stats, uint16_t idx);

__rte_experimental
void rte_pmd_cnxk_hw_inline_inb_cfg_set(uint16_t portid, struct rte_pmd_cnxk_ipsec_inb_cfg *cfg);

struct rte_pmd_cnxk_rx_def_inl_cfg {
    uint64_t ltype_mask;
    uint64_t ltype_match;
    uint64_t lid;
    uint64_t gen_offset_ng;
    uint64_t gen_offset;
    uint64_t gen_nz;
    uint64_t cpt_l3_lid;
    uint64_t flags_mask;
    uint64_t flags_match;
    uint64_t match_oipv4;
    uint64_t match_oipv6;
    uint64_t oiplen_ena;
    uint64_t inline_shift;
};

struct rte_pmd_cnxk_rx_gen_inl_cfg {
    uint64_t ltype_mask;
    uint64_t ltype_match;
    uint64_t lid;
    uint64_t noffset;
    uint64_t offset;
    uint64_t param2;
    uint64_t param1;
    uint64_t opcode;
    uint64_t egrp;
    uint64_t ctx_val;
};

struct rte_pmd_cnxk_rx_extract_inl_cfg {
    uint64_t len_l;
    uint64_t bitpos_l;
    uint64_t len_m;
    uint64_t bitpos_m;
    uint64_t len_h;
    uint64_t bitpos_h;
};

enum rte_pmd_cnxk_nix_rx_prot_e {
    RTE_PMD_CNXK_RX_PROT_OPCODE = 0,     
    RTE_PMD_CNXK_RX_PROT_PARAM1 = 1,     
    RTE_PMD_CNXK_RX_PROT_PARAM2 = 2,     
    RTE_PMD_CNXK_RX_PROT_SA_INDEX = 3,   
    RTE_PMD_CNXK_RX_PROT_RPTR_H = 4,     
    RTE_PMD_CNXK_RX_PROT_IP_OFFSET = 5,  
    RTE_PMD_CNXK_RX_PROT_INL_OFFSET = 6, 
    RTE_PMD_CNXK_RX_PROT_ALG = 7,        
    RTE_PMD_CNXK_RX_PROT_SUB_INDEX = 8,  
};

#define RTE_PMD_CNXK_MAX_PROT_FIELDS 9

struct rte_pmd_cnxk_rx_prot_field_inl_cfg {
    uint64_t logmult;
    uint64_t sizem1;
    uint64_t offset;
    uint64_t valid;
};

struct rte_pmd_cnxk_profile_cfg_params {
    struct rte_pmd_cnxk_rx_def_inl_cfg def_cfg;

    struct rte_pmd_cnxk_rx_gen_inl_cfg gen_cfg;

    struct rte_pmd_cnxk_rx_extract_inl_cfg extract_cfg;

    struct rte_pmd_cnxk_rx_prot_field_inl_cfg prot_field_cfg[RTE_PMD_CNXK_MAX_PROT_FIELDS];

    uint32_t sa_size;

    uint32_t max_sa;
};

__rte_experimental
int rte_pmd_cnxk_nix_inl_custom_profile_setup(uint16_t portid,
        const struct rte_pmd_cnxk_profile_cfg_params *cfg, uint16_t *profile_id);

__rte_experimental
int rte_pmd_cnxk_nix_inl_custom_profile_release(uint16_t portid,
                        uint16_t profile_id);

__rte_experimental
const char *rte_pmd_cnxk_model_str_get(void);
#endif /* _PMD_CNXK_H_ */