Mock Version: 4.1
ENTER ['do_with_status'](['bash', '--login', '-c', '/usr/bin/rpmbuild -bs  --target aarch64 --nodeps /builddir/build/SPECS/litex-pythondata-cpu-cva5.spec'], chrootPath='/var/lib/mock/rhel+epel-9-aarch64-1688731624.732795/root'env={'TERM': 'vt100', 'SHELL': '/bin/bash', 'HOME': '/builddir', 'HOSTNAME': 'mock', 'PATH': '/usr/bin:/bin:/usr/sbin:/sbin', 'PROMPT_COMMAND': 'printf "\\033]0;<mock-chroot>\\007"', 'PS1': '<mock-chroot> \\s-\\v\\$ ', 'LANG': 'C.UTF-8'}shell=Falselogger=<mockbuild.trace_decorator.getLog object at 0xffff9427ed50>timeout=0uid=1001gid=135user='mockbuild'nspawn_args=['--capability=cap_ipc_lock', '--rlimit=RLIMIT_NOFILE=10240', '--capability=cap_ipc_lock', '--bind=/tmp/mock-resolv.95k5sx3r:/etc/resolv.conf', '--bind=/dev/btrfs-control', '--bind=/dev/mapper/control', '--bind=/dev/loop-control', '--bind=/dev/loop0', '--bind=/dev/loop1', '--bind=/dev/loop2', '--bind=/dev/loop3', '--bind=/dev/loop4', '--bind=/dev/loop5', '--bind=/dev/loop6', '--bind=/dev/loop7', '--bind=/dev/loop8', '--bind=/dev/loop9', '--bind=/dev/loop10', '--bind=/dev/loop11']unshare_net=FalseprintOutput=True)
Using nspawn with args ['--capability=cap_ipc_lock', '--rlimit=RLIMIT_NOFILE=10240', '--capability=cap_ipc_lock', '--bind=/tmp/mock-resolv.95k5sx3r:/etc/resolv.conf', '--bind=/dev/btrfs-control', '--bind=/dev/mapper/control', '--bind=/dev/loop-control', '--bind=/dev/loop0', '--bind=/dev/loop1', '--bind=/dev/loop2', '--bind=/dev/loop3', '--bind=/dev/loop4', '--bind=/dev/loop5', '--bind=/dev/loop6', '--bind=/dev/loop7', '--bind=/dev/loop8', '--bind=/dev/loop9', '--bind=/dev/loop10', '--bind=/dev/loop11']
Executing command: ['/usr/bin/systemd-nspawn', '-q', '-M', '05d5eb51cf6c4bbd86e232847622fddc', '-D', '/var/lib/mock/rhel+epel-9-aarch64-1688731624.732795/root', '-a', '-u', 'mockbuild', '--capability=cap_ipc_lock', '--rlimit=RLIMIT_NOFILE=10240', '--capability=cap_ipc_lock', '--bind=/tmp/mock-resolv.95k5sx3r:/etc/resolv.conf', '--bind=/dev/btrfs-control', '--bind=/dev/mapper/control', '--bind=/dev/loop-control', '--bind=/dev/loop0', '--bind=/dev/loop1', '--bind=/dev/loop2', '--bind=/dev/loop3', '--bind=/dev/loop4', '--bind=/dev/loop5', '--bind=/dev/loop6', '--bind=/dev/loop7', '--bind=/dev/loop8', '--bind=/dev/loop9', '--bind=/dev/loop10', '--bind=/dev/loop11', '--console=pipe', '--setenv=TERM=vt100', '--setenv=SHELL=/bin/bash', '--setenv=HOME=/builddir', '--setenv=HOSTNAME=mock', '--setenv=PATH=/usr/bin:/bin:/usr/sbin:/sbin', '--setenv=PROMPT_COMMAND=printf "\\033]0;<mock-chroot>\\007"', '--setenv=PS1=<mock-chroot> \\s-\\v\\$ ', '--setenv=LANG=C.UTF-8', '--resolv-conf=off', 'bash', '--login', '-c', '/usr/bin/rpmbuild -bs  --target aarch64 --nodeps /builddir/build/SPECS/litex-pythondata-cpu-cva5.spec'] with env {'TERM': 'vt100', 'SHELL': '/bin/bash', 'HOME': '/builddir', 'HOSTNAME': 'mock', 'PATH': '/usr/bin:/bin:/usr/sbin:/sbin', 'PROMPT_COMMAND': 'printf "\\033]0;<mock-chroot>\\007"', 'PS1': '<mock-chroot> \\s-\\v\\$ ', 'LANG': 'C.UTF-8', 'SYSTEMD_NSPAWN_TMPFS_TMP': '0', 'SYSTEMD_SECCOMP': '0'} and shell False
Building target platforms: aarch64
Building for target aarch64
setting SOURCE_DATE_EPOCH=1654300800
Wrote: /builddir/build/SRPMS/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.src.rpm
Child return code was: 0
ENTER ['do_with_status'](['bash', '--login', '-c', '/usr/bin/rpmbuild -bb  --target aarch64 --nodeps /builddir/build/SPECS/litex-pythondata-cpu-cva5.spec'], chrootPath='/var/lib/mock/rhel+epel-9-aarch64-1688731624.732795/root'env={'TERM': 'vt100', 'SHELL': '/bin/bash', 'HOME': '/builddir', 'HOSTNAME': 'mock', 'PATH': '/usr/bin:/bin:/usr/sbin:/sbin', 'PROMPT_COMMAND': 'printf "\\033]0;<mock-chroot>\\007"', 'PS1': '<mock-chroot> \\s-\\v\\$ ', 'LANG': 'C.UTF-8'}shell=Falselogger=<mockbuild.trace_decorator.getLog object at 0xffff9427ed50>timeout=0uid=1001gid=135user='mockbuild'nspawn_args=['--capability=cap_ipc_lock', '--rlimit=RLIMIT_NOFILE=10240', '--capability=cap_ipc_lock', '--bind=/tmp/mock-resolv.95k5sx3r:/etc/resolv.conf', '--bind=/dev/btrfs-control', '--bind=/dev/mapper/control', '--bind=/dev/loop-control', '--bind=/dev/loop0', '--bind=/dev/loop1', '--bind=/dev/loop2', '--bind=/dev/loop3', '--bind=/dev/loop4', '--bind=/dev/loop5', '--bind=/dev/loop6', '--bind=/dev/loop7', '--bind=/dev/loop8', '--bind=/dev/loop9', '--bind=/dev/loop10', '--bind=/dev/loop11']unshare_net=FalseprintOutput=True)
Using nspawn with args ['--capability=cap_ipc_lock', '--rlimit=RLIMIT_NOFILE=10240', '--capability=cap_ipc_lock', '--bind=/tmp/mock-resolv.95k5sx3r:/etc/resolv.conf', '--bind=/dev/btrfs-control', '--bind=/dev/mapper/control', '--bind=/dev/loop-control', '--bind=/dev/loop0', '--bind=/dev/loop1', '--bind=/dev/loop2', '--bind=/dev/loop3', '--bind=/dev/loop4', '--bind=/dev/loop5', '--bind=/dev/loop6', '--bind=/dev/loop7', '--bind=/dev/loop8', '--bind=/dev/loop9', '--bind=/dev/loop10', '--bind=/dev/loop11']
Executing command: ['/usr/bin/systemd-nspawn', '-q', '-M', 'f80a1d1604ce48119f8da748547121b4', '-D', '/var/lib/mock/rhel+epel-9-aarch64-1688731624.732795/root', '-a', '-u', 'mockbuild', '--capability=cap_ipc_lock', '--rlimit=RLIMIT_NOFILE=10240', '--capability=cap_ipc_lock', '--bind=/tmp/mock-resolv.95k5sx3r:/etc/resolv.conf', '--bind=/dev/btrfs-control', '--bind=/dev/mapper/control', '--bind=/dev/loop-control', '--bind=/dev/loop0', '--bind=/dev/loop1', '--bind=/dev/loop2', '--bind=/dev/loop3', '--bind=/dev/loop4', '--bind=/dev/loop5', '--bind=/dev/loop6', '--bind=/dev/loop7', '--bind=/dev/loop8', '--bind=/dev/loop9', '--bind=/dev/loop10', '--bind=/dev/loop11', '--console=pipe', '--setenv=TERM=vt100', '--setenv=SHELL=/bin/bash', '--setenv=HOME=/builddir', '--setenv=HOSTNAME=mock', '--setenv=PATH=/usr/bin:/bin:/usr/sbin:/sbin', '--setenv=PROMPT_COMMAND=printf "\\033]0;<mock-chroot>\\007"', '--setenv=PS1=<mock-chroot> \\s-\\v\\$ ', '--setenv=LANG=C.UTF-8', '--resolv-conf=off', 'bash', '--login', '-c', '/usr/bin/rpmbuild -bb  --target aarch64 --nodeps /builddir/build/SPECS/litex-pythondata-cpu-cva5.spec'] with env {'TERM': 'vt100', 'SHELL': '/bin/bash', 'HOME': '/builddir', 'HOSTNAME': 'mock', 'PATH': '/usr/bin:/bin:/usr/sbin:/sbin', 'PROMPT_COMMAND': 'printf "\\033]0;<mock-chroot>\\007"', 'PS1': '<mock-chroot> \\s-\\v\\$ ', 'LANG': 'C.UTF-8', 'SYSTEMD_NSPAWN_TMPFS_TMP': '0', 'SYSTEMD_SECCOMP': '0'} and shell False
Building target platforms: aarch64
Building for target aarch64
setting SOURCE_DATE_EPOCH=1654300800
Executing(%prep): /bin/sh -e /var/tmp/rpm-tmp.F1XY80
+ umask 022
+ cd /builddir/build/BUILD
+ cd /builddir/build/BUILD
+ rm -rf litex-pythondata-cpu-cva5
+ /usr/bin/mkdir -p litex-pythondata-cpu-cva5
+ cd litex-pythondata-cpu-cva5
+ /usr/bin/chmod -Rf a+rX,u+w,g-w,o-w .
+ find /builddir/build/BUILD -name SPECPARTS -exec rm -rf '{}' +
+ git clone --depth 1 -n -b master https://github.com/litex-hub/pythondata-cpu-cva5.git .
Cloning into '.'...
+ git fetch --depth 1 origin ea1075d60c82191a1391ad00aa55be916bb37ab7
From https://github.com/litex-hub/pythondata-cpu-cva5
 * branch            ea1075d60c82191a1391ad00aa55be916bb37ab7 -> FETCH_HEAD
+ git reset --hard ea1075d60c82191a1391ad00aa55be916bb37ab7
HEAD is now at ea1075d Updating pythondata-cpu-cva5 to 0.0.post649
+ git log --format=fuller
commit ea1075d60c82191a1391ad00aa55be916bb37ab7
Author:     LiteX Robot <robot@timvideos.us>
AuthorDate: Mon May 30 19:56:00 2022 +0000
Commit:     LiteX Robot <robot@timvideos.us>
CommitDate: Mon May 30 19:56:00 2022 +0000
    Updating pythondata-cpu-cva5 to 0.0.post649
    
    Updated data to v0.0-507-g3239e20 based on 3239e20360993151f435fc2f5a567e09b3f185ad from https://github.com/openhwgroup/cva5.
    > commit 3239e20360993151f435fc2f5a567e09b3f185ad
    > Merge: b4d6a9f ce38554
    > Author: Mike Thompson <mike@openhwgroup.org>
    > Date:   Thu May 26 13:17:14 2022 -0400
    >
    >     Merge pull request #5 from e-matthews/minor-fixes
    >
    >     Minor fixes
    >
    
    Updated using 0.0.post142 from https://github.com/litex-hub/litex-data-auto
+ RPM_EC=0
++ jobs -p
+ exit 0
Executing(%build): /bin/sh -e /var/tmp/rpm-tmp.P7PCKx
+ umask 022
+ cd /builddir/build/BUILD
+ cd litex-pythondata-cpu-cva5
+ CFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-D_FORTIFY_SOURCE=2 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fstack-clash-protection'
+ LDFLAGS='-Wl,-z,relro -Wl,--as-needed  -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 '
+ /usr/bin/python3 setup.py build '--executable=/usr/bin/python3 -s'
running build
running build_py
creating build
creating build/lib
creating build/lib/pythondata_cpu_cva5
copying pythondata_cpu_cva5/__init__.py -> build/lib/pythondata_cpu_cva5
running egg_info
creating pythondata_cpu_cva5.egg-info
writing pythondata_cpu_cva5.egg-info/PKG-INFO
writing dependency_links to pythondata_cpu_cva5.egg-info/dependency_links.txt
writing top-level names to pythondata_cpu_cva5.egg-info/top_level.txt
writing manifest file 'pythondata_cpu_cva5.egg-info/SOURCES.txt'
reading manifest file 'pythondata_cpu_cva5.egg-info/SOURCES.txt'
reading manifest template 'MANIFEST.in'
warning: no previously-included files matching '*.py[cod]' found anywhere in distribution
adding license file 'LICENSE'
writing manifest file 'pythondata_cpu_cva5.egg-info/SOURCES.txt'
creating build/lib/pythondata_cpu_cva5/system_verilog
copying pythondata_cpu_cva5/system_verilog/.gitlab-ci.yml -> build/lib/pythondata_cpu_cva5/system_verilog
copying pythondata_cpu_cva5/system_verilog/LICENSE -> build/lib/pythondata_cpu_cva5/system_verilog
copying pythondata_cpu_cva5/system_verilog/README.md -> build/lib/pythondata_cpu_cva5/system_verilog
creating build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/addr_hash.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/alu_unit.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/amo_alu.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/avalon_master.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/axi_master.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/axi_to_arb.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/barrel_shifter.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/binary_occupancy.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/branch_comparator.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/branch_predictor.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/branch_predictor_ram.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/branch_unit.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/byte_en_BRAM.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/clz.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/csr_types.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/csr_unit.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/cva5.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/cva5_config.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/cva5_fifo.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/cva5_types.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/cycler.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/dcache.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/ddata_bank.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/decode_and_issue.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/div_core.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/div_unit.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/dtag_banks.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/external_interfaces.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/fetch.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/gc_unit.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/icache.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/illegal_instruction_checker.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/instruction_metadata_and_id_management.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/interfaces.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/itag_banks.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/l1_arbiter.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/lfsr.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/load_store_queue.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/load_store_unit.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/local_mem_sub_unit.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/mmu.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/mul_unit.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/one_hot_occupancy.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/one_hot_to_integer.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/placer_randomizer.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/priority_encoder.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/ras.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/reg_inuse.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/register_bank.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/register_file.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/register_free_list.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/renamer.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/riscv_types.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/set_clr_reg_with_rst.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/shift_counter.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/store_queue.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/tag_bank.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/tlb_lut_ram.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/toggle_memory.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/toggle_memory_set.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/wishbone_master.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
copying pythondata_cpu_cva5/system_verilog/core/writeback.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core
creating build/lib/pythondata_cpu_cva5/system_verilog/core/intel
copying pythondata_cpu_cva5/system_verilog/core/intel/intel_byte_enable_ram.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core/intel
creating build/lib/pythondata_cpu_cva5/system_verilog/core/lutrams
copying pythondata_cpu_cva5/system_verilog/core/lutrams/lutram_1w_1r.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core/lutrams
copying pythondata_cpu_cva5/system_verilog/core/lutrams/lutram_1w_mr.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core/lutrams
creating build/lib/pythondata_cpu_cva5/system_verilog/core/xilinx
copying pythondata_cpu_cva5/system_verilog/core/xilinx/cva5_wrapper_xilinx.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core/xilinx
copying pythondata_cpu_cva5/system_verilog/core/xilinx/xilinx_byte_enable_ram.sv -> build/lib/pythondata_cpu_cva5/system_verilog/core/xilinx
creating build/lib/pythondata_cpu_cva5/system_verilog/debug_module
copying pythondata_cpu_cva5/system_verilog/debug_module/.gitkeep -> build/lib/pythondata_cpu_cva5/system_verilog/debug_module
copying pythondata_cpu_cva5/system_verilog/debug_module/debug_cfg_types.sv -> build/lib/pythondata_cpu_cva5/system_verilog/debug_module
copying pythondata_cpu_cva5/system_verilog/debug_module/debug_interfaces.sv -> build/lib/pythondata_cpu_cva5/system_verilog/debug_module
copying pythondata_cpu_cva5/system_verilog/debug_module/debug_module.sv -> build/lib/pythondata_cpu_cva5/system_verilog/debug_module
copying pythondata_cpu_cva5/system_verilog/debug_module/jtag_module.sv -> build/lib/pythondata_cpu_cva5/system_verilog/debug_module
copying pythondata_cpu_cva5/system_verilog/debug_module/jtag_register.sv -> build/lib/pythondata_cpu_cva5/system_verilog/debug_module
copying pythondata_cpu_cva5/system_verilog/debug_module/jtag_registers.sv -> build/lib/pythondata_cpu_cva5/system_verilog/debug_module
creating build/lib/pythondata_cpu_cva5/system_verilog/examples
creating build/lib/pythondata_cpu_cva5/system_verilog/examples/litex
copying pythondata_cpu_cva5/system_verilog/examples/litex/l1_to_wishbone.sv -> build/lib/pythondata_cpu_cva5/system_verilog/examples/litex
copying pythondata_cpu_cva5/system_verilog/examples/litex/litex_wrapper.sv -> build/lib/pythondata_cpu_cva5/system_verilog/examples/litex
creating build/lib/pythondata_cpu_cva5/system_verilog/examples/zedboard
copying pythondata_cpu_cva5/system_verilog/examples/zedboard/README.md -> build/lib/pythondata_cpu_cva5/system_verilog/examples/zedboard
copying pythondata_cpu_cva5/system_verilog/examples/zedboard/arm.tcl -> build/lib/pythondata_cpu_cva5/system_verilog/examples/zedboard
copying pythondata_cpu_cva5/system_verilog/examples/zedboard/cva5.png -> build/lib/pythondata_cpu_cva5/system_verilog/examples/zedboard
copying pythondata_cpu_cva5/system_verilog/examples/zedboard/cva5_small.png -> build/lib/pythondata_cpu_cva5/system_verilog/examples/zedboard
copying pythondata_cpu_cva5/system_verilog/examples/zedboard/cva5_wrapper.sv -> build/lib/pythondata_cpu_cva5/system_verilog/examples/zedboard
copying pythondata_cpu_cva5/system_verilog/examples/zedboard/dhrystone.riscv.hw_init -> build/lib/pythondata_cpu_cva5/system_verilog/examples/zedboard
copying pythondata_cpu_cva5/system_verilog/examples/zedboard/dhrystone.riscv.sim_init -> build/lib/pythondata_cpu_cva5/system_verilog/examples/zedboard
copying pythondata_cpu_cva5/system_verilog/examples/zedboard/simulator_output_example.png -> build/lib/pythondata_cpu_cva5/system_verilog/examples/zedboard
copying pythondata_cpu_cva5/system_verilog/examples/zedboard/system.png -> build/lib/pythondata_cpu_cva5/system_verilog/examples/zedboard
copying pythondata_cpu_cva5/system_verilog/examples/zedboard/system_periperhals.tcl -> build/lib/pythondata_cpu_cva5/system_verilog/examples/zedboard
copying pythondata_cpu_cva5/system_verilog/examples/zedboard/xilinx_wiring_sample.png -> build/lib/pythondata_cpu_cva5/system_verilog/examples/zedboard
copying pythondata_cpu_cva5/system_verilog/examples/zedboard/zedboard.xdc -> build/lib/pythondata_cpu_cva5/system_verilog/examples/zedboard
creating build/lib/pythondata_cpu_cva5/system_verilog/examples/zedboard/scripts
copying pythondata_cpu_cva5/system_verilog/examples/zedboard/scripts/cva5-ip-core-base.tcl -> build/lib/pythondata_cpu_cva5/system_verilog/examples/zedboard/scripts
copying pythondata_cpu_cva5/system_verilog/examples/zedboard/scripts/design_1_wrapper.v -> build/lib/pythondata_cpu_cva5/system_verilog/examples/zedboard/scripts
copying pythondata_cpu_cva5/system_verilog/examples/zedboard/scripts/zedboard_master_XDC_RevC_D_v3.xdc -> build/lib/pythondata_cpu_cva5/system_verilog/examples/zedboard/scripts
creating build/lib/pythondata_cpu_cva5/system_verilog/formal
creating build/lib/pythondata_cpu_cva5/system_verilog/formal/interfaces
copying pythondata_cpu_cva5/system_verilog/formal/interfaces/axi4_basic_props.sv -> build/lib/pythondata_cpu_cva5/system_verilog/formal/interfaces
creating build/lib/pythondata_cpu_cva5/system_verilog/formal/models
copying pythondata_cpu_cva5/system_verilog/formal/models/cva5_fbm.sv -> build/lib/pythondata_cpu_cva5/system_verilog/formal/models
copying pythondata_cpu_cva5/system_verilog/formal/models/cva5_formal_wrapper.sv -> build/lib/pythondata_cpu_cva5/system_verilog/formal/models
creating build/lib/pythondata_cpu_cva5/system_verilog/formal/scripts
copying pythondata_cpu_cva5/system_verilog/formal/scripts/cva5_rtl.vfile -> build/lib/pythondata_cpu_cva5/system_verilog/formal/scripts
copying pythondata_cpu_cva5/system_verilog/formal/scripts/setup_cva5_dev.tcl -> build/lib/pythondata_cpu_cva5/system_verilog/formal/scripts
creating build/lib/pythondata_cpu_cva5/system_verilog/l2_arbiter
copying pythondata_cpu_cva5/system_verilog/l2_arbiter/l2_arbiter.sv -> build/lib/pythondata_cpu_cva5/system_verilog/l2_arbiter
copying pythondata_cpu_cva5/system_verilog/l2_arbiter/l2_config_and_types.sv -> build/lib/pythondata_cpu_cva5/system_verilog/l2_arbiter
copying pythondata_cpu_cva5/system_verilog/l2_arbiter/l2_external_interfaces.sv -> build/lib/pythondata_cpu_cva5/system_verilog/l2_arbiter
copying pythondata_cpu_cva5/system_verilog/l2_arbiter/l2_fifo.sv -> build/lib/pythondata_cpu_cva5/system_verilog/l2_arbiter
copying pythondata_cpu_cva5/system_verilog/l2_arbiter/l2_interfaces.sv -> build/lib/pythondata_cpu_cva5/system_verilog/l2_arbiter
copying pythondata_cpu_cva5/system_verilog/l2_arbiter/l2_reservation_logic.sv -> build/lib/pythondata_cpu_cva5/system_verilog/l2_arbiter
copying pythondata_cpu_cva5/system_verilog/l2_arbiter/l2_round_robin.sv -> build/lib/pythondata_cpu_cva5/system_verilog/l2_arbiter
creating build/lib/pythondata_cpu_cva5/system_verilog/local_memory
copying pythondata_cpu_cva5/system_verilog/local_memory/local_mem.sv -> build/lib/pythondata_cpu_cva5/system_verilog/local_memory
copying pythondata_cpu_cva5/system_verilog/local_memory/local_memory_interface.sv -> build/lib/pythondata_cpu_cva5/system_verilog/local_memory
creating build/lib/pythondata_cpu_cva5/system_verilog/scripts
creating build/lib/pythondata_cpu_cva5/system_verilog/scripts/xilinx
copying pythondata_cpu_cva5/system_verilog/scripts/xilinx/cva5_wrapper_IP.tcl -> build/lib/pythondata_cpu_cva5/system_verilog/scripts/xilinx
copying pythondata_cpu_cva5/system_verilog/scripts/xilinx/local_memory_IP.tcl -> build/lib/pythondata_cpu_cva5/system_verilog/scripts/xilinx
creating build/lib/pythondata_cpu_cva5/system_verilog/test_benches
copying pythondata_cpu_cva5/system_verilog/test_benches/axi_mem_sim.sv -> build/lib/pythondata_cpu_cva5/system_verilog/test_benches
copying pythondata_cpu_cva5/system_verilog/test_benches/cva5_tb.sv -> build/lib/pythondata_cpu_cva5/system_verilog/test_benches
copying pythondata_cpu_cva5/system_verilog/test_benches/cva5_tb.wcfg -> build/lib/pythondata_cpu_cva5/system_verilog/test_benches
copying pythondata_cpu_cva5/system_verilog/test_benches/sim_mem.sv -> build/lib/pythondata_cpu_cva5/system_verilog/test_benches
creating build/lib/pythondata_cpu_cva5/system_verilog/test_benches/unit_test_benches
copying pythondata_cpu_cva5/system_verilog/test_benches/unit_test_benches/alu_unit_tb.sv -> build/lib/pythondata_cpu_cva5/system_verilog/test_benches/unit_test_benches
copying pythondata_cpu_cva5/system_verilog/test_benches/unit_test_benches/div_unit_tb.sv -> build/lib/pythondata_cpu_cva5/system_verilog/test_benches/unit_test_benches
copying pythondata_cpu_cva5/system_verilog/test_benches/unit_test_benches/mul_unit_tb.sv -> build/lib/pythondata_cpu_cva5/system_verilog/test_benches/unit_test_benches
creating build/lib/pythondata_cpu_cva5/system_verilog/test_benches/verilator
copying pythondata_cpu_cva5/system_verilog/test_benches/verilator/CVA5Tracer.cc -> build/lib/pythondata_cpu_cva5/system_verilog/test_benches/verilator
copying pythondata_cpu_cva5/system_verilog/test_benches/verilator/CVA5Tracer.h -> build/lib/pythondata_cpu_cva5/system_verilog/test_benches/verilator
copying pythondata_cpu_cva5/system_verilog/test_benches/verilator/SimMem.cc -> build/lib/pythondata_cpu_cva5/system_verilog/test_benches/verilator
copying pythondata_cpu_cva5/system_verilog/test_benches/verilator/SimMem.h -> build/lib/pythondata_cpu_cva5/system_verilog/test_benches/verilator
copying pythondata_cpu_cva5/system_verilog/test_benches/verilator/cva5_sim.cc -> build/lib/pythondata_cpu_cva5/system_verilog/test_benches/verilator
copying pythondata_cpu_cva5/system_verilog/test_benches/verilator/cva5_sim.sv -> build/lib/pythondata_cpu_cva5/system_verilog/test_benches/verilator
creating build/lib/pythondata_cpu_cva5/system_verilog/test_benches/verilator/AXI_DDR_simulation
copying pythondata_cpu_cva5/system_verilog/test_benches/verilator/AXI_DDR_simulation/DDR_init.txt -> build/lib/pythondata_cpu_cva5/system_verilog/test_benches/verilator/AXI_DDR_simulation
copying pythondata_cpu_cva5/system_verilog/test_benches/verilator/AXI_DDR_simulation/axi_ddr_sim.cc -> build/lib/pythondata_cpu_cva5/system_verilog/test_benches/verilator/AXI_DDR_simulation
copying pythondata_cpu_cva5/system_verilog/test_benches/verilator/AXI_DDR_simulation/axi_ddr_sim.h -> build/lib/pythondata_cpu_cva5/system_verilog/test_benches/verilator/AXI_DDR_simulation
copying pythondata_cpu_cva5/system_verilog/test_benches/verilator/AXI_DDR_simulation/axi_interface.h -> build/lib/pythondata_cpu_cva5/system_verilog/test_benches/verilator/AXI_DDR_simulation
copying pythondata_cpu_cva5/system_verilog/test_benches/verilator/AXI_DDR_simulation/axi_l2_test.cc -> build/lib/pythondata_cpu_cva5/system_verilog/test_benches/verilator/AXI_DDR_simulation
copying pythondata_cpu_cva5/system_verilog/test_benches/verilator/AXI_DDR_simulation/axi_l2_test.sv -> build/lib/pythondata_cpu_cva5/system_verilog/test_benches/verilator/AXI_DDR_simulation
copying pythondata_cpu_cva5/system_verilog/test_benches/verilator/AXI_DDR_simulation/ddr_page.cc -> build/lib/pythondata_cpu_cva5/system_verilog/test_benches/verilator/AXI_DDR_simulation
copying pythondata_cpu_cva5/system_verilog/test_benches/verilator/AXI_DDR_simulation/ddr_page.h -> build/lib/pythondata_cpu_cva5/system_verilog/test_benches/verilator/AXI_DDR_simulation
copying pythondata_cpu_cva5/system_verilog/test_benches/verilator/AXI_DDR_simulation/main.cc -> build/lib/pythondata_cpu_cva5/system_verilog/test_benches/verilator/AXI_DDR_simulation
creating build/lib/pythondata_cpu_cva5/system_verilog/tools
copying pythondata_cpu_cva5/system_verilog/tools/.gitignore -> build/lib/pythondata_cpu_cva5/system_verilog/tools
copying pythondata_cpu_cva5/system_verilog/tools/compile_order -> build/lib/pythondata_cpu_cva5/system_verilog/tools
copying pythondata_cpu_cva5/system_verilog/tools/cva5.mak -> build/lib/pythondata_cpu_cva5/system_verilog/tools
copying pythondata_cpu_cva5/system_verilog/tools/elf-to-hw-init.py -> build/lib/pythondata_cpu_cva5/system_verilog/tools
+ RPM_EC=0
++ jobs -p
+ exit 0
Executing(%install): /bin/sh -e /var/tmp/rpm-tmp.qjL4ui
+ umask 022
+ cd /builddir/build/BUILD
+ '[' /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64 '!=' / ']'
+ rm -rf /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64
++ dirname /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64
+ mkdir -p /builddir/build/BUILDROOT
+ mkdir /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64
+ cd litex-pythondata-cpu-cva5
+ CFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-D_FORTIFY_SOURCE=2 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fstack-clash-protection'
+ LDFLAGS='-Wl,-z,relro -Wl,--as-needed  -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 '
+ /usr/bin/python3 setup.py install -O1 --skip-build --root /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64
running install
running install_lib
creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr
creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib
creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9
creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages
creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5
creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog
creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/tools
copying build/lib/pythondata_cpu_cva5/system_verilog/tools/elf-to-hw-init.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/tools
copying build/lib/pythondata_cpu_cva5/system_verilog/tools/cva5.mak -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/tools
copying build/lib/pythondata_cpu_cva5/system_verilog/tools/compile_order -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/tools
copying build/lib/pythondata_cpu_cva5/system_verilog/tools/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/tools
creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/test_benches
creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/test_benches/verilator
creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/test_benches/verilator/AXI_DDR_simulation
copying build/lib/pythondata_cpu_cva5/system_verilog/test_benches/verilator/AXI_DDR_simulation/main.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/test_benches/verilator/AXI_DDR_simulation
copying build/lib/pythondata_cpu_cva5/system_verilog/test_benches/verilator/AXI_DDR_simulation/ddr_page.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/test_benches/verilator/AXI_DDR_simulation
copying build/lib/pythondata_cpu_cva5/system_verilog/test_benches/verilator/AXI_DDR_simulation/ddr_page.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/test_benches/verilator/AXI_DDR_simulation
copying build/lib/pythondata_cpu_cva5/system_verilog/test_benches/verilator/AXI_DDR_simulation/axi_l2_test.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/test_benches/verilator/AXI_DDR_simulation
copying build/lib/pythondata_cpu_cva5/system_verilog/test_benches/verilator/AXI_DDR_simulation/axi_l2_test.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/test_benches/verilator/AXI_DDR_simulation
copying build/lib/pythondata_cpu_cva5/system_verilog/test_benches/verilator/AXI_DDR_simulation/axi_interface.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/test_benches/verilator/AXI_DDR_simulation
copying build/lib/pythondata_cpu_cva5/system_verilog/test_benches/verilator/AXI_DDR_simulation/axi_ddr_sim.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/test_benches/verilator/AXI_DDR_simulation
copying build/lib/pythondata_cpu_cva5/system_verilog/test_benches/verilator/AXI_DDR_simulation/axi_ddr_sim.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/test_benches/verilator/AXI_DDR_simulation
copying build/lib/pythondata_cpu_cva5/system_verilog/test_benches/verilator/AXI_DDR_simulation/DDR_init.txt -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/test_benches/verilator/AXI_DDR_simulation
copying build/lib/pythondata_cpu_cva5/system_verilog/test_benches/verilator/cva5_sim.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/test_benches/verilator
copying build/lib/pythondata_cpu_cva5/system_verilog/test_benches/verilator/cva5_sim.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/test_benches/verilator
copying build/lib/pythondata_cpu_cva5/system_verilog/test_benches/verilator/SimMem.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/test_benches/verilator
copying build/lib/pythondata_cpu_cva5/system_verilog/test_benches/verilator/SimMem.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/test_benches/verilator
copying build/lib/pythondata_cpu_cva5/system_verilog/test_benches/verilator/CVA5Tracer.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/test_benches/verilator
copying build/lib/pythondata_cpu_cva5/system_verilog/test_benches/verilator/CVA5Tracer.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/test_benches/verilator
creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/test_benches/unit_test_benches
copying build/lib/pythondata_cpu_cva5/system_verilog/test_benches/unit_test_benches/mul_unit_tb.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/test_benches/unit_test_benches
copying build/lib/pythondata_cpu_cva5/system_verilog/test_benches/unit_test_benches/div_unit_tb.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/test_benches/unit_test_benches
copying build/lib/pythondata_cpu_cva5/system_verilog/test_benches/unit_test_benches/alu_unit_tb.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/test_benches/unit_test_benches
copying build/lib/pythondata_cpu_cva5/system_verilog/test_benches/sim_mem.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/test_benches
copying build/lib/pythondata_cpu_cva5/system_verilog/test_benches/cva5_tb.wcfg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/test_benches
copying build/lib/pythondata_cpu_cva5/system_verilog/test_benches/cva5_tb.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/test_benches
copying build/lib/pythondata_cpu_cva5/system_verilog/test_benches/axi_mem_sim.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/test_benches
creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/scripts
creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/scripts/xilinx
copying build/lib/pythondata_cpu_cva5/system_verilog/scripts/xilinx/local_memory_IP.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/scripts/xilinx
copying build/lib/pythondata_cpu_cva5/system_verilog/scripts/xilinx/cva5_wrapper_IP.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/scripts/xilinx
creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/local_memory
copying build/lib/pythondata_cpu_cva5/system_verilog/local_memory/local_memory_interface.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/local_memory
copying build/lib/pythondata_cpu_cva5/system_verilog/local_memory/local_mem.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/local_memory
creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/l2_arbiter
copying build/lib/pythondata_cpu_cva5/system_verilog/l2_arbiter/l2_round_robin.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/l2_arbiter
copying build/lib/pythondata_cpu_cva5/system_verilog/l2_arbiter/l2_reservation_logic.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/l2_arbiter
copying build/lib/pythondata_cpu_cva5/system_verilog/l2_arbiter/l2_interfaces.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/l2_arbiter
copying build/lib/pythondata_cpu_cva5/system_verilog/l2_arbiter/l2_fifo.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/l2_arbiter
copying build/lib/pythondata_cpu_cva5/system_verilog/l2_arbiter/l2_external_interfaces.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/l2_arbiter
copying build/lib/pythondata_cpu_cva5/system_verilog/l2_arbiter/l2_config_and_types.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/l2_arbiter
copying build/lib/pythondata_cpu_cva5/system_verilog/l2_arbiter/l2_arbiter.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/l2_arbiter
creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/formal
creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/formal/scripts
copying build/lib/pythondata_cpu_cva5/system_verilog/formal/scripts/setup_cva5_dev.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/formal/scripts
copying build/lib/pythondata_cpu_cva5/system_verilog/formal/scripts/cva5_rtl.vfile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/formal/scripts
creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/formal/models
copying build/lib/pythondata_cpu_cva5/system_verilog/formal/models/cva5_formal_wrapper.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/formal/models
copying build/lib/pythondata_cpu_cva5/system_verilog/formal/models/cva5_fbm.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/formal/models
creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/formal/interfaces
copying build/lib/pythondata_cpu_cva5/system_verilog/formal/interfaces/axi4_basic_props.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/formal/interfaces
creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/examples
creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/examples/zedboard
creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/examples/zedboard/scripts
copying build/lib/pythondata_cpu_cva5/system_verilog/examples/zedboard/scripts/zedboard_master_XDC_RevC_D_v3.xdc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/examples/zedboard/scripts
copying build/lib/pythondata_cpu_cva5/system_verilog/examples/zedboard/scripts/design_1_wrapper.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/examples/zedboard/scripts
copying build/lib/pythondata_cpu_cva5/system_verilog/examples/zedboard/scripts/cva5-ip-core-base.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/examples/zedboard/scripts
copying build/lib/pythondata_cpu_cva5/system_verilog/examples/zedboard/zedboard.xdc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/examples/zedboard
copying build/lib/pythondata_cpu_cva5/system_verilog/examples/zedboard/xilinx_wiring_sample.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/examples/zedboard
copying build/lib/pythondata_cpu_cva5/system_verilog/examples/zedboard/system_periperhals.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/examples/zedboard
copying build/lib/pythondata_cpu_cva5/system_verilog/examples/zedboard/system.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/examples/zedboard
copying build/lib/pythondata_cpu_cva5/system_verilog/examples/zedboard/simulator_output_example.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/examples/zedboard
copying build/lib/pythondata_cpu_cva5/system_verilog/examples/zedboard/dhrystone.riscv.sim_init -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/examples/zedboard
copying build/lib/pythondata_cpu_cva5/system_verilog/examples/zedboard/dhrystone.riscv.hw_init -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/examples/zedboard
copying build/lib/pythondata_cpu_cva5/system_verilog/examples/zedboard/cva5_wrapper.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/examples/zedboard
copying build/lib/pythondata_cpu_cva5/system_verilog/examples/zedboard/cva5_small.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/examples/zedboard
copying build/lib/pythondata_cpu_cva5/system_verilog/examples/zedboard/cva5.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/examples/zedboard
copying build/lib/pythondata_cpu_cva5/system_verilog/examples/zedboard/arm.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/examples/zedboard
copying build/lib/pythondata_cpu_cva5/system_verilog/examples/zedboard/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/examples/zedboard
creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/examples/litex
copying build/lib/pythondata_cpu_cva5/system_verilog/examples/litex/litex_wrapper.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/examples/litex
copying build/lib/pythondata_cpu_cva5/system_verilog/examples/litex/l1_to_wishbone.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/examples/litex
creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/debug_module
copying build/lib/pythondata_cpu_cva5/system_verilog/debug_module/jtag_registers.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/debug_module
copying build/lib/pythondata_cpu_cva5/system_verilog/debug_module/jtag_register.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/debug_module
copying build/lib/pythondata_cpu_cva5/system_verilog/debug_module/jtag_module.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/debug_module
copying build/lib/pythondata_cpu_cva5/system_verilog/debug_module/debug_module.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/debug_module
copying build/lib/pythondata_cpu_cva5/system_verilog/debug_module/debug_interfaces.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/debug_module
copying build/lib/pythondata_cpu_cva5/system_verilog/debug_module/debug_cfg_types.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/debug_module
copying build/lib/pythondata_cpu_cva5/system_verilog/debug_module/.gitkeep -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/debug_module
creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/xilinx
copying build/lib/pythondata_cpu_cva5/system_verilog/core/xilinx/xilinx_byte_enable_ram.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/xilinx
copying build/lib/pythondata_cpu_cva5/system_verilog/core/xilinx/cva5_wrapper_xilinx.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/xilinx
creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/lutrams
copying build/lib/pythondata_cpu_cva5/system_verilog/core/lutrams/lutram_1w_mr.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/lutrams
copying build/lib/pythondata_cpu_cva5/system_verilog/core/lutrams/lutram_1w_1r.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/lutrams
creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/intel
copying build/lib/pythondata_cpu_cva5/system_verilog/core/intel/intel_byte_enable_ram.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/intel
copying build/lib/pythondata_cpu_cva5/system_verilog/core/writeback.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/wishbone_master.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/toggle_memory_set.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/toggle_memory.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/tlb_lut_ram.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/tag_bank.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/store_queue.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/shift_counter.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/set_clr_reg_with_rst.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/riscv_types.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/renamer.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/register_free_list.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/register_file.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/register_bank.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/reg_inuse.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/ras.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/priority_encoder.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/placer_randomizer.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/one_hot_to_integer.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/one_hot_occupancy.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/mul_unit.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/mmu.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/local_mem_sub_unit.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/load_store_unit.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/load_store_queue.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/lfsr.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/l1_arbiter.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/itag_banks.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/interfaces.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/instruction_metadata_and_id_management.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/illegal_instruction_checker.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/icache.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/gc_unit.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/fetch.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/external_interfaces.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/dtag_banks.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/div_unit.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/div_core.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/decode_and_issue.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/ddata_bank.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/dcache.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/cycler.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/cva5_types.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/cva5_fifo.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/cva5_config.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/cva5.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/csr_unit.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/csr_types.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/clz.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/byte_en_BRAM.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/branch_unit.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/branch_predictor_ram.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/branch_predictor.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/branch_comparator.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/binary_occupancy.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/barrel_shifter.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/axi_to_arb.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/axi_master.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/avalon_master.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/amo_alu.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/alu_unit.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/core/addr_hash.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core
copying build/lib/pythondata_cpu_cva5/system_verilog/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog
copying build/lib/pythondata_cpu_cva5/system_verilog/LICENSE -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog
copying build/lib/pythondata_cpu_cva5/system_verilog/.gitlab-ci.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog
copying build/lib/pythondata_cpu_cva5/__init__.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5
byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/tools/elf-to-hw-init.py to elf-to-hw-init.cpython-39.pyc
byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5/__init__.py to __init__.cpython-39.pyc
writing byte-compilation script '/tmp/tmpx3dsf04p.py'
/usr/bin/python3 /tmp/tmpx3dsf04p.py
removing /tmp/tmpx3dsf04p.py
running install_egg_info
running egg_info
writing pythondata_cpu_cva5.egg-info/PKG-INFO
writing dependency_links to pythondata_cpu_cva5.egg-info/dependency_links.txt
writing top-level names to pythondata_cpu_cva5.egg-info/top_level.txt
reading manifest file 'pythondata_cpu_cva5.egg-info/SOURCES.txt'
reading manifest template 'MANIFEST.in'
warning: no previously-included files matching '*.py[cod]' found anywhere in distribution
adding license file 'LICENSE'
writing manifest file 'pythondata_cpu_cva5.egg-info/SOURCES.txt'
Copying pythondata_cpu_cva5.egg-info to /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_cva5-0.0.post649-py3.9.egg-info
running install_scripts
+ rm -rfv /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/bin/__pycache__
+ /usr/lib/rpm/check-buildroot
+ /usr/lib/rpm/redhat/brp-ldconfig
+ /usr/lib/rpm/brp-compress
+ /usr/lib/rpm/brp-strip /bin/true
+ /usr/lib/rpm/brp-strip-comment-note /bin/true /usr/bin/objdump
+ /usr/lib/rpm/redhat/brp-strip-lto /bin/true
+ /usr/lib/rpm/brp-strip-static-archive /bin/true
+ /usr/lib/rpm/redhat/brp-python-bytecompile '' 1 0
Bytecompiling .py files below /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/lib/python3.9 using python3.9
+ /usr/lib/rpm/brp-python-hardlink
+ /usr/lib/rpm/redhat/brp-mangle-shebangs
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/LICENSE is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/README.md is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/alu_unit.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/amo_alu.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/axi_master.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/axi_to_arb.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/barrel_shifter.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/binary_occupancy.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/branch_predictor.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/branch_unit.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/byte_en_BRAM.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/csr_unit.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/cva5.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/cva5_config.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/cva5_fifo.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/cva5_types.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/cycler.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/dcache.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/ddata_bank.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/decode_and_issue.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/div_unit.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/dtag_banks.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/fetch.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/icache.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/interfaces.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/itag_banks.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/l1_arbiter.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/load_store_unit.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/local_mem_sub_unit.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/mmu.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/mul_unit.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/one_hot_occupancy.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/one_hot_to_integer.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/ras.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/register_file.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/tag_bank.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/tlb_lut_ram.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/intel/intel_byte_enable_ram.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/core/xilinx/xilinx_byte_enable_ram.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/examples/litex/litex_wrapper.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/examples/zedboard/README.md is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/examples/zedboard/arm.tcl is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/examples/zedboard/cva5_wrapper.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/examples/zedboard/system_periperhals.tcl is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/formal/interfaces/axi4_basic_props.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/formal/models/cva5_fbm.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/formal/models/cva5_formal_wrapper.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/l2_arbiter/l2_arbiter.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/l2_arbiter/l2_config_and_types.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/l2_arbiter/l2_fifo.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/l2_arbiter/l2_interfaces.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/l2_arbiter/l2_reservation_logic.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/l2_arbiter/l2_round_robin.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/test_benches/axi_mem_sim.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/test_benches/cva5_tb.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/test_benches/cva5_tb.wcfg is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/test_benches/sim_mem.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/test_benches/unit_test_benches/alu_unit_tb.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/test_benches/unit_test_benches/div_unit_tb.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/test_benches/unit_test_benches/mul_unit_tb.sv is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.9/site-packages/pythondata_cpu_cva5/system_verilog/tools/elf-to-hw-init.py is executable but has no shebang, removing executable bit
Processing files: litex-pythondata-cpu-cva5-python3-2022.12-20220530.3.gitea1075d6.el9.noarch
Executing(%doc): /bin/sh -e /var/tmp/rpm-tmp.ZuRUeb
+ umask 022
+ cd /builddir/build/BUILD
+ cd litex-pythondata-cpu-cva5
+ DOCDIR=/builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/share/doc/litex-pythondata-cpu-cva5-python3
+ export LC_ALL=C
+ LC_ALL=C
+ export DOCDIR
+ /usr/bin/mkdir -p /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/share/doc/litex-pythondata-cpu-cva5-python3
+ cp -pr README.md /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/share/doc/litex-pythondata-cpu-cva5-python3
+ RPM_EC=0
++ jobs -p
+ exit 0
Executing(%license): /bin/sh -e /var/tmp/rpm-tmp.NDCcd0
+ umask 022
+ cd /builddir/build/BUILD
+ cd litex-pythondata-cpu-cva5
+ LICENSEDIR=/builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/share/licenses/litex-pythondata-cpu-cva5-python3
+ export LC_ALL=C
+ LC_ALL=C
+ export LICENSEDIR
+ /usr/bin/mkdir -p /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/share/licenses/litex-pythondata-cpu-cva5-python3
+ cp -pr LICENSE /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64/usr/share/licenses/litex-pythondata-cpu-cva5-python3
+ RPM_EC=0
++ jobs -p
+ exit 0
Provides: litex-pythondata-cpu-cva5-python3 = 2022.12-20220530.3.gitea1075d6.el9 python3.9dist(pythondata-cpu-cva5) = 0^post649 python3dist(pythondata-cpu-cva5) = 0^post649 pythondata-cpu-cva5
Requires(rpmlib): rpmlib(CompressedFileNames) <= 3.0.4-1 rpmlib(FileDigests) <= 4.6.0-1 rpmlib(PartialHardlinkSets) <= 4.0.4-1 rpmlib(PayloadFilesHavePrefix) <= 4.0-1
Requires: python(abi) = 3.9
Checking for unpackaged file(s): /usr/lib/rpm/check-files /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64
Wrote: /builddir/build/RPMS/litex-pythondata-cpu-cva5-python3-2022.12-20220530.3.gitea1075d6.el9.noarch.rpm
Executing(%clean): /bin/sh -e /var/tmp/rpm-tmp.iuG5yO
+ umask 022
+ cd /builddir/build/BUILD
+ cd litex-pythondata-cpu-cva5
+ /usr/bin/rm -rf /builddir/build/BUILDROOT/litex-pythondata-cpu-cva5-2022.12-20220530.3.gitea1075d6.el9.aarch64
+ RPM_EC=0
++ jobs -p
+ exit 0
Child return code was: 0