Warning: Permanently added '44.222.211.26' (ED25519) to the list of known hosts. You can reproduce this build on your computer by running: sudo dnf install copr-rpmbuild /usr/bin/copr-rpmbuild --verbose --drop-resultdir --task-url https://copr.fedorainfracloud.org/backend/get-build-task/7096668-fedora-39-aarch64 --chroot fedora-39-aarch64 Version: 0.70 PID: 6635 Logging PID: 6636 Task: {'appstream': False, 'background': False, 'build_id': 7096668, 'buildroot_pkgs': [], 'chroot': 'fedora-39-aarch64', 'enable_net': True, 'fedora_review': False, 'git_hash': 'a57176dae536103f9c43a6afd653e8bf9f74de0d', 'git_repo': 'https://copr-dist-git.fedorainfracloud.org/git/rezso/HDL/litex-pythondata-cpu-rocket', 'isolation': 'default', 'memory_reqs': 2048, 'package_name': 'litex-pythondata-cpu-rocket', 'package_version': '2023.12-20240219.0.git55d7e429', 'project_dirname': 'HDL', 'project_name': 'HDL', 'project_owner': 'rezso', 'repo_priority': None, 'repos': [{'baseurl': 'https://download.copr.fedorainfracloud.org/results/rezso/HDL/fedora-39-aarch64/', 'id': 'copr_base', 'name': 'Copr repository', 'priority': None}, {'baseurl': 'https://download.copr.fedorainfracloud.org/results/rezso/ML/fedora-39-aarch64/', 'id': 'copr_rezso_ML', 'name': 'Additional repo copr_rezso_ML'}, {'baseurl': 'https://download.copr.fedorainfracloud.org/results/rezso/CUDA/fedora-39-aarch64/', 'id': 'copr_rezso_CUDA', 'name': 'Additional repo copr_rezso_CUDA'}, {'baseurl': 'http://developer.download.nvidia.com/compute/cuda/repos/rhel8/x86_64', 'id': 'http_developer_download_nvidia_com_compute_cuda_repos_rhel8_x86_64', 'name': 'Additional repo http_developer_download_nvidia_com_compute_cuda_repos_rhel8_x86_64'}, {'baseurl': 'http://developer.download.nvidia.com/compute/cuda/repos/rhel8/sbsa', 'id': 'http_developer_download_nvidia_com_compute_cuda_repos_rhel8_sbsa', 'name': 'Additional repo http_developer_download_nvidia_com_compute_cuda_repos_rhel8_sbsa'}, {'baseurl': 'http://developer.download.nvidia.com/compute/cuda/repos/rhel8/ppc64le', 'id': 'http_developer_download_nvidia_com_compute_cuda_repos_rhel8_ppc64le', 'name': 'Additional repo http_developer_download_nvidia_com_compute_cuda_repos_rhel8_ppc64le'}], 'sandbox': 'rezso/HDL--rezso', 'source_json': {}, 'source_type': None, 'submitter': 'rezso', 'tags': [], 'task_id': '7096668-fedora-39-aarch64', 'timeout': 172800, 'uses_devel_repo': False, 'with_opts': [], 'without_opts': []} Running: git clone https://copr-dist-git.fedorainfracloud.org/git/rezso/HDL/litex-pythondata-cpu-rocket /var/lib/copr-rpmbuild/workspace/workdir-8rujp7yt/litex-pythondata-cpu-rocket --depth 500 --no-single-branch --recursive cmd: ['git', 'clone', 'https://copr-dist-git.fedorainfracloud.org/git/rezso/HDL/litex-pythondata-cpu-rocket', '/var/lib/copr-rpmbuild/workspace/workdir-8rujp7yt/litex-pythondata-cpu-rocket', '--depth', '500', '--no-single-branch', '--recursive'] cwd: . rc: 0 stdout: stderr: Cloning into '/var/lib/copr-rpmbuild/workspace/workdir-8rujp7yt/litex-pythondata-cpu-rocket'... Running: git checkout a57176dae536103f9c43a6afd653e8bf9f74de0d -- cmd: ['git', 'checkout', 'a57176dae536103f9c43a6afd653e8bf9f74de0d', '--'] cwd: /var/lib/copr-rpmbuild/workspace/workdir-8rujp7yt/litex-pythondata-cpu-rocket rc: 0 stdout: stderr: Note: switching to 'a57176dae536103f9c43a6afd653e8bf9f74de0d'. You are in 'detached HEAD' state. You can look around, make experimental changes and commit them, and you can discard any commits you make in this state without impacting any branches by switching back to a branch. If you want to create a new branch to retain commits you create, you may do so (now or later) by using -c with the switch command. Example: git switch -c Or undo this operation with: git switch - Turn off this advice by setting config variable advice.detachedHead to false HEAD is now at a57176d automatic import of litex-pythondata-cpu-rocket Running: copr-distgit-client sources cmd: ['copr-distgit-client', 'sources'] cwd: /var/lib/copr-rpmbuild/workspace/workdir-8rujp7yt/litex-pythondata-cpu-rocket rc: 0 stdout: stderr: INFO: Reading stdout from command: git rev-parse --abbrev-ref HEAD INFO: Reading stdout from command: git rev-parse HEAD INFO: Reading sources specification file: sources /usr/bin/tail: /var/lib/copr-rpmbuild/main.log: file truncated Running (timeout=172800): unbuffer mock --spec /var/lib/copr-rpmbuild/workspace/workdir-8rujp7yt/litex-pythondata-cpu-rocket/litex-pythondata-cpu-rocket.spec --sources /var/lib/copr-rpmbuild/workspace/workdir-8rujp7yt/litex-pythondata-cpu-rocket --resultdir /var/lib/copr-rpmbuild/results --uniqueext 1709342025.186079 -r /var/lib/copr-rpmbuild/results/configs/child.cfg INFO: mock.py version 5.5 starting (python version = 3.12.1, NVR = mock-5.5-1.fc39), args: /usr/libexec/mock/mock --spec /var/lib/copr-rpmbuild/workspace/workdir-8rujp7yt/litex-pythondata-cpu-rocket/litex-pythondata-cpu-rocket.spec --sources /var/lib/copr-rpmbuild/workspace/workdir-8rujp7yt/litex-pythondata-cpu-rocket --resultdir /var/lib/copr-rpmbuild/results --uniqueext 1709342025.186079 -r /var/lib/copr-rpmbuild/results/configs/child.cfg Start(bootstrap): init plugins INFO: tmpfs initialized INFO: selinux enabled INFO: chroot_scan: initialized INFO: compress_logs: initialized Finish(bootstrap): init plugins Start: init plugins INFO: tmpfs initialized INFO: selinux enabled INFO: chroot_scan: initialized INFO: compress_logs: initialized Finish: init plugins INFO: Signal handler active Start: run INFO: Start(/var/lib/copr-rpmbuild/workspace/workdir-8rujp7yt/litex-pythondata-cpu-rocket/litex-pythondata-cpu-rocket.spec) Config(fedora-39-aarch64) Start: clean chroot Finish: clean chroot Mock Version: 5.5 INFO: Mock Version: 5.5 Start(bootstrap): chroot init INFO: mounting tmpfs at /var/lib/mock/fedora-39-aarch64-bootstrap-1709342025.186079/root. INFO: calling preinit hooks INFO: enabled root cache INFO: enabled package manager cache Start(bootstrap): cleaning package manager metadata Finish(bootstrap): cleaning package manager metadata INFO: Guessed host environment type: unknown INFO: Using bootstrap image: registry.fedoraproject.org/fedora:39 INFO: Pulling image: registry.fedoraproject.org/fedora:39 INFO: Copy content of container registry.fedoraproject.org/fedora:39 to /var/lib/mock/fedora-39-aarch64-bootstrap-1709342025.186079/root INFO: Checking that registry.fedoraproject.org/fedora:39 image matches host's architecture INFO: mounting registry.fedoraproject.org/fedora:39 with podman image mount INFO: image registry.fedoraproject.org/fedora:39 as /var/lib/containers/storage/overlay/5663d2b0f39cbf19384039014059b724d3e69c4c6585956f862c61164e77495f/merged INFO: umounting image registry.fedoraproject.org/fedora:39 (/var/lib/containers/storage/overlay/5663d2b0f39cbf19384039014059b724d3e69c4c6585956f862c61164e77495f/merged) with podman image umount INFO: Package manager dnf detected and used (fallback) INFO: Bootstrap image not marked ready Start(bootstrap): installing dnf tooling No matches found for the following disable plugin patterns: local, spacewalk, versionlock Copr repository 19 MB/s | 1.2 MB 00:00 Additional repo copr_rezso_ML 27 MB/s | 1.2 MB 00:00 Additional repo copr_rezso_CUDA 1.3 MB/s | 57 kB 00:00 Additional repo http_developer_download_nvidia_ 150 MB/s | 3.1 MB 00:00 Additional repo http_developer_download_nvidia_ 15 MB/s | 1.9 MB 00:00 Additional repo http_developer_download_nvidia_ 117 MB/s | 1.7 MB 00:00 fedora 24 MB/s | 86 MB 00:03 updates 17 MB/s | 32 MB 00:01 Package python3-dnf-4.18.1-2.fc39.noarch is already installed. Dependencies resolved. ================================================================================ Package Arch Version Repository Size ================================================================================ Installing: python3-dnf-plugins-core noarch 4.5.0-1.fc39 updates 318 k Upgrading: dnf noarch 4.19.0-1.fc39 updates 508 k dnf-data noarch 4.19.0-1.fc39 updates 40 k libdnf aarch64 0.73.0-1.fc39 updates 629 k python3-dnf noarch 4.19.0-1.fc39 updates 591 k python3-hawkey aarch64 0.73.0-1.fc39 updates 99 k python3-libdnf aarch64 0.73.0-1.fc39 updates 809 k yum noarch 4.19.0-1.fc39 updates 37 k Installing dependencies: dbus-libs aarch64 1:1.14.10-1.fc39 fedora 156 k python3-dateutil noarch 1:2.8.2-10.fc39 fedora 355 k python3-dbus aarch64 1.3.2-4.fc39 fedora 157 k python3-distro noarch 1.8.0-6.fc39 fedora 49 k python3-six noarch 1.16.0-12.fc39 fedora 41 k python3-systemd aarch64 235-5.fc39 fedora 107 k Transaction Summary ================================================================================ Install 7 Packages Upgrade 7 Packages Total download size: 3.8 M Downloading Packages: (1/14): dbus-libs-1.14.10-1.fc39.aarch64.rpm 471 kB/s | 156 kB 00:00 (2/14): python3-dbus-1.3.2-4.fc39.aarch64.rpm 457 kB/s | 157 kB 00:00 (3/14): python3-distro-1.8.0-6.fc39.noarch.rpm 878 kB/s | 49 kB 00:00 (4/14): python3-dateutil-2.8.2-10.fc39.noarch.r 918 kB/s | 355 kB 00:00 (5/14): python3-six-1.16.0-12.fc39.noarch.rpm 709 kB/s | 41 kB 00:00 (6/14): python3-systemd-235-5.fc39.aarch64.rpm 1.7 MB/s | 107 kB 00:00 (7/14): dnf-data-4.19.0-1.fc39.noarch.rpm 194 kB/s | 40 kB 00:00 (8/14): python3-dnf-plugins-core-4.5.0-1.fc39.n 653 kB/s | 318 kB 00:00 (9/14): dnf-4.19.0-1.fc39.noarch.rpm 1.0 MB/s | 508 kB 00:00 (10/14): python3-hawkey-0.73.0-1.fc39.aarch64.r 1.4 MB/s | 99 kB 00:00 (11/14): python3-dnf-4.19.0-1.fc39.noarch.rpm 4.1 MB/s | 591 kB 00:00 (12/14): libdnf-0.73.0-1.fc39.aarch64.rpm 1.5 MB/s | 629 kB 00:00 (13/14): yum-4.19.0-1.fc39.noarch.rpm 536 kB/s | 37 kB 00:00 (14/14): python3-libdnf-0.73.0-1.fc39.aarch64.r 5.6 MB/s | 809 kB 00:00 -------------------------------------------------------------------------------- Total 2.7 MB/s | 3.8 MB 00:01 Running transaction check Transaction check succeeded. Running transaction test Transaction test succeeded. Running transaction Preparing : 1/1 Upgrading : libdnf-0.73.0-1.fc39.aarch64 1/21 Upgrading : python3-libdnf-0.73.0-1.fc39.aarch64 2/21 Upgrading : python3-hawkey-0.73.0-1.fc39.aarch64 3/21 Upgrading : dnf-data-4.19.0-1.fc39.noarch 4/21 Upgrading : python3-dnf-4.19.0-1.fc39.noarch 5/21 Upgrading : dnf-4.19.0-1.fc39.noarch 6/21 Running scriptlet: dnf-4.19.0-1.fc39.noarch 6/21 Installing : python3-systemd-235-5.fc39.aarch64 7/21 Installing : python3-six-1.16.0-12.fc39.noarch 8/21 Installing : python3-dateutil-1:2.8.2-10.fc39.noarch 9/21 Installing : python3-distro-1.8.0-6.fc39.noarch 10/21 Installing : dbus-libs-1:1.14.10-1.fc39.aarch64 11/21 Installing : python3-dbus-1.3.2-4.fc39.aarch64 12/21 Installing : python3-dnf-plugins-core-4.5.0-1.fc39.noarch 13/21 Upgrading : yum-4.19.0-1.fc39.noarch 14/21 Cleanup : yum-4.18.1-2.fc39.noarch 15/21 Running scriptlet: dnf-4.18.1-2.fc39.noarch 16/21 Cleanup : dnf-4.18.1-2.fc39.noarch 16/21 Running scriptlet: dnf-4.18.1-2.fc39.noarch 16/21 Cleanup : python3-dnf-4.18.1-2.fc39.noarch 17/21 Cleanup : python3-hawkey-0.72.0-1.fc39.aarch64 18/21 Cleanup : dnf-data-4.18.1-2.fc39.noarch 19/21 Cleanup : python3-libdnf-0.72.0-1.fc39.aarch64 20/21 Cleanup : libdnf-0.72.0-1.fc39.aarch64 21/21 Running scriptlet: libdnf-0.72.0-1.fc39.aarch64 21/21 Verifying : dbus-libs-1:1.14.10-1.fc39.aarch64 1/21 Verifying : python3-dateutil-1:2.8.2-10.fc39.noarch 2/21 Verifying : python3-dbus-1.3.2-4.fc39.aarch64 3/21 Verifying : python3-distro-1.8.0-6.fc39.noarch 4/21 Verifying : python3-six-1.16.0-12.fc39.noarch 5/21 Verifying : python3-systemd-235-5.fc39.aarch64 6/21 Verifying : python3-dnf-plugins-core-4.5.0-1.fc39.noarch 7/21 Verifying : dnf-4.19.0-1.fc39.noarch 8/21 Verifying : dnf-4.18.1-2.fc39.noarch 9/21 Verifying : dnf-data-4.19.0-1.fc39.noarch 10/21 Verifying : dnf-data-4.18.1-2.fc39.noarch 11/21 Verifying : libdnf-0.73.0-1.fc39.aarch64 12/21 Verifying : libdnf-0.72.0-1.fc39.aarch64 13/21 Verifying : python3-dnf-4.19.0-1.fc39.noarch 14/21 Verifying : python3-dnf-4.18.1-2.fc39.noarch 15/21 Verifying : python3-hawkey-0.73.0-1.fc39.aarch64 16/21 Verifying : python3-hawkey-0.72.0-1.fc39.aarch64 17/21 Verifying : python3-libdnf-0.73.0-1.fc39.aarch64 18/21 Verifying : python3-libdnf-0.72.0-1.fc39.aarch64 19/21 Verifying : yum-4.19.0-1.fc39.noarch 20/21 Verifying : yum-4.18.1-2.fc39.noarch 21/21 Upgraded: dnf-4.19.0-1.fc39.noarch dnf-data-4.19.0-1.fc39.noarch libdnf-0.73.0-1.fc39.aarch64 python3-dnf-4.19.0-1.fc39.noarch python3-hawkey-0.73.0-1.fc39.aarch64 python3-libdnf-0.73.0-1.fc39.aarch64 yum-4.19.0-1.fc39.noarch Installed: dbus-libs-1:1.14.10-1.fc39.aarch64 python3-dateutil-1:2.8.2-10.fc39.noarch python3-dbus-1.3.2-4.fc39.aarch64 python3-distro-1.8.0-6.fc39.noarch python3-dnf-plugins-core-4.5.0-1.fc39.noarch python3-six-1.16.0-12.fc39.noarch python3-systemd-235-5.fc39.aarch64 Complete! Finish(bootstrap): installing dnf tooling Start(bootstrap): creating root cache Finish(bootstrap): creating root cache Finish(bootstrap): chroot init Start: chroot init INFO: mounting tmpfs at /var/lib/mock/fedora-39-aarch64-1709342025.186079/root. INFO: calling preinit hooks INFO: enabled root cache INFO: enabled package manager cache Start: cleaning package manager metadata Finish: cleaning package manager metadata INFO: enabled HW Info plugin INFO: Package manager dnf detected and used (direct choice) INFO: Buildroot is handled by package management downloaded with a bootstrap image: rpm-4.19.0-1.fc39.aarch64 rpm-sequoia-1.5.0-1.fc39.aarch64 python3-dnf-4.19.0-1.fc39.noarch python3-dnf-plugins-core-4.5.0-1.fc39.noarch yum-4.19.0-1.fc39.noarch Start: installing minimal buildroot with dnf No matches found for the following disable plugin patterns: local, spacewalk, versionlock Copr repository 27 MB/s | 1.2 MB 00:00 Additional repo copr_rezso_ML 29 MB/s | 1.2 MB 00:00 Additional repo copr_rezso_CUDA 1.3 MB/s | 57 kB 00:00 Additional repo http_developer_download_nvidia_ 174 MB/s | 3.1 MB 00:00 Additional repo http_developer_download_nvidia_ 131 MB/s | 1.9 MB 00:00 Additional repo http_developer_download_nvidia_ 104 MB/s | 1.7 MB 00:00 fedora 28 MB/s | 86 MB 00:03 updates 192 kB/s | 32 MB 02:50 Dependencies resolved. ========================================================================================= Package Arch Version Repository Size ========================================================================================= Installing group/module packages: bash aarch64 5.2.26-1.fc39 updates 1.8 M bzip2 aarch64 1.0.8-16.fc39 fedora 52 k coreutils aarch64 9.3-5.fc39 updates 1.2 M cpio aarch64 2.14-4.fc39 fedora 277 k diffutils aarch64 3.10-3.fc39 fedora 396 k fedora-release-common noarch 39-36 updates 19 k findutils aarch64 1:4.9.0-5.fc39 fedora 495 k gawk aarch64 5.2.2-2.fc39 fedora 1.1 M glibc-minimal-langpack aarch64 2.38-99.fc39 copr_rezso_ML 67 k grep aarch64 3.11-3.fc39 fedora 295 k gzip aarch64 1.12-6.fc39 fedora 164 k info aarch64 7.0.3-3.fc39 fedora 179 k patch aarch64 2.7.6-22.fc39 fedora 123 k redhat-rpm-config noarch 265-1.fc39 updates 78 k rpm-build aarch64 4.19.1.1-1.fc39 updates 79 k sed aarch64 4.8-14.fc39 fedora 304 k shadow-utils aarch64 2:4.14.0-2.fc39 updates 1.3 M tar aarch64 2:1.35-2.fc39 fedora 854 k unzip aarch64 6.0-62.fc39 fedora 183 k util-linux aarch64 2.39.3-6.fc39 updates 1.2 M which aarch64 2.21-40.fc39 fedora 42 k xz aarch64 5.4.4-1.fc39 fedora 556 k Installing dependencies: alternatives aarch64 1.26-1.fc39 updates 38 k ansible-srpm-macros noarch 1-12.fc39 updates 21 k audit-libs aarch64 3.1.2-8.fc39 updates 118 k authselect aarch64 1.4.3-1.fc39 fedora 150 k authselect-libs aarch64 1.4.3-1.fc39 fedora 249 k basesystem noarch 11-18.fc39 fedora 7.2 k binutils aarch64 2.40-14.fc39 updates 6.1 M binutils-gold aarch64 2.40-14.fc39 updates 945 k bzip2-libs aarch64 1.0.8-16.fc39 fedora 43 k ca-certificates noarch 2023.2.60_v7.0.306-2.fc39 fedora 837 k coreutils-common aarch64 9.3-5.fc39 updates 2.1 M cracklib aarch64 2.9.11-2.fc39 fedora 94 k crypto-policies noarch 20231204-1.git1e3a2e4.fc39 updates 100 k curl aarch64 8.2.1-4.fc39 updates 341 k cyrus-sasl-lib aarch64 2.1.28-11.fc39 fedora 781 k debugedit aarch64 5.0-12.fc39 updates 78 k dwz aarch64 0.15-3.fc39 fedora 136 k ed aarch64 1.19-4.fc39 fedora 78 k efi-srpm-macros noarch 5-9.fc39 fedora 22 k elfutils aarch64 0.190-4.fc39 updates 552 k elfutils-debuginfod-client aarch64 0.190-4.fc39 updates 37 k elfutils-default-yama-scope noarch 0.190-4.fc39 updates 13 k elfutils-libelf aarch64 0.190-4.fc39 updates 194 k elfutils-libs aarch64 0.190-4.fc39 updates 259 k fedora-gpg-keys noarch 39-1 fedora 130 k fedora-release noarch 39-36 updates 8.6 k fedora-release-identity-basic noarch 39-36 updates 9.4 k fedora-repos noarch 39-1 fedora 9.3 k file aarch64 5.44-5.fc39 fedora 49 k file-libs aarch64 5.44-5.fc39 fedora 729 k filesystem aarch64 3.18-6.fc39 fedora 1.1 M fonts-srpm-macros noarch 1:2.0.5-12.fc39 fedora 26 k forge-srpm-macros noarch 0.2.0-3.fc39 updates 19 k fpc-srpm-macros noarch 1.3-8.fc39 fedora 7.4 k gdb-minimal aarch64 14.1-4.fc39 updates 3.9 M gdbm-libs aarch64 1:1.23-4.fc39 fedora 56 k ghc-srpm-macros noarch 1.6.1-2.fc39 fedora 7.8 k glibc aarch64 2.38-99.fc39 copr_rezso_ML 1.7 M glibc-common aarch64 2.38-99.fc39 copr_rezso_ML 338 k glibc-gconv-extra aarch64 2.38-99.fc39 copr_rezso_ML 1.9 M gmp aarch64 1:6.2.1-5.fc39 fedora 266 k gnat-srpm-macros noarch 6-3.fc39 fedora 8.8 k go-srpm-macros noarch 3.4.0-2.fc39 updates 27 k jansson aarch64 2.13.1-7.fc39 fedora 46 k kernel-srpm-macros noarch 1.0-20.fc39 fedora 10 k keyutils-libs aarch64 1.6.1-7.fc39 fedora 31 k krb5-libs aarch64 1.21.2-3.fc39 updates 770 k libacl aarch64 2.3.1-9.fc39 updates 24 k libarchive aarch64 3.7.1-1.fc39 fedora 402 k libattr aarch64 2.5.1-8.fc39 fedora 18 k libblkid aarch64 2.39.3-6.fc39 updates 116 k libbrotli aarch64 1.1.0-1.fc39 fedora 345 k libcap aarch64 2.48-9.fc39 updates 69 k libcap-ng aarch64 0.8.3-8.fc39 fedora 32 k libcom_err aarch64 1.47.0-2.fc39 fedora 26 k libcurl aarch64 8.2.1-4.fc39 updates 317 k libdb aarch64 5.3.28-56.fc39 fedora 735 k libeconf aarch64 0.5.2-1.fc39 fedora 30 k libevent aarch64 2.1.12-9.fc39 fedora 254 k libfdisk aarch64 2.39.3-6.fc39 updates 158 k libffi aarch64 3.4.4-4.fc39 fedora 38 k libgcc aarch64 13.2.1-6.fc39 updates 97 k libgomp aarch64 13.2.1-6.fc39 updates 313 k libidn2 aarch64 2.3.7-1.fc39 updates 120 k libmount aarch64 2.39.3-6.fc39 updates 154 k libnghttp2 aarch64 1.55.1-4.fc39 updates 76 k libnsl2 aarch64 2.0.0-6.fc39 fedora 30 k libpkgconf aarch64 1.9.5-2.fc39 fedora 38 k libpsl aarch64 0.21.2-4.fc39 fedora 63 k libpwquality aarch64 1.4.5-6.fc39 fedora 120 k libselinux aarch64 3.5-5.fc39 fedora 86 k libsemanage aarch64 3.5-4.fc39 fedora 117 k libsepol aarch64 3.5-2.fc39 fedora 311 k libsigsegv aarch64 2.14-5.fc39 fedora 27 k libsmartcols aarch64 2.39.3-6.fc39 updates 66 k libssh aarch64 0.10.6-2.fc39 updates 213 k libssh-config noarch 0.10.6-2.fc39 updates 9.0 k libstdc++ aarch64 13.2.1-6.fc39 updates 815 k libtasn1 aarch64 4.19.0-3.fc39 fedora 73 k libtirpc aarch64 1.3.4-0.rc2.fc39 updates 95 k libunistring aarch64 1.1-5.fc39 fedora 540 k libutempter aarch64 1.2.1-10.fc39 fedora 27 k libuuid aarch64 2.39.3-6.fc39 updates 28 k libverto aarch64 0.3.2-6.fc39 fedora 21 k libxcrypt aarch64 4.4.36-2.fc39 fedora 123 k libxml2 aarch64 2.10.4-3.fc39 fedora 689 k libzstd aarch64 1.5.5-4.fc39 fedora 280 k lua-libs aarch64 5.4.6-3.fc39 fedora 131 k lua-srpm-macros noarch 1-13.fc39 updates 8.7 k lz4-libs aarch64 1.9.4-4.fc39 fedora 68 k mpfr aarch64 4.2.0-3.fc39 fedora 319 k ncurses-base noarch 6.4-7.20230520.fc39.1 updates 88 k ncurses-libs aarch64 6.4-7.20230520.fc39.1 updates 326 k ocaml-srpm-macros noarch 8-2.fc39 fedora 14 k openblas-srpm-macros noarch 2-14.fc39 fedora 7.5 k openldap aarch64 2.6.6-1.fc39 fedora 251 k openssl-libs aarch64 1:3.1.1-4.fc39 fedora 2.0 M p11-kit aarch64 0.25.3-1.fc39 updates 495 k p11-kit-trust aarch64 0.25.3-1.fc39 updates 141 k package-notes-srpm-macros noarch 0.5-9.fc39 fedora 11 k pam aarch64 1.5.3-3.fc39 updates 552 k pam-libs aarch64 1.5.3-3.fc39 updates 57 k pcre2 aarch64 10.42-1.fc39.2 fedora 219 k pcre2-syntax noarch 10.42-1.fc39.2 fedora 143 k perl-srpm-macros noarch 1-51.fc39 fedora 8.0 k pkgconf aarch64 1.9.5-2.fc39 fedora 42 k pkgconf-m4 noarch 1.9.5-2.fc39 fedora 14 k pkgconf-pkg-config aarch64 1.9.5-2.fc39 fedora 9.6 k popt aarch64 1.19-3.fc39 fedora 66 k publicsuffix-list-dafsa noarch 20240107-1.fc39 updates 58 k pyproject-srpm-macros noarch 1.12.0-1.fc39 updates 14 k python-srpm-macros noarch 3.12-4.fc39 fedora 25 k qt5-srpm-macros noarch 5.15.12-1.fc39 updates 8.4 k qt6-srpm-macros noarch 6.6.2-1.fc39 updates 8.9 k readline aarch64 8.2-6.fc39 updates 212 k rpm aarch64 4.19.1.1-1.fc39 updates 536 k rpm-build-libs aarch64 4.19.1.1-1.fc39 updates 91 k rpm-libs aarch64 4.19.1.1-1.fc39 updates 305 k rpm-sequoia aarch64 1.6.0-1.fc39 updates 817 k rpmautospec-rpm-macros noarch 0.6.3-1.fc39 updates 10 k rust-srpm-macros noarch 26.1-1.fc39 updates 13 k setup noarch 2.14.4-1.fc39 fedora 154 k sqlite-libs aarch64 3.42.0-7.fc39 fedora 677 k systemd-libs aarch64 254.9-1.fc39 updates 665 k util-linux-core aarch64 2.39.3-6.fc39 updates 506 k xxhash-libs aarch64 0.8.2-1.fc39 fedora 35 k xz-libs aarch64 5.4.4-1.fc39 fedora 106 k zip aarch64 3.0-39.fc39 fedora 262 k zlib aarch64 1.2.13-4.fc39 fedora 93 k zstd aarch64 1.5.5-4.fc39 fedora 446 k Installing Groups: Buildsystem building group Transaction Summary ========================================================================================= Install 152 Packages Total download size: 52 M Installed size: 302 M Downloading Packages: (1/152): glibc-common-2.38-99.fc39.aarch64.rpm 12 MB/s | 338 kB 00:00 (2/152): glibc-minimal-langpack-2.38-99.fc39.aa 8.4 MB/s | 67 kB 00:00 (3/152): glibc-2.38-99.fc39.aarch64.rpm 43 MB/s | 1.7 MB 00:00 (4/152): glibc-gconv-extra-2.38-99.fc39.aarch64 39 MB/s | 1.9 MB 00:00 (5/152): basesystem-11-18.fc39.noarch.rpm 65 kB/s | 7.2 kB 00:00 (6/152): bzip2-1.0.8-16.fc39.aarch64.rpm 318 kB/s | 52 kB 00:00 (7/152): authselect-1.4.3-1.fc39.aarch64.rpm 451 kB/s | 150 kB 00:00 (8/152): bzip2-libs-1.0.8-16.fc39.aarch64.rpm 771 kB/s | 43 kB 00:00 (9/152): authselect-libs-1.4.3-1.fc39.aarch64.r 698 kB/s | 249 kB 00:00 (10/152): cracklib-2.9.11-2.fc39.aarch64.rpm 1.5 MB/s | 94 kB 00:00 (11/152): ca-certificates-2023.2.60_v7.0.306-2. 3.7 MB/s | 837 kB 00:00 (12/152): cpio-2.14-4.fc39.aarch64.rpm 1.2 MB/s | 277 kB 00:00 (13/152): cyrus-sasl-lib-2.1.28-11.fc39.aarch64 4.2 MB/s | 781 kB 00:00 (14/152): diffutils-3.10-3.fc39.aarch64.rpm 6.8 MB/s | 396 kB 00:00 (15/152): dwz-0.15-3.fc39.aarch64.rpm 2.2 MB/s | 136 kB 00:00 (16/152): ed-1.19-4.fc39.aarch64.rpm 1.3 MB/s | 78 kB 00:00 (17/152): efi-srpm-macros-5-9.fc39.noarch.rpm 403 kB/s | 22 kB 00:00 (18/152): fedora-gpg-keys-39-1.noarch.rpm 2.3 MB/s | 130 kB 00:00 (19/152): file-5.44-5.fc39.aarch64.rpm 892 kB/s | 49 kB 00:00 (20/152): fedora-repos-39-1.noarch.rpm 156 kB/s | 9.3 kB 00:00 (21/152): findutils-4.9.0-5.fc39.aarch64.rpm 7.8 MB/s | 495 kB 00:00 (22/152): file-libs-5.44-5.fc39.aarch64.rpm 6.3 MB/s | 729 kB 00:00 (23/152): filesystem-3.18-6.fc39.aarch64.rpm 9.8 MB/s | 1.1 MB 00:00 (24/152): fonts-srpm-macros-2.0.5-12.fc39.noarc 441 kB/s | 26 kB 00:00 (25/152): fpc-srpm-macros-1.3-8.fc39.noarch.rpm 134 kB/s | 7.4 kB 00:00 (26/152): gawk-5.2.2-2.fc39.aarch64.rpm 18 MB/s | 1.1 MB 00:00 (27/152): ghc-srpm-macros-1.6.1-2.fc39.noarch.r 140 kB/s | 7.8 kB 00:00 (28/152): gdbm-libs-1.23-4.fc39.aarch64.rpm 936 kB/s | 56 kB 00:00 (29/152): gmp-6.2.1-5.fc39.aarch64.rpm 4.6 MB/s | 266 kB 00:00 (30/152): gnat-srpm-macros-6-3.fc39.noarch.rpm 160 kB/s | 8.8 kB 00:00 (31/152): grep-3.11-3.fc39.aarch64.rpm 4.7 MB/s | 295 kB 00:00 (32/152): gzip-1.12-6.fc39.aarch64.rpm 2.9 MB/s | 164 kB 00:00 (33/152): info-7.0.3-3.fc39.aarch64.rpm 3.1 MB/s | 179 kB 00:00 (34/152): jansson-2.13.1-7.fc39.aarch64.rpm 759 kB/s | 46 kB 00:00 (35/152): kernel-srpm-macros-1.0-20.fc39.noarch 190 kB/s | 10 kB 00:00 (36/152): keyutils-libs-1.6.1-7.fc39.aarch64.rp 563 kB/s | 31 kB 00:00 (37/152): libarchive-3.7.1-1.fc39.aarch64.rpm 6.4 MB/s | 402 kB 00:00 (38/152): libattr-2.5.1-8.fc39.aarch64.rpm 323 kB/s | 18 kB 00:00 (39/152): libbrotli-1.1.0-1.fc39.aarch64.rpm 6.0 MB/s | 345 kB 00:00 (40/152): libcap-ng-0.8.3-8.fc39.aarch64.rpm 534 kB/s | 32 kB 00:00 (41/152): libcom_err-1.47.0-2.fc39.aarch64.rpm 473 kB/s | 26 kB 00:00 (42/152): libdb-5.3.28-56.fc39.aarch64.rpm 12 MB/s | 735 kB 00:00 (43/152): libeconf-0.5.2-1.fc39.aarch64.rpm 502 kB/s | 30 kB 00:00 (44/152): libevent-2.1.12-9.fc39.aarch64.rpm 4.4 MB/s | 254 kB 00:00 (45/152): libffi-3.4.4-4.fc39.aarch64.rpm 683 kB/s | 38 kB 00:00 (46/152): libnsl2-2.0.0-6.fc39.aarch64.rpm 500 kB/s | 30 kB 00:00 (47/152): libpkgconf-1.9.5-2.fc39.aarch64.rpm 688 kB/s | 38 kB 00:00 (48/152): libpsl-0.21.2-4.fc39.aarch64.rpm 1.1 MB/s | 63 kB 00:00 (49/152): libpwquality-1.4.5-6.fc39.aarch64.rpm 1.9 MB/s | 120 kB 00:00 (50/152): libselinux-3.5-5.fc39.aarch64.rpm 1.5 MB/s | 86 kB 00:00 (51/152): libsemanage-3.5-4.fc39.aarch64.rpm 2.1 MB/s | 117 kB 00:00 (52/152): libsepol-3.5-2.fc39.aarch64.rpm 5.0 MB/s | 311 kB 00:00 (53/152): libsigsegv-2.14-5.fc39.aarch64.rpm 489 kB/s | 27 kB 00:00 (54/152): libtasn1-4.19.0-3.fc39.aarch64.rpm 1.3 MB/s | 73 kB 00:00 (55/152): libutempter-1.2.1-10.fc39.aarch64.rpm 484 kB/s | 27 kB 00:00 (56/152): libunistring-1.1-5.fc39.aarch64.rpm 8.5 MB/s | 540 kB 00:00 (57/152): libverto-0.3.2-6.fc39.aarch64.rpm 372 kB/s | 21 kB 00:00 (58/152): libxcrypt-4.4.36-2.fc39.aarch64.rpm 2.2 MB/s | 123 kB 00:00 (59/152): libxml2-2.10.4-3.fc39.aarch64.rpm 11 MB/s | 689 kB 00:00 (60/152): libzstd-1.5.5-4.fc39.aarch64.rpm 4.9 MB/s | 280 kB 00:00 (61/152): lua-libs-5.4.6-3.fc39.aarch64.rpm 2.3 MB/s | 131 kB 00:00 (62/152): lz4-libs-1.9.4-4.fc39.aarch64.rpm 1.1 MB/s | 68 kB 00:00 (63/152): mpfr-4.2.0-3.fc39.aarch64.rpm 5.5 MB/s | 319 kB 00:00 (64/152): ocaml-srpm-macros-8-2.fc39.noarch.rpm 245 kB/s | 14 kB 00:00 (65/152): openldap-2.6.6-1.fc39.aarch64.rpm 4.4 MB/s | 251 kB 00:00 (66/152): openblas-srpm-macros-2-14.fc39.noarch 126 kB/s | 7.5 kB 00:00 (67/152): package-notes-srpm-macros-0.5-9.fc39. 202 kB/s | 11 kB 00:00 (68/152): patch-2.7.6-22.fc39.aarch64.rpm 1.7 MB/s | 123 kB 00:00 (69/152): openssl-libs-3.1.1-4.fc39.aarch64.rpm 17 MB/s | 2.0 MB 00:00 (70/152): pcre2-10.42-1.fc39.2.aarch64.rpm 3.8 MB/s | 219 kB 00:00 (71/152): pcre2-syntax-10.42-1.fc39.2.noarch.rp 2.3 MB/s | 143 kB 00:00 (72/152): perl-srpm-macros-1-51.fc39.noarch.rpm 145 kB/s | 8.0 kB 00:00 (73/152): pkgconf-1.9.5-2.fc39.aarch64.rpm 764 kB/s | 42 kB 00:00 (74/152): pkgconf-m4-1.9.5-2.fc39.noarch.rpm 232 kB/s | 14 kB 00:00 (75/152): pkgconf-pkg-config-1.9.5-2.fc39.aarch 175 kB/s | 9.6 kB 00:00 (76/152): popt-1.19-3.fc39.aarch64.rpm 1.2 MB/s | 66 kB 00:00 (77/152): python-srpm-macros-3.12-4.fc39.noarch 417 kB/s | 25 kB 00:00 (78/152): sed-4.8-14.fc39.aarch64.rpm 5.3 MB/s | 304 kB 00:00 (79/152): setup-2.14.4-1.fc39.noarch.rpm 2.7 MB/s | 154 kB 00:00 (80/152): sqlite-libs-3.42.0-7.fc39.aarch64.rpm 11 MB/s | 677 kB 00:00 (81/152): tar-1.35-2.fc39.aarch64.rpm 14 MB/s | 854 kB 00:00 (82/152): unzip-6.0-62.fc39.aarch64.rpm 3.2 MB/s | 183 kB 00:00 (83/152): which-2.21-40.fc39.aarch64.rpm 697 kB/s | 42 kB 00:00 (84/152): xxhash-libs-0.8.2-1.fc39.aarch64.rpm 630 kB/s | 35 kB 00:00 (85/152): xz-5.4.4-1.fc39.aarch64.rpm 9.5 MB/s | 556 kB 00:00 (86/152): xz-libs-5.4.4-1.fc39.aarch64.rpm 1.7 MB/s | 106 kB 00:00 (87/152): zip-3.0-39.fc39.aarch64.rpm 4.6 MB/s | 262 kB 00:00 (88/152): zlib-1.2.13-4.fc39.aarch64.rpm 1.6 MB/s | 93 kB 00:00 (89/152): zstd-1.5.5-4.fc39.aarch64.rpm 6.1 MB/s | 446 kB 00:00 (90/152): alternatives-1.26-1.fc39.aarch64.rpm 92 kB/s | 38 kB 00:00 (91/152): ansible-srpm-macros-1-12.fc39.noarch. 50 kB/s | 21 kB 00:00 (92/152): audit-libs-3.1.2-8.fc39.aarch64.rpm 208 kB/s | 118 kB 00:00 (93/152): bash-5.2.26-1.fc39.aarch64.rpm 2.2 MB/s | 1.8 MB 00:00 (94/152): binutils-gold-2.40-14.fc39.aarch64.rp 1.4 MB/s | 945 kB 00:00 (95/152): coreutils-9.3-5.fc39.aarch64.rpm 8.6 MB/s | 1.2 MB 00:00 (96/152): crypto-policies-20231204-1.git1e3a2e4 778 kB/s | 100 kB 00:00 (97/152): coreutils-common-9.3-5.fc39.aarch64.r 8.9 MB/s | 2.1 MB 00:00 (98/152): curl-8.2.1-4.fc39.aarch64.rpm 1.4 MB/s | 341 kB 00:00 (99/152): debugedit-5.0-12.fc39.aarch64.rpm 402 kB/s | 78 kB 00:00 (100/152): binutils-2.40-14.fc39.aarch64.rpm 4.2 MB/s | 6.1 MB 00:01 (101/152): elfutils-debuginfod-client-0.190-4.f 261 kB/s | 37 kB 00:00 (102/152): elfutils-0.190-4.fc39.aarch64.rpm 2.3 MB/s | 552 kB 00:00 (103/152): elfutils-default-yama-scope-0.190-4. 100 kB/s | 13 kB 00:00 (104/152): elfutils-libelf-0.190-4.fc39.aarch64 1.0 MB/s | 194 kB 00:00 (105/152): elfutils-libs-0.190-4.fc39.aarch64.r 2.1 MB/s | 259 kB 00:00 (106/152): fedora-release-39-36.noarch.rpm 65 kB/s | 8.6 kB 00:00 (107/152): fedora-release-common-39-36.noarch.r 166 kB/s | 19 kB 00:00 (108/152): fedora-release-identity-basic-39-36. 79 kB/s | 9.4 kB 00:00 (109/152): forge-srpm-macros-0.2.0-3.fc39.noarc 157 kB/s | 19 kB 00:00 (110/152): go-srpm-macros-3.4.0-2.fc39.noarch.r 176 kB/s | 27 kB 00:00 (111/152): krb5-libs-1.21.2-3.fc39.aarch64.rpm 5.1 MB/s | 770 kB 00:00 (112/152): libacl-2.3.1-9.fc39.aarch64.rpm 153 kB/s | 24 kB 00:00 (113/152): gdb-minimal-14.1-4.fc39.aarch64.rpm 11 MB/s | 3.9 MB 00:00 (114/152): libblkid-2.39.3-6.fc39.aarch64.rpm 808 kB/s | 116 kB 00:00 (115/152): libcap-2.48-9.fc39.aarch64.rpm 570 kB/s | 69 kB 00:00 (116/152): libfdisk-2.39.3-6.fc39.aarch64.rpm 1.3 MB/s | 158 kB 00:00 (117/152): libcurl-8.2.1-4.fc39.aarch64.rpm 1.8 MB/s | 317 kB 00:00 (118/152): libgomp-13.2.1-6.fc39.aarch64.rpm 1.8 MB/s | 313 kB 00:00 (119/152): libgcc-13.2.1-6.fc39.aarch64.rpm 491 kB/s | 97 kB 00:00 (120/152): libidn2-2.3.7-1.fc39.aarch64.rpm 772 kB/s | 120 kB 00:00 (121/152): libmount-2.39.3-6.fc39.aarch64.rpm 1.3 MB/s | 154 kB 00:00 (122/152): libnghttp2-1.55.1-4.fc39.aarch64.rpm 510 kB/s | 76 kB 00:00 (123/152): libsmartcols-2.39.3-6.fc39.aarch64.r 471 kB/s | 66 kB 00:00 (124/152): libssh-0.10.6-2.fc39.aarch64.rpm 1.8 MB/s | 213 kB 00:00 (125/152): libssh-config-0.10.6-2.fc39.noarch.r 75 kB/s | 9.0 kB 00:00 (126/152): libstdc++-13.2.1-6.fc39.aarch64.rpm 4.4 MB/s | 815 kB 00:00 (127/152): libtirpc-1.3.4-0.rc2.fc39.aarch64.rp 783 kB/s | 95 kB 00:00 (128/152): libuuid-2.39.3-6.fc39.aarch64.rpm 236 kB/s | 28 kB 00:00 (129/152): ncurses-base-6.4-7.20230520.fc39.1.n 773 kB/s | 88 kB 00:00 (130/152): lua-srpm-macros-1-13.fc39.noarch.rpm 73 kB/s | 8.7 kB 00:00 (131/152): ncurses-libs-6.4-7.20230520.fc39.1.a 2.6 MB/s | 326 kB 00:00 (132/152): p11-kit-0.25.3-1.fc39.aarch64.rpm 2.9 MB/s | 495 kB 00:00 (133/152): p11-kit-trust-0.25.3-1.fc39.aarch64. 650 kB/s | 141 kB 00:00 (134/152): pam-1.5.3-3.fc39.aarch64.rpm 2.6 MB/s | 552 kB 00:00 (135/152): pam-libs-1.5.3-3.fc39.aarch64.rpm 457 kB/s | 57 kB 00:00 (136/152): publicsuffix-list-dafsa-20240107-1.f 481 kB/s | 58 kB 00:00 (137/152): pyproject-srpm-macros-1.12.0-1.fc39. 104 kB/s | 14 kB 00:00 (138/152): qt5-srpm-macros-5.15.12-1.fc39.noarc 64 kB/s | 8.4 kB 00:00 (139/152): qt6-srpm-macros-6.6.2-1.fc39.noarch. 74 kB/s | 8.9 kB 00:00 (140/152): readline-8.2-6.fc39.aarch64.rpm 1.7 MB/s | 212 kB 00:00 (141/152): redhat-rpm-config-265-1.fc39.noarch. 684 kB/s | 78 kB 00:00 (142/152): rpm-4.19.1.1-1.fc39.aarch64.rpm 4.0 MB/s | 536 kB 00:00 (143/152): rpm-build-4.19.1.1-1.fc39.aarch64.rp 663 kB/s | 79 kB 00:00 (144/152): rpm-build-libs-4.19.1.1-1.fc39.aarch 799 kB/s | 91 kB 00:00 (145/152): rpm-libs-4.19.1.1-1.fc39.aarch64.rpm 2.4 MB/s | 305 kB 00:00 (146/152): rpm-sequoia-1.6.0-1.fc39.aarch64.rpm 5.4 MB/s | 817 kB 00:00 (147/152): rpmautospec-rpm-macros-0.6.3-1.fc39. 73 kB/s | 10 kB 00:00 (148/152): rust-srpm-macros-26.1-1.fc39.noarch. 105 kB/s | 13 kB 00:00 (149/152): systemd-libs-254.9-1.fc39.aarch64.rp 5.4 MB/s | 665 kB 00:00 (150/152): shadow-utils-4.14.0-2.fc39.aarch64.r 6.9 MB/s | 1.3 MB 00:00 (151/152): util-linux-core-2.39.3-6.fc39.aarch6 4.1 MB/s | 506 kB 00:00 (152/152): util-linux-2.39.3-6.fc39.aarch64.rpm 949 kB/s | 1.2 MB 00:01 -------------------------------------------------------------------------------- Total 6.7 MB/s | 52 MB 00:07 fedora 1.6 MB/s | 1.6 kB 00:00 Importing GPG key 0x18B8E74C: Userid : "Fedora (39) " Fingerprint: E8F2 3996 F232 1864 0CB4 4CBE 75CF 5AC4 18B8 E74C From : /usr/share/distribution-gpg-keys/fedora/RPM-GPG-KEY-fedora-39-primary Key imported successfully Running transaction check Transaction check succeeded. Running transaction test Transaction test succeeded. Running transaction Running scriptlet: filesystem-3.18-6.fc39.aarch64 1/1 Preparing : 1/1 Installing : libgcc-13.2.1-6.fc39.aarch64 1/152 Running scriptlet: libgcc-13.2.1-6.fc39.aarch64 1/152 Installing : crypto-policies-20231204-1.git1e3a2e4.fc39.noarc 2/152 Running scriptlet: crypto-policies-20231204-1.git1e3a2e4.fc39.noarc 2/152 Installing : fedora-release-identity-basic-39-36.noarch 3/152 Installing : fedora-gpg-keys-39-1.noarch 4/152 Installing : fedora-repos-39-1.noarch 5/152 Installing : fedora-release-common-39-36.noarch 6/152 Installing : fedora-release-39-36.noarch 7/152 Installing : setup-2.14.4-1.fc39.noarch 8/152 Running scriptlet: setup-2.14.4-1.fc39.noarch 8/152 Installing : filesystem-3.18-6.fc39.aarch64 9/152 Installing : basesystem-11-18.fc39.noarch 10/152 Installing : rust-srpm-macros-26.1-1.fc39.noarch 11/152 Installing : qt6-srpm-macros-6.6.2-1.fc39.noarch 12/152 Installing : qt5-srpm-macros-5.15.12-1.fc39.noarch 13/152 Installing : publicsuffix-list-dafsa-20240107-1.fc39.noarch 14/152 Installing : ncurses-base-6.4-7.20230520.fc39.1.noarch 15/152 Installing : glibc-gconv-extra-2.38-99.fc39.aarch64 16/152 Running scriptlet: glibc-gconv-extra-2.38-99.fc39.aarch64 16/152 Installing : glibc-minimal-langpack-2.38-99.fc39.aarch64 17/152 Installing : glibc-common-2.38-99.fc39.aarch64 18/152 Running scriptlet: glibc-2.38-99.fc39.aarch64 19/152 Installing : glibc-2.38-99.fc39.aarch64 19/152 Running scriptlet: glibc-2.38-99.fc39.aarch64 19/152 Installing : ncurses-libs-6.4-7.20230520.fc39.1.aarch64 20/152 Installing : bash-5.2.26-1.fc39.aarch64 21/152 Running scriptlet: bash-5.2.26-1.fc39.aarch64 21/152 Installing : zlib-1.2.13-4.fc39.aarch64 22/152 Installing : xz-libs-5.4.4-1.fc39.aarch64 23/152 Installing : bzip2-libs-1.0.8-16.fc39.aarch64 24/152 Installing : libzstd-1.5.5-4.fc39.aarch64 25/152 Installing : elfutils-libelf-0.190-4.fc39.aarch64 26/152 Installing : popt-1.19-3.fc39.aarch64 27/152 Installing : libstdc++-13.2.1-6.fc39.aarch64 28/152 Installing : libuuid-2.39.3-6.fc39.aarch64 29/152 Installing : libblkid-2.39.3-6.fc39.aarch64 30/152 Installing : readline-8.2-6.fc39.aarch64 31/152 Installing : gmp-1:6.2.1-5.fc39.aarch64 32/152 Installing : libattr-2.5.1-8.fc39.aarch64 33/152 Installing : libacl-2.3.1-9.fc39.aarch64 34/152 Installing : libxcrypt-4.4.36-2.fc39.aarch64 35/152 Installing : libcap-2.48-9.fc39.aarch64 36/152 Installing : libeconf-0.5.2-1.fc39.aarch64 37/152 Installing : lz4-libs-1.9.4-4.fc39.aarch64 38/152 Installing : systemd-libs-254.9-1.fc39.aarch64 39/152 Installing : mpfr-4.2.0-3.fc39.aarch64 40/152 Installing : dwz-0.15-3.fc39.aarch64 41/152 Installing : unzip-6.0-62.fc39.aarch64 42/152 Installing : file-libs-5.44-5.fc39.aarch64 43/152 Installing : file-5.44-5.fc39.aarch64 44/152 Installing : jansson-2.13.1-7.fc39.aarch64 45/152 Installing : libcap-ng-0.8.3-8.fc39.aarch64 46/152 Installing : audit-libs-3.1.2-8.fc39.aarch64 47/152 Installing : pam-libs-1.5.3-3.fc39.aarch64 48/152 Installing : libcom_err-1.47.0-2.fc39.aarch64 49/152 Installing : libsepol-3.5-2.fc39.aarch64 50/152 Installing : libtasn1-4.19.0-3.fc39.aarch64 51/152 Installing : libunistring-1.1-5.fc39.aarch64 52/152 Installing : libidn2-2.3.7-1.fc39.aarch64 53/152 Installing : lua-libs-5.4.6-3.fc39.aarch64 54/152 Installing : alternatives-1.26-1.fc39.aarch64 55/152 Installing : libsmartcols-2.39.3-6.fc39.aarch64 56/152 Installing : libpsl-0.21.2-4.fc39.aarch64 57/152 Installing : zip-3.0-39.fc39.aarch64 58/152 Installing : zstd-1.5.5-4.fc39.aarch64 59/152 Installing : libfdisk-2.39.3-6.fc39.aarch64 60/152 Installing : bzip2-1.0.8-16.fc39.aarch64 61/152 Installing : libxml2-2.10.4-3.fc39.aarch64 62/152 Installing : sqlite-libs-3.42.0-7.fc39.aarch64 63/152 Installing : ed-1.19-4.fc39.aarch64 64/152 Installing : elfutils-default-yama-scope-0.190-4.fc39.noarch 65/152 Running scriptlet: elfutils-default-yama-scope-0.190-4.fc39.noarch 65/152 Installing : cpio-2.14-4.fc39.aarch64 66/152 Installing : diffutils-3.10-3.fc39.aarch64 67/152 Installing : gdbm-libs-1:1.23-4.fc39.aarch64 68/152 Installing : cyrus-sasl-lib-2.1.28-11.fc39.aarch64 69/152 Installing : keyutils-libs-1.6.1-7.fc39.aarch64 70/152 Installing : libbrotli-1.1.0-1.fc39.aarch64 71/152 Installing : libdb-5.3.28-56.fc39.aarch64 72/152 Installing : libffi-3.4.4-4.fc39.aarch64 73/152 Installing : p11-kit-0.25.3-1.fc39.aarch64 74/152 Installing : p11-kit-trust-0.25.3-1.fc39.aarch64 75/152 Running scriptlet: p11-kit-trust-0.25.3-1.fc39.aarch64 75/152 Installing : libpkgconf-1.9.5-2.fc39.aarch64 76/152 Installing : pkgconf-1.9.5-2.fc39.aarch64 77/152 Installing : libsigsegv-2.14-5.fc39.aarch64 78/152 Installing : gawk-5.2.2-2.fc39.aarch64 79/152 Installing : libverto-0.3.2-6.fc39.aarch64 80/152 Installing : xxhash-libs-0.8.2-1.fc39.aarch64 81/152 Installing : libgomp-13.2.1-6.fc39.aarch64 82/152 Installing : libnghttp2-1.55.1-4.fc39.aarch64 83/152 Installing : libssh-config-0.10.6-2.fc39.noarch 84/152 Installing : coreutils-common-9.3-5.fc39.aarch64 85/152 Installing : ansible-srpm-macros-1-12.fc39.noarch 86/152 Installing : pkgconf-m4-1.9.5-2.fc39.noarch 87/152 Installing : pkgconf-pkg-config-1.9.5-2.fc39.aarch64 88/152 Installing : perl-srpm-macros-1-51.fc39.noarch 89/152 Installing : pcre2-syntax-10.42-1.fc39.2.noarch 90/152 Installing : pcre2-10.42-1.fc39.2.aarch64 91/152 Installing : libselinux-3.5-5.fc39.aarch64 92/152 Installing : sed-4.8-14.fc39.aarch64 93/152 Installing : grep-3.11-3.fc39.aarch64 94/152 Installing : findutils-1:4.9.0-5.fc39.aarch64 95/152 Installing : xz-5.4.4-1.fc39.aarch64 96/152 Installing : libmount-2.39.3-6.fc39.aarch64 97/152 Installing : util-linux-core-2.39.3-6.fc39.aarch64 98/152 Installing : openssl-libs-1:3.1.1-4.fc39.aarch64 99/152 Installing : coreutils-9.3-5.fc39.aarch64 100/152 Running scriptlet: ca-certificates-2023.2.60_v7.0.306-2.fc39.noarch 101/152 Installing : ca-certificates-2023.2.60_v7.0.306-2.fc39.noarch 101/152 Running scriptlet: ca-certificates-2023.2.60_v7.0.306-2.fc39.noarch 101/152 Installing : krb5-libs-1.21.2-3.fc39.aarch64 102/152 Installing : libtirpc-1.3.4-0.rc2.fc39.aarch64 103/152 Running scriptlet: authselect-libs-1.4.3-1.fc39.aarch64 104/152 Installing : authselect-libs-1.4.3-1.fc39.aarch64 104/152 Installing : gzip-1.12-6.fc39.aarch64 105/152 Installing : cracklib-2.9.11-2.fc39.aarch64 106/152 Installing : libpwquality-1.4.5-6.fc39.aarch64 107/152 Installing : authselect-1.4.3-1.fc39.aarch64 108/152 Installing : libnsl2-2.0.0-6.fc39.aarch64 109/152 Installing : pam-1.5.3-3.fc39.aarch64 110/152 Installing : libssh-0.10.6-2.fc39.aarch64 111/152 Installing : libarchive-3.7.1-1.fc39.aarch64 112/152 Installing : libevent-2.1.12-9.fc39.aarch64 113/152 Installing : openldap-2.6.6-1.fc39.aarch64 114/152 Installing : libcurl-8.2.1-4.fc39.aarch64 115/152 Installing : elfutils-libs-0.190-4.fc39.aarch64 116/152 Installing : elfutils-debuginfod-client-0.190-4.fc39.aarch64 117/152 Installing : binutils-gold-2.40-14.fc39.aarch64 118/152 Running scriptlet: binutils-gold-2.40-14.fc39.aarch64 118/152 Installing : binutils-2.40-14.fc39.aarch64 119/152 Running scriptlet: binutils-2.40-14.fc39.aarch64 119/152 Installing : elfutils-0.190-4.fc39.aarch64 120/152 Installing : gdb-minimal-14.1-4.fc39.aarch64 121/152 Installing : debugedit-5.0-12.fc39.aarch64 122/152 Installing : curl-8.2.1-4.fc39.aarch64 123/152 Installing : rpm-sequoia-1.6.0-1.fc39.aarch64 124/152 Installing : rpm-libs-4.19.1.1-1.fc39.aarch64 125/152 Running scriptlet: rpm-4.19.1.1-1.fc39.aarch64 126/152 Installing : rpm-4.19.1.1-1.fc39.aarch64 126/152 Installing : efi-srpm-macros-5-9.fc39.noarch 127/152 Installing : lua-srpm-macros-1-13.fc39.noarch 128/152 Installing : rpmautospec-rpm-macros-0.6.3-1.fc39.noarch 129/152 Installing : rpm-build-libs-4.19.1.1-1.fc39.aarch64 130/152 Installing : libsemanage-3.5-4.fc39.aarch64 131/152 Installing : shadow-utils-2:4.14.0-2.fc39.aarch64 132/152 Running scriptlet: libutempter-1.2.1-10.fc39.aarch64 133/152 Installing : libutempter-1.2.1-10.fc39.aarch64 133/152 Installing : patch-2.7.6-22.fc39.aarch64 134/152 Installing : tar-2:1.35-2.fc39.aarch64 135/152 Installing : package-notes-srpm-macros-0.5-9.fc39.noarch 136/152 Installing : openblas-srpm-macros-2-14.fc39.noarch 137/152 Installing : ocaml-srpm-macros-8-2.fc39.noarch 138/152 Installing : kernel-srpm-macros-1.0-20.fc39.noarch 139/152 Installing : gnat-srpm-macros-6-3.fc39.noarch 140/152 Installing : ghc-srpm-macros-1.6.1-2.fc39.noarch 141/152 Installing : fpc-srpm-macros-1.3-8.fc39.noarch 142/152 Installing : fonts-srpm-macros-1:2.0.5-12.fc39.noarch 143/152 Installing : python-srpm-macros-3.12-4.fc39.noarch 144/152 Installing : forge-srpm-macros-0.2.0-3.fc39.noarch 145/152 Installing : go-srpm-macros-3.4.0-2.fc39.noarch 146/152 Installing : redhat-rpm-config-265-1.fc39.noarch 147/152 Installing : rpm-build-4.19.1.1-1.fc39.aarch64 148/152 Installing : pyproject-srpm-macros-1.12.0-1.fc39.noarch 149/152 Installing : util-linux-2.39.3-6.fc39.aarch64 150/152 Running scriptlet: util-linux-2.39.3-6.fc39.aarch64 150/152 Installing : which-2.21-40.fc39.aarch64 151/152 Installing : info-7.0.3-3.fc39.aarch64 152/152 Running scriptlet: filesystem-3.18-6.fc39.aarch64 152/152 Running scriptlet: ca-certificates-2023.2.60_v7.0.306-2.fc39.noarch 152/152 Running scriptlet: authselect-libs-1.4.3-1.fc39.aarch64 152/152 Running scriptlet: rpm-4.19.1.1-1.fc39.aarch64 152/152 Running scriptlet: info-7.0.3-3.fc39.aarch64 152/152 Verifying : glibc-2.38-99.fc39.aarch64 1/152 Verifying : glibc-common-2.38-99.fc39.aarch64 2/152 Verifying : glibc-gconv-extra-2.38-99.fc39.aarch64 3/152 Verifying : glibc-minimal-langpack-2.38-99.fc39.aarch64 4/152 Verifying : authselect-1.4.3-1.fc39.aarch64 5/152 Verifying : authselect-libs-1.4.3-1.fc39.aarch64 6/152 Verifying : basesystem-11-18.fc39.noarch 7/152 Verifying : bzip2-1.0.8-16.fc39.aarch64 8/152 Verifying : bzip2-libs-1.0.8-16.fc39.aarch64 9/152 Verifying : ca-certificates-2023.2.60_v7.0.306-2.fc39.noarch 10/152 Verifying : cpio-2.14-4.fc39.aarch64 11/152 Verifying : cracklib-2.9.11-2.fc39.aarch64 12/152 Verifying : cyrus-sasl-lib-2.1.28-11.fc39.aarch64 13/152 Verifying : diffutils-3.10-3.fc39.aarch64 14/152 Verifying : dwz-0.15-3.fc39.aarch64 15/152 Verifying : ed-1.19-4.fc39.aarch64 16/152 Verifying : efi-srpm-macros-5-9.fc39.noarch 17/152 Verifying : fedora-gpg-keys-39-1.noarch 18/152 Verifying : fedora-repos-39-1.noarch 19/152 Verifying : file-5.44-5.fc39.aarch64 20/152 Verifying : file-libs-5.44-5.fc39.aarch64 21/152 Verifying : filesystem-3.18-6.fc39.aarch64 22/152 Verifying : findutils-1:4.9.0-5.fc39.aarch64 23/152 Verifying : fonts-srpm-macros-1:2.0.5-12.fc39.noarch 24/152 Verifying : fpc-srpm-macros-1.3-8.fc39.noarch 25/152 Verifying : gawk-5.2.2-2.fc39.aarch64 26/152 Verifying : gdbm-libs-1:1.23-4.fc39.aarch64 27/152 Verifying : ghc-srpm-macros-1.6.1-2.fc39.noarch 28/152 Verifying : gmp-1:6.2.1-5.fc39.aarch64 29/152 Verifying : gnat-srpm-macros-6-3.fc39.noarch 30/152 Verifying : grep-3.11-3.fc39.aarch64 31/152 Verifying : gzip-1.12-6.fc39.aarch64 32/152 Verifying : info-7.0.3-3.fc39.aarch64 33/152 Verifying : jansson-2.13.1-7.fc39.aarch64 34/152 Verifying : kernel-srpm-macros-1.0-20.fc39.noarch 35/152 Verifying : keyutils-libs-1.6.1-7.fc39.aarch64 36/152 Verifying : libarchive-3.7.1-1.fc39.aarch64 37/152 Verifying : libattr-2.5.1-8.fc39.aarch64 38/152 Verifying : libbrotli-1.1.0-1.fc39.aarch64 39/152 Verifying : libcap-ng-0.8.3-8.fc39.aarch64 40/152 Verifying : libcom_err-1.47.0-2.fc39.aarch64 41/152 Verifying : libdb-5.3.28-56.fc39.aarch64 42/152 Verifying : libeconf-0.5.2-1.fc39.aarch64 43/152 Verifying : libevent-2.1.12-9.fc39.aarch64 44/152 Verifying : libffi-3.4.4-4.fc39.aarch64 45/152 Verifying : libnsl2-2.0.0-6.fc39.aarch64 46/152 Verifying : libpkgconf-1.9.5-2.fc39.aarch64 47/152 Verifying : libpsl-0.21.2-4.fc39.aarch64 48/152 Verifying : libpwquality-1.4.5-6.fc39.aarch64 49/152 Verifying : libselinux-3.5-5.fc39.aarch64 50/152 Verifying : libsemanage-3.5-4.fc39.aarch64 51/152 Verifying : libsepol-3.5-2.fc39.aarch64 52/152 Verifying : libsigsegv-2.14-5.fc39.aarch64 53/152 Verifying : libtasn1-4.19.0-3.fc39.aarch64 54/152 Verifying : libunistring-1.1-5.fc39.aarch64 55/152 Verifying : libutempter-1.2.1-10.fc39.aarch64 56/152 Verifying : libverto-0.3.2-6.fc39.aarch64 57/152 Verifying : libxcrypt-4.4.36-2.fc39.aarch64 58/152 Verifying : libxml2-2.10.4-3.fc39.aarch64 59/152 Verifying : libzstd-1.5.5-4.fc39.aarch64 60/152 Verifying : lua-libs-5.4.6-3.fc39.aarch64 61/152 Verifying : lz4-libs-1.9.4-4.fc39.aarch64 62/152 Verifying : mpfr-4.2.0-3.fc39.aarch64 63/152 Verifying : ocaml-srpm-macros-8-2.fc39.noarch 64/152 Verifying : openblas-srpm-macros-2-14.fc39.noarch 65/152 Verifying : openldap-2.6.6-1.fc39.aarch64 66/152 Verifying : openssl-libs-1:3.1.1-4.fc39.aarch64 67/152 Verifying : package-notes-srpm-macros-0.5-9.fc39.noarch 68/152 Verifying : patch-2.7.6-22.fc39.aarch64 69/152 Verifying : pcre2-10.42-1.fc39.2.aarch64 70/152 Verifying : pcre2-syntax-10.42-1.fc39.2.noarch 71/152 Verifying : perl-srpm-macros-1-51.fc39.noarch 72/152 Verifying : pkgconf-1.9.5-2.fc39.aarch64 73/152 Verifying : pkgconf-m4-1.9.5-2.fc39.noarch 74/152 Verifying : pkgconf-pkg-config-1.9.5-2.fc39.aarch64 75/152 Verifying : popt-1.19-3.fc39.aarch64 76/152 Verifying : python-srpm-macros-3.12-4.fc39.noarch 77/152 Verifying : sed-4.8-14.fc39.aarch64 78/152 Verifying : setup-2.14.4-1.fc39.noarch 79/152 Verifying : sqlite-libs-3.42.0-7.fc39.aarch64 80/152 Verifying : tar-2:1.35-2.fc39.aarch64 81/152 Verifying : unzip-6.0-62.fc39.aarch64 82/152 Verifying : which-2.21-40.fc39.aarch64 83/152 Verifying : xxhash-libs-0.8.2-1.fc39.aarch64 84/152 Verifying : xz-5.4.4-1.fc39.aarch64 85/152 Verifying : xz-libs-5.4.4-1.fc39.aarch64 86/152 Verifying : zip-3.0-39.fc39.aarch64 87/152 Verifying : zlib-1.2.13-4.fc39.aarch64 88/152 Verifying : zstd-1.5.5-4.fc39.aarch64 89/152 Verifying : alternatives-1.26-1.fc39.aarch64 90/152 Verifying : ansible-srpm-macros-1-12.fc39.noarch 91/152 Verifying : audit-libs-3.1.2-8.fc39.aarch64 92/152 Verifying : bash-5.2.26-1.fc39.aarch64 93/152 Verifying : binutils-2.40-14.fc39.aarch64 94/152 Verifying : binutils-gold-2.40-14.fc39.aarch64 95/152 Verifying : coreutils-9.3-5.fc39.aarch64 96/152 Verifying : coreutils-common-9.3-5.fc39.aarch64 97/152 Verifying : crypto-policies-20231204-1.git1e3a2e4.fc39.noarc 98/152 Verifying : curl-8.2.1-4.fc39.aarch64 99/152 Verifying : debugedit-5.0-12.fc39.aarch64 100/152 Verifying : elfutils-0.190-4.fc39.aarch64 101/152 Verifying : elfutils-debuginfod-client-0.190-4.fc39.aarch64 102/152 Verifying : elfutils-default-yama-scope-0.190-4.fc39.noarch 103/152 Verifying : elfutils-libelf-0.190-4.fc39.aarch64 104/152 Verifying : elfutils-libs-0.190-4.fc39.aarch64 105/152 Verifying : fedora-release-39-36.noarch 106/152 Verifying : fedora-release-common-39-36.noarch 107/152 Verifying : fedora-release-identity-basic-39-36.noarch 108/152 Verifying : forge-srpm-macros-0.2.0-3.fc39.noarch 109/152 Verifying : gdb-minimal-14.1-4.fc39.aarch64 110/152 Verifying : go-srpm-macros-3.4.0-2.fc39.noarch 111/152 Verifying : krb5-libs-1.21.2-3.fc39.aarch64 112/152 Verifying : libacl-2.3.1-9.fc39.aarch64 113/152 Verifying : libblkid-2.39.3-6.fc39.aarch64 114/152 Verifying : libcap-2.48-9.fc39.aarch64 115/152 Verifying : libcurl-8.2.1-4.fc39.aarch64 116/152 Verifying : libfdisk-2.39.3-6.fc39.aarch64 117/152 Verifying : libgcc-13.2.1-6.fc39.aarch64 118/152 Verifying : libgomp-13.2.1-6.fc39.aarch64 119/152 Verifying : libidn2-2.3.7-1.fc39.aarch64 120/152 Verifying : libmount-2.39.3-6.fc39.aarch64 121/152 Verifying : libnghttp2-1.55.1-4.fc39.aarch64 122/152 Verifying : libsmartcols-2.39.3-6.fc39.aarch64 123/152 Verifying : libssh-0.10.6-2.fc39.aarch64 124/152 Verifying : libssh-config-0.10.6-2.fc39.noarch 125/152 Verifying : libstdc++-13.2.1-6.fc39.aarch64 126/152 Verifying : libtirpc-1.3.4-0.rc2.fc39.aarch64 127/152 Verifying : libuuid-2.39.3-6.fc39.aarch64 128/152 Verifying : lua-srpm-macros-1-13.fc39.noarch 129/152 Verifying : ncurses-base-6.4-7.20230520.fc39.1.noarch 130/152 Verifying : ncurses-libs-6.4-7.20230520.fc39.1.aarch64 131/152 Verifying : p11-kit-0.25.3-1.fc39.aarch64 132/152 Verifying : p11-kit-trust-0.25.3-1.fc39.aarch64 133/152 Verifying : pam-1.5.3-3.fc39.aarch64 134/152 Verifying : pam-libs-1.5.3-3.fc39.aarch64 135/152 Verifying : publicsuffix-list-dafsa-20240107-1.fc39.noarch 136/152 Verifying : pyproject-srpm-macros-1.12.0-1.fc39.noarch 137/152 Verifying : qt5-srpm-macros-5.15.12-1.fc39.noarch 138/152 Verifying : qt6-srpm-macros-6.6.2-1.fc39.noarch 139/152 Verifying : readline-8.2-6.fc39.aarch64 140/152 Verifying : redhat-rpm-config-265-1.fc39.noarch 141/152 Verifying : rpm-4.19.1.1-1.fc39.aarch64 142/152 Verifying : rpm-build-4.19.1.1-1.fc39.aarch64 143/152 Verifying : rpm-build-libs-4.19.1.1-1.fc39.aarch64 144/152 Verifying : rpm-libs-4.19.1.1-1.fc39.aarch64 145/152 Verifying : rpm-sequoia-1.6.0-1.fc39.aarch64 146/152 Verifying : rpmautospec-rpm-macros-0.6.3-1.fc39.noarch 147/152 Verifying : rust-srpm-macros-26.1-1.fc39.noarch 148/152 Verifying : shadow-utils-2:4.14.0-2.fc39.aarch64 149/152 Verifying : systemd-libs-254.9-1.fc39.aarch64 150/152 Verifying : util-linux-2.39.3-6.fc39.aarch64 151/152 Verifying : util-linux-core-2.39.3-6.fc39.aarch64 152/152 Installed: alternatives-1.26-1.fc39.aarch64 ansible-srpm-macros-1-12.fc39.noarch audit-libs-3.1.2-8.fc39.aarch64 authselect-1.4.3-1.fc39.aarch64 authselect-libs-1.4.3-1.fc39.aarch64 basesystem-11-18.fc39.noarch bash-5.2.26-1.fc39.aarch64 binutils-2.40-14.fc39.aarch64 binutils-gold-2.40-14.fc39.aarch64 bzip2-1.0.8-16.fc39.aarch64 bzip2-libs-1.0.8-16.fc39.aarch64 ca-certificates-2023.2.60_v7.0.306-2.fc39.noarch coreutils-9.3-5.fc39.aarch64 coreutils-common-9.3-5.fc39.aarch64 cpio-2.14-4.fc39.aarch64 cracklib-2.9.11-2.fc39.aarch64 crypto-policies-20231204-1.git1e3a2e4.fc39.noarch curl-8.2.1-4.fc39.aarch64 cyrus-sasl-lib-2.1.28-11.fc39.aarch64 debugedit-5.0-12.fc39.aarch64 diffutils-3.10-3.fc39.aarch64 dwz-0.15-3.fc39.aarch64 ed-1.19-4.fc39.aarch64 efi-srpm-macros-5-9.fc39.noarch elfutils-0.190-4.fc39.aarch64 elfutils-debuginfod-client-0.190-4.fc39.aarch64 elfutils-default-yama-scope-0.190-4.fc39.noarch elfutils-libelf-0.190-4.fc39.aarch64 elfutils-libs-0.190-4.fc39.aarch64 fedora-gpg-keys-39-1.noarch fedora-release-39-36.noarch fedora-release-common-39-36.noarch fedora-release-identity-basic-39-36.noarch fedora-repos-39-1.noarch file-5.44-5.fc39.aarch64 file-libs-5.44-5.fc39.aarch64 filesystem-3.18-6.fc39.aarch64 findutils-1:4.9.0-5.fc39.aarch64 fonts-srpm-macros-1:2.0.5-12.fc39.noarch forge-srpm-macros-0.2.0-3.fc39.noarch fpc-srpm-macros-1.3-8.fc39.noarch gawk-5.2.2-2.fc39.aarch64 gdb-minimal-14.1-4.fc39.aarch64 gdbm-libs-1:1.23-4.fc39.aarch64 ghc-srpm-macros-1.6.1-2.fc39.noarch glibc-2.38-99.fc39.aarch64 glibc-common-2.38-99.fc39.aarch64 glibc-gconv-extra-2.38-99.fc39.aarch64 glibc-minimal-langpack-2.38-99.fc39.aarch64 gmp-1:6.2.1-5.fc39.aarch64 gnat-srpm-macros-6-3.fc39.noarch go-srpm-macros-3.4.0-2.fc39.noarch grep-3.11-3.fc39.aarch64 gzip-1.12-6.fc39.aarch64 info-7.0.3-3.fc39.aarch64 jansson-2.13.1-7.fc39.aarch64 kernel-srpm-macros-1.0-20.fc39.noarch keyutils-libs-1.6.1-7.fc39.aarch64 krb5-libs-1.21.2-3.fc39.aarch64 libacl-2.3.1-9.fc39.aarch64 libarchive-3.7.1-1.fc39.aarch64 libattr-2.5.1-8.fc39.aarch64 libblkid-2.39.3-6.fc39.aarch64 libbrotli-1.1.0-1.fc39.aarch64 libcap-2.48-9.fc39.aarch64 libcap-ng-0.8.3-8.fc39.aarch64 libcom_err-1.47.0-2.fc39.aarch64 libcurl-8.2.1-4.fc39.aarch64 libdb-5.3.28-56.fc39.aarch64 libeconf-0.5.2-1.fc39.aarch64 libevent-2.1.12-9.fc39.aarch64 libfdisk-2.39.3-6.fc39.aarch64 libffi-3.4.4-4.fc39.aarch64 libgcc-13.2.1-6.fc39.aarch64 libgomp-13.2.1-6.fc39.aarch64 libidn2-2.3.7-1.fc39.aarch64 libmount-2.39.3-6.fc39.aarch64 libnghttp2-1.55.1-4.fc39.aarch64 libnsl2-2.0.0-6.fc39.aarch64 libpkgconf-1.9.5-2.fc39.aarch64 libpsl-0.21.2-4.fc39.aarch64 libpwquality-1.4.5-6.fc39.aarch64 libselinux-3.5-5.fc39.aarch64 libsemanage-3.5-4.fc39.aarch64 libsepol-3.5-2.fc39.aarch64 libsigsegv-2.14-5.fc39.aarch64 libsmartcols-2.39.3-6.fc39.aarch64 libssh-0.10.6-2.fc39.aarch64 libssh-config-0.10.6-2.fc39.noarch libstdc++-13.2.1-6.fc39.aarch64 libtasn1-4.19.0-3.fc39.aarch64 libtirpc-1.3.4-0.rc2.fc39.aarch64 libunistring-1.1-5.fc39.aarch64 libutempter-1.2.1-10.fc39.aarch64 libuuid-2.39.3-6.fc39.aarch64 libverto-0.3.2-6.fc39.aarch64 libxcrypt-4.4.36-2.fc39.aarch64 libxml2-2.10.4-3.fc39.aarch64 libzstd-1.5.5-4.fc39.aarch64 lua-libs-5.4.6-3.fc39.aarch64 lua-srpm-macros-1-13.fc39.noarch lz4-libs-1.9.4-4.fc39.aarch64 mpfr-4.2.0-3.fc39.aarch64 ncurses-base-6.4-7.20230520.fc39.1.noarch ncurses-libs-6.4-7.20230520.fc39.1.aarch64 ocaml-srpm-macros-8-2.fc39.noarch openblas-srpm-macros-2-14.fc39.noarch openldap-2.6.6-1.fc39.aarch64 openssl-libs-1:3.1.1-4.fc39.aarch64 p11-kit-0.25.3-1.fc39.aarch64 p11-kit-trust-0.25.3-1.fc39.aarch64 package-notes-srpm-macros-0.5-9.fc39.noarch pam-1.5.3-3.fc39.aarch64 pam-libs-1.5.3-3.fc39.aarch64 patch-2.7.6-22.fc39.aarch64 pcre2-10.42-1.fc39.2.aarch64 pcre2-syntax-10.42-1.fc39.2.noarch perl-srpm-macros-1-51.fc39.noarch pkgconf-1.9.5-2.fc39.aarch64 pkgconf-m4-1.9.5-2.fc39.noarch pkgconf-pkg-config-1.9.5-2.fc39.aarch64 popt-1.19-3.fc39.aarch64 publicsuffix-list-dafsa-20240107-1.fc39.noarch pyproject-srpm-macros-1.12.0-1.fc39.noarch python-srpm-macros-3.12-4.fc39.noarch qt5-srpm-macros-5.15.12-1.fc39.noarch qt6-srpm-macros-6.6.2-1.fc39.noarch readline-8.2-6.fc39.aarch64 redhat-rpm-config-265-1.fc39.noarch rpm-4.19.1.1-1.fc39.aarch64 rpm-build-4.19.1.1-1.fc39.aarch64 rpm-build-libs-4.19.1.1-1.fc39.aarch64 rpm-libs-4.19.1.1-1.fc39.aarch64 rpm-sequoia-1.6.0-1.fc39.aarch64 rpmautospec-rpm-macros-0.6.3-1.fc39.noarch rust-srpm-macros-26.1-1.fc39.noarch sed-4.8-14.fc39.aarch64 setup-2.14.4-1.fc39.noarch shadow-utils-2:4.14.0-2.fc39.aarch64 sqlite-libs-3.42.0-7.fc39.aarch64 systemd-libs-254.9-1.fc39.aarch64 tar-2:1.35-2.fc39.aarch64 unzip-6.0-62.fc39.aarch64 util-linux-2.39.3-6.fc39.aarch64 util-linux-core-2.39.3-6.fc39.aarch64 which-2.21-40.fc39.aarch64 xxhash-libs-0.8.2-1.fc39.aarch64 xz-5.4.4-1.fc39.aarch64 xz-libs-5.4.4-1.fc39.aarch64 zip-3.0-39.fc39.aarch64 zlib-1.2.13-4.fc39.aarch64 zstd-1.5.5-4.fc39.aarch64 Complete! Finish: installing minimal buildroot with dnf Start: creating root cache Finish: creating root cache Finish: chroot init INFO: Installed packages: INFO: alternatives-1.26-1.fc39.aarch64 ansible-srpm-macros-1-12.fc39.noarch audit-libs-3.1.2-8.fc39.aarch64 authselect-1.4.3-1.fc39.aarch64 authselect-libs-1.4.3-1.fc39.aarch64 basesystem-11-18.fc39.noarch bash-5.2.26-1.fc39.aarch64 binutils-2.40-14.fc39.aarch64 binutils-gold-2.40-14.fc39.aarch64 bzip2-1.0.8-16.fc39.aarch64 bzip2-libs-1.0.8-16.fc39.aarch64 ca-certificates-2023.2.60_v7.0.306-2.fc39.noarch coreutils-9.3-5.fc39.aarch64 coreutils-common-9.3-5.fc39.aarch64 cpio-2.14-4.fc39.aarch64 cracklib-2.9.11-2.fc39.aarch64 crypto-policies-20231204-1.git1e3a2e4.fc39.noarch curl-8.2.1-4.fc39.aarch64 cyrus-sasl-lib-2.1.28-11.fc39.aarch64 debugedit-5.0-12.fc39.aarch64 diffutils-3.10-3.fc39.aarch64 dwz-0.15-3.fc39.aarch64 ed-1.19-4.fc39.aarch64 efi-srpm-macros-5-9.fc39.noarch elfutils-0.190-4.fc39.aarch64 elfutils-debuginfod-client-0.190-4.fc39.aarch64 elfutils-default-yama-scope-0.190-4.fc39.noarch elfutils-libelf-0.190-4.fc39.aarch64 elfutils-libs-0.190-4.fc39.aarch64 fedora-gpg-keys-39-1.noarch fedora-release-39-36.noarch fedora-release-common-39-36.noarch fedora-release-identity-basic-39-36.noarch fedora-repos-39-1.noarch file-5.44-5.fc39.aarch64 file-libs-5.44-5.fc39.aarch64 filesystem-3.18-6.fc39.aarch64 findutils-4.9.0-5.fc39.aarch64 fonts-srpm-macros-2.0.5-12.fc39.noarch forge-srpm-macros-0.2.0-3.fc39.noarch fpc-srpm-macros-1.3-8.fc39.noarch gawk-5.2.2-2.fc39.aarch64 gdb-minimal-14.1-4.fc39.aarch64 gdbm-libs-1.23-4.fc39.aarch64 ghc-srpm-macros-1.6.1-2.fc39.noarch glibc-2.38-99.fc39.aarch64 glibc-common-2.38-99.fc39.aarch64 glibc-gconv-extra-2.38-99.fc39.aarch64 glibc-minimal-langpack-2.38-99.fc39.aarch64 gmp-6.2.1-5.fc39.aarch64 gnat-srpm-macros-6-3.fc39.noarch go-srpm-macros-3.4.0-2.fc39.noarch gpg-pubkey-18b8e74c-62f2920f grep-3.11-3.fc39.aarch64 gzip-1.12-6.fc39.aarch64 info-7.0.3-3.fc39.aarch64 jansson-2.13.1-7.fc39.aarch64 kernel-srpm-macros-1.0-20.fc39.noarch keyutils-libs-1.6.1-7.fc39.aarch64 krb5-libs-1.21.2-3.fc39.aarch64 libacl-2.3.1-9.fc39.aarch64 libarchive-3.7.1-1.fc39.aarch64 libattr-2.5.1-8.fc39.aarch64 libblkid-2.39.3-6.fc39.aarch64 libbrotli-1.1.0-1.fc39.aarch64 libcap-2.48-9.fc39.aarch64 libcap-ng-0.8.3-8.fc39.aarch64 libcom_err-1.47.0-2.fc39.aarch64 libcurl-8.2.1-4.fc39.aarch64 libdb-5.3.28-56.fc39.aarch64 libeconf-0.5.2-1.fc39.aarch64 libevent-2.1.12-9.fc39.aarch64 libfdisk-2.39.3-6.fc39.aarch64 libffi-3.4.4-4.fc39.aarch64 libgcc-13.2.1-6.fc39.aarch64 libgomp-13.2.1-6.fc39.aarch64 libidn2-2.3.7-1.fc39.aarch64 libmount-2.39.3-6.fc39.aarch64 libnghttp2-1.55.1-4.fc39.aarch64 libnsl2-2.0.0-6.fc39.aarch64 libpkgconf-1.9.5-2.fc39.aarch64 libpsl-0.21.2-4.fc39.aarch64 libpwquality-1.4.5-6.fc39.aarch64 libselinux-3.5-5.fc39.aarch64 libsemanage-3.5-4.fc39.aarch64 libsepol-3.5-2.fc39.aarch64 libsigsegv-2.14-5.fc39.aarch64 libsmartcols-2.39.3-6.fc39.aarch64 libssh-0.10.6-2.fc39.aarch64 libssh-config-0.10.6-2.fc39.noarch libstdc++-13.2.1-6.fc39.aarch64 libtasn1-4.19.0-3.fc39.aarch64 libtirpc-1.3.4-0.rc2.fc39.aarch64 libunistring-1.1-5.fc39.aarch64 libutempter-1.2.1-10.fc39.aarch64 libuuid-2.39.3-6.fc39.aarch64 libverto-0.3.2-6.fc39.aarch64 libxcrypt-4.4.36-2.fc39.aarch64 libxml2-2.10.4-3.fc39.aarch64 libzstd-1.5.5-4.fc39.aarch64 lua-libs-5.4.6-3.fc39.aarch64 lua-srpm-macros-1-13.fc39.noarch lz4-libs-1.9.4-4.fc39.aarch64 mpfr-4.2.0-3.fc39.aarch64 ncurses-base-6.4-7.20230520.fc39.1.noarch ncurses-libs-6.4-7.20230520.fc39.1.aarch64 ocaml-srpm-macros-8-2.fc39.noarch openblas-srpm-macros-2-14.fc39.noarch openldap-2.6.6-1.fc39.aarch64 openssl-libs-3.1.1-4.fc39.aarch64 p11-kit-0.25.3-1.fc39.aarch64 p11-kit-trust-0.25.3-1.fc39.aarch64 package-notes-srpm-macros-0.5-9.fc39.noarch pam-1.5.3-3.fc39.aarch64 pam-libs-1.5.3-3.fc39.aarch64 patch-2.7.6-22.fc39.aarch64 pcre2-10.42-1.fc39.2.aarch64 pcre2-syntax-10.42-1.fc39.2.noarch perl-srpm-macros-1-51.fc39.noarch pkgconf-1.9.5-2.fc39.aarch64 pkgconf-m4-1.9.5-2.fc39.noarch pkgconf-pkg-config-1.9.5-2.fc39.aarch64 popt-1.19-3.fc39.aarch64 publicsuffix-list-dafsa-20240107-1.fc39.noarch pyproject-srpm-macros-1.12.0-1.fc39.noarch python-srpm-macros-3.12-4.fc39.noarch qt5-srpm-macros-5.15.12-1.fc39.noarch qt6-srpm-macros-6.6.2-1.fc39.noarch readline-8.2-6.fc39.aarch64 redhat-rpm-config-265-1.fc39.noarch rpm-4.19.1.1-1.fc39.aarch64 rpm-build-4.19.1.1-1.fc39.aarch64 rpm-build-libs-4.19.1.1-1.fc39.aarch64 rpm-libs-4.19.1.1-1.fc39.aarch64 rpm-sequoia-1.6.0-1.fc39.aarch64 rpmautospec-rpm-macros-0.6.3-1.fc39.noarch rust-srpm-macros-26.1-1.fc39.noarch sed-4.8-14.fc39.aarch64 setup-2.14.4-1.fc39.noarch shadow-utils-4.14.0-2.fc39.aarch64 sqlite-libs-3.42.0-7.fc39.aarch64 systemd-libs-254.9-1.fc39.aarch64 tar-1.35-2.fc39.aarch64 unzip-6.0-62.fc39.aarch64 util-linux-2.39.3-6.fc39.aarch64 util-linux-core-2.39.3-6.fc39.aarch64 which-2.21-40.fc39.aarch64 xxhash-libs-0.8.2-1.fc39.aarch64 xz-5.4.4-1.fc39.aarch64 xz-libs-5.4.4-1.fc39.aarch64 zip-3.0-39.fc39.aarch64 zlib-1.2.13-4.fc39.aarch64 zstd-1.5.5-4.fc39.aarch64 Start: buildsrpm Start: rpmbuild -bs Building target platforms: aarch64 Building for target aarch64 setting SOURCE_DATE_EPOCH=1637193600 Wrote: /builddir/build/SRPMS/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.src.rpm Finish: rpmbuild -bs cp: preserving permissions for ‘/var/lib/copr-rpmbuild/results/chroot_scan/var/lib/mock/fedora-39-aarch64-1709342025.186079/root/var/log’: No such file or directory INFO: chroot_scan: 3 files copied to /var/lib/copr-rpmbuild/results/chroot_scan INFO: /var/lib/mock/fedora-39-aarch64-1709342025.186079/root/var/log/dnf.rpm.log /var/lib/mock/fedora-39-aarch64-1709342025.186079/root/var/log/dnf.librepo.log /var/lib/mock/fedora-39-aarch64-1709342025.186079/root/var/log/dnf.log Finish: buildsrpm INFO: Done(/var/lib/copr-rpmbuild/workspace/workdir-8rujp7yt/litex-pythondata-cpu-rocket/litex-pythondata-cpu-rocket.spec) Config(child) 4 minutes 22 seconds INFO: Results and/or logs in: /var/lib/copr-rpmbuild/results INFO: Cleaning up build root ('cleanup_on_success=True') Start: clean chroot INFO: unmounting tmpfs. Finish: clean chroot INFO: Start(/var/lib/copr-rpmbuild/results/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.src.rpm) Config(fedora-39-aarch64) Start(bootstrap): chroot init INFO: mounting tmpfs at /var/lib/mock/fedora-39-aarch64-bootstrap-1709342025.186079/root. INFO: reusing tmpfs at /var/lib/mock/fedora-39-aarch64-bootstrap-1709342025.186079/root. INFO: calling preinit hooks INFO: enabled root cache INFO: enabled package manager cache Start(bootstrap): cleaning package manager metadata Finish(bootstrap): cleaning package manager metadata Finish(bootstrap): chroot init Start: chroot init INFO: mounting tmpfs at /var/lib/mock/fedora-39-aarch64-1709342025.186079/root. INFO: calling preinit hooks INFO: enabled root cache Start: unpacking root cache Finish: unpacking root cache INFO: enabled package manager cache Start: cleaning package manager metadata Finish: cleaning package manager metadata INFO: enabled HW Info plugin INFO: Buildroot is handled by package management downloaded with a bootstrap image: rpm-4.19.0-1.fc39.aarch64 rpm-sequoia-1.5.0-1.fc39.aarch64 python3-dnf-4.19.0-1.fc39.noarch python3-dnf-plugins-core-4.5.0-1.fc39.noarch yum-4.19.0-1.fc39.noarch Finish: chroot init Start: build phase for litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.src.rpm Start: build setup for litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.src.rpm Building target platforms: aarch64 Building for target aarch64 setting SOURCE_DATE_EPOCH=1637193600 Wrote: /builddir/build/SRPMS/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.src.rpm No matches found for the following disable plugin patterns: local, spacewalk, versionlock Copr repository 75 kB/s | 1.5 kB 00:00 Additional repo copr_rezso_ML 82 kB/s | 1.5 kB 00:00 Additional repo copr_rezso_CUDA 76 kB/s | 1.5 kB 00:00 Additional repo http_developer_download_nvidia_ 609 kB/s | 3.5 kB 00:00 Additional repo http_developer_download_nvidia_ 640 kB/s | 3.5 kB 00:00 Additional repo http_developer_download_nvidia_ 529 kB/s | 3.5 kB 00:00 fedora 166 kB/s | 14 kB 00:00 updates 126 kB/s | 13 kB 00:00 Dependencies resolved. ================================================================================ Package Arch Version Repo Size ================================================================================ Installing: git aarch64 2.44.0-1.fc39 updates 53 k python3-devel aarch64 3.12.2-1.fc39 updates 312 k python3-setuptools noarch 67.7.2-7.fc39 fedora 1.5 M Installing dependencies: expat aarch64 2.6.0-1.fc39 updates 111 k git-core aarch64 2.44.0-1.fc39 updates 4.6 M git-core-doc noarch 2.44.0-1.fc39 updates 2.9 M groff-base aarch64 1.23.0-3.fc39 updates 1.1 M less aarch64 633-2.fc39 fedora 176 k libb2 aarch64 0.98.1-9.fc39 fedora 24 k libcbor aarch64 0.10.2-2.fc39 fedora 57 k libedit aarch64 3.1-48.20230828cvs.fc39 fedora 107 k libfido2 aarch64 1.13.0-3.fc39 fedora 96 k mpdecimal aarch64 2.5.1-7.fc39 fedora 90 k ncurses aarch64 6.4-7.20230520.fc39.1 updates 414 k openssh aarch64 9.3p1-10.fc39 updates 431 k openssh-clients aarch64 9.3p1-10.fc39 updates 729 k perl-AutoLoader noarch 5.74-502.fc39 updates 21 k perl-B aarch64 1.88-502.fc39 updates 178 k perl-Carp noarch 1.54-500.fc39 fedora 29 k perl-Class-Struct noarch 0.68-502.fc39 updates 22 k perl-Data-Dumper aarch64 2.188-501.fc39 fedora 55 k perl-Digest noarch 1.20-500.fc39 fedora 25 k perl-Digest-MD5 aarch64 2.58-500.fc39 fedora 36 k perl-DynaLoader aarch64 1.54-502.fc39 updates 26 k perl-Encode aarch64 4:3.19-500.fc39 fedora 1.7 M perl-Errno aarch64 1.37-502.fc39 updates 15 k perl-Error noarch 1:0.17029-13.fc39 fedora 40 k perl-Exporter noarch 5.77-500.fc39 fedora 31 k perl-Fcntl aarch64 1.15-502.fc39 updates 21 k perl-File-Basename noarch 2.86-502.fc39 updates 17 k perl-File-Find noarch 1.43-502.fc39 updates 25 k perl-File-Path noarch 2.18-500.fc39 fedora 35 k perl-File-Temp noarch 1:0.231.100-500.fc39 fedora 58 k perl-File-stat noarch 1.13-502.fc39 updates 17 k perl-FileHandle noarch 2.05-502.fc39 updates 16 k perl-Getopt-Long noarch 1:2.54-500.fc39 fedora 60 k perl-Getopt-Std noarch 1.13-502.fc39 updates 16 k perl-Git noarch 2.44.0-1.fc39 updates 40 k perl-HTTP-Tiny noarch 0.088-3.fc39 fedora 56 k perl-IO aarch64 1.52-502.fc39 updates 83 k perl-IO-Socket-IP noarch 0.42-1.fc39 fedora 42 k perl-IO-Socket-SSL noarch 2.083-3.fc39 fedora 225 k perl-IPC-Open3 noarch 1.22-502.fc39 updates 22 k perl-MIME-Base64 aarch64 3.16-500.fc39 fedora 30 k perl-Mozilla-CA noarch 20230801-1.fc39 fedora 13 k perl-Net-SSLeay aarch64 1.92-10.fc39 fedora 356 k perl-POSIX aarch64 2.13-502.fc39 updates 98 k perl-PathTools aarch64 3.89-500.fc39 fedora 88 k perl-Pod-Escapes noarch 1:1.07-500.fc39 fedora 20 k perl-Pod-Perldoc noarch 3.28.01-501.fc39 fedora 86 k perl-Pod-Simple noarch 1:3.45-4.fc39 fedora 218 k perl-Pod-Usage noarch 4:2.03-500.fc39 fedora 39 k perl-Scalar-List-Utils aarch64 5:1.63-500.fc39 fedora 71 k perl-SelectSaver noarch 1.02-502.fc39 updates 12 k perl-Socket aarch64 4:2.037-3.fc39 fedora 56 k perl-Storable aarch64 1:3.32-500.fc39 fedora 97 k perl-Symbol noarch 1.09-502.fc39 updates 14 k perl-Term-ANSIColor noarch 5.01-501.fc39 fedora 47 k perl-Term-Cap noarch 1.18-500.fc39 fedora 22 k perl-TermReadKey aarch64 2.38-18.fc39 fedora 35 k perl-Text-ParseWords noarch 3.31-500.fc39 fedora 16 k perl-Text-Tabs+Wrap noarch 2023.0511-3.fc39 fedora 22 k perl-Time-Local noarch 2:1.350-3.fc39 fedora 34 k perl-URI noarch 5.21-1.fc39 fedora 125 k perl-base noarch 2.27-502.fc39 updates 16 k perl-constant noarch 1.33-501.fc39 fedora 22 k perl-if noarch 0.61.000-502.fc39 updates 14 k perl-interpreter aarch64 4:5.38.2-502.fc39 updates 72 k perl-lib aarch64 0.65-502.fc39 updates 15 k perl-libnet noarch 3.15-501.fc39 fedora 129 k perl-libs aarch64 4:5.38.2-502.fc39 updates 2.3 M perl-locale noarch 1.10-502.fc39 updates 14 k perl-mro aarch64 1.28-502.fc39 updates 29 k perl-overload noarch 1.37-502.fc39 updates 46 k perl-overloading noarch 0.02-502.fc39 updates 13 k perl-parent noarch 1:0.241-500.fc39 fedora 14 k perl-podlators noarch 1:5.01-500.fc39 fedora 125 k perl-vars noarch 1.05-502.fc39 updates 13 k pyproject-rpm-macros noarch 1.12.0-1.fc39 updates 41 k python-pip-wheel noarch 23.2.1-1.fc39 fedora 1.5 M python-rpm-macros noarch 3.12-4.fc39 fedora 19 k python3 aarch64 3.12.2-1.fc39 updates 27 k python3-libs aarch64 3.12.2-1.fc39 updates 9.2 M python3-packaging noarch 23.1-4.fc39 fedora 114 k python3-rpm-generators noarch 14-7.fc39 fedora 30 k python3-rpm-macros noarch 3.12-4.fc39 fedora 14 k tzdata noarch 2024a-2.fc39 updates 715 k Transaction Summary ================================================================================ Install 87 Packages Total download size: 31 M Installed size: 149 M Downloading Packages: (1/87): libcbor-0.10.2-2.fc39.aarch64.rpm 212 kB/s | 57 kB 00:00 (2/87): libb2-0.98.1-9.fc39.aarch64.rpm 88 kB/s | 24 kB 00:00 (3/87): less-633-2.fc39.aarch64.rpm 250 kB/s | 176 kB 00:00 (4/87): libedit-3.1-48.20230828cvs.fc39.aarch64 237 kB/s | 107 kB 00:00 (5/87): libfido2-1.13.0-3.fc39.aarch64.rpm 210 kB/s | 96 kB 00:00 (6/87): mpdecimal-2.5.1-7.fc39.aarch64.rpm 818 kB/s | 90 kB 00:00 (7/87): perl-Carp-1.54-500.fc39.noarch.rpm 308 kB/s | 29 kB 00:00 (8/87): perl-Data-Dumper-2.188-501.fc39.aarch64 498 kB/s | 55 kB 00:00 (9/87): perl-Digest-1.20-500.fc39.noarch.rpm 823 kB/s | 25 kB 00:00 (10/87): perl-Digest-MD5-2.58-500.fc39.aarch64. 807 kB/s | 36 kB 00:00 (11/87): perl-Error-0.17029-13.fc39.noarch.rpm 43 kB/s | 40 kB 00:00 (12/87): perl-Exporter-5.77-500.fc39.noarch.rpm 33 kB/s | 31 kB 00:00 (13/87): perl-File-Path-2.18-500.fc39.noarch.rp 197 kB/s | 35 kB 00:00 (14/87): perl-File-Temp-0.231.100-500.fc39.noar 332 kB/s | 58 kB 00:00 (15/87): perl-Encode-3.19-500.fc39.aarch64.rpm 1.4 MB/s | 1.7 MB 00:01 (16/87): perl-Getopt-Long-2.54-500.fc39.noarch. 674 kB/s | 60 kB 00:00 (17/87): perl-HTTP-Tiny-0.088-3.fc39.noarch.rpm 490 kB/s | 56 kB 00:00 (18/87): perl-IO-Socket-IP-0.42-1.fc39.noarch.r 693 kB/s | 42 kB 00:00 (19/87): perl-IO-Socket-SSL-2.083-3.fc39.noarch 1.5 MB/s | 225 kB 00:00 (20/87): perl-MIME-Base64-3.16-500.fc39.aarch64 213 kB/s | 30 kB 00:00 (21/87): perl-Mozilla-CA-20230801-1.fc39.noarch 98 kB/s | 13 kB 00:00 (22/87): perl-Net-SSLeay-1.92-10.fc39.aarch64.r 1.6 MB/s | 356 kB 00:00 (23/87): perl-PathTools-3.89-500.fc39.aarch64.r 347 kB/s | 88 kB 00:00 (24/87): perl-Pod-Escapes-1.07-500.fc39.noarch. 77 kB/s | 20 kB 00:00 (25/87): perl-Pod-Perldoc-3.28.01-501.fc39.noar 440 kB/s | 86 kB 00:00 (26/87): perl-Pod-Simple-3.45-4.fc39.noarch.rpm 838 kB/s | 218 kB 00:00 (27/87): perl-Pod-Usage-2.03-500.fc39.noarch.rp 153 kB/s | 39 kB 00:00 (28/87): perl-Scalar-List-Utils-1.63-500.fc39.a 358 kB/s | 71 kB 00:00 (29/87): perl-Socket-2.037-3.fc39.aarch64.rpm 528 kB/s | 56 kB 00:00 (30/87): perl-Storable-3.32-500.fc39.aarch64.rp 446 kB/s | 97 kB 00:00 (31/87): perl-Term-ANSIColor-5.01-501.fc39.noar 350 kB/s | 47 kB 00:00 (32/87): perl-Term-Cap-1.18-500.fc39.noarch.rpm 160 kB/s | 22 kB 00:00 (33/87): perl-TermReadKey-2.38-18.fc39.aarch64. 843 kB/s | 35 kB 00:00 (34/87): perl-Text-ParseWords-3.31-500.fc39.noa 374 kB/s | 16 kB 00:00 (35/87): perl-Text-Tabs+Wrap-2023.0511-3.fc39.n 841 kB/s | 22 kB 00:00 (36/87): perl-Time-Local-1.350-3.fc39.noarch.rp 1.2 MB/s | 34 kB 00:00 (37/87): perl-URI-5.21-1.fc39.noarch.rpm 2.4 MB/s | 125 kB 00:00 (38/87): perl-constant-1.33-501.fc39.noarch.rpm 466 kB/s | 22 kB 00:00 (39/87): perl-libnet-3.15-501.fc39.noarch.rpm 2.4 MB/s | 129 kB 00:00 (40/87): perl-parent-0.241-500.fc39.noarch.rpm 493 kB/s | 14 kB 00:00 (41/87): perl-podlators-5.01-500.fc39.noarch.rp 2.3 MB/s | 125 kB 00:00 (42/87): python-rpm-macros-3.12-4.fc39.noarch.r 70 kB/s | 19 kB 00:00 (43/87): python-pip-wheel-23.2.1-1.fc39.noarch. 4.4 MB/s | 1.5 MB 00:00 (44/87): python3-packaging-23.1-4.fc39.noarch.r 357 kB/s | 114 kB 00:00 (45/87): python3-rpm-generators-14-7.fc39.noarc 367 kB/s | 30 kB 00:00 (46/87): python3-rpm-macros-3.12-4.fc39.noarch. 269 kB/s | 14 kB 00:00 (47/87): expat-2.6.0-1.fc39.aarch64.rpm 2.3 MB/s | 111 kB 00:00 (48/87): git-2.44.0-1.fc39.aarch64.rpm 1.3 MB/s | 53 kB 00:00 (49/87): git-core-2.44.0-1.fc39.aarch64.rpm 108 MB/s | 4.6 MB 00:00 (50/87): groff-base-1.23.0-3.fc39.aarch64.rpm 123 MB/s | 1.1 MB 00:00 (51/87): ncurses-6.4-7.20230520.fc39.1.aarch64. 58 MB/s | 414 kB 00:00 (52/87): git-core-doc-2.44.0-1.fc39.noarch.rpm 61 MB/s | 2.9 MB 00:00 (53/87): openssh-9.3p1-10.fc39.aarch64.rpm 47 MB/s | 431 kB 00:00 (54/87): openssh-clients-9.3p1-10.fc39.aarch64. 92 MB/s | 729 kB 00:00 (55/87): perl-AutoLoader-5.74-502.fc39.noarch.r 3.0 MB/s | 21 kB 00:00 (56/87): perl-B-1.88-502.fc39.aarch64.rpm 27 MB/s | 178 kB 00:00 (57/87): perl-Class-Struct-0.68-502.fc39.noarch 3.3 MB/s | 22 kB 00:00 (58/87): perl-DynaLoader-1.54-502.fc39.aarch64. 4.1 MB/s | 26 kB 00:00 (59/87): perl-Errno-1.37-502.fc39.aarch64.rpm 2.3 MB/s | 15 kB 00:00 (60/87): perl-Fcntl-1.15-502.fc39.aarch64.rpm 3.3 MB/s | 21 kB 00:00 (61/87): perl-File-Basename-2.86-502.fc39.noarc 2.7 MB/s | 17 kB 00:00 (62/87): perl-File-Find-1.43-502.fc39.noarch.rp 3.9 MB/s | 25 kB 00:00 (63/87): perl-File-stat-1.13-502.fc39.noarch.rp 2.6 MB/s | 17 kB 00:00 (64/87): perl-FileHandle-2.05-502.fc39.noarch.r 2.4 MB/s | 16 kB 00:00 (65/87): perl-Getopt-Std-1.13-502.fc39.noarch.r 2.4 MB/s | 16 kB 00:00 (66/87): perl-Git-2.44.0-1.fc39.noarch.rpm 5.6 MB/s | 40 kB 00:00 (67/87): perl-IO-1.52-502.fc39.aarch64.rpm 11 MB/s | 83 kB 00:00 (68/87): perl-IPC-Open3-1.22-502.fc39.noarch.rp 3.4 MB/s | 22 kB 00:00 (69/87): perl-POSIX-2.13-502.fc39.aarch64.rpm 15 MB/s | 98 kB 00:00 (70/87): perl-SelectSaver-1.02-502.fc39.noarch. 1.8 MB/s | 12 kB 00:00 (71/87): perl-Symbol-1.09-502.fc39.noarch.rpm 2.2 MB/s | 14 kB 00:00 (72/87): perl-base-2.27-502.fc39.noarch.rpm 2.6 MB/s | 16 kB 00:00 (73/87): perl-if-0.61.000-502.fc39.noarch.rpm 2.2 MB/s | 14 kB 00:00 (74/87): perl-interpreter-5.38.2-502.fc39.aarch 11 MB/s | 72 kB 00:00 (75/87): perl-lib-0.65-502.fc39.aarch64.rpm 2.1 MB/s | 15 kB 00:00 (76/87): perl-libs-5.38.2-502.fc39.aarch64.rpm 202 MB/s | 2.3 MB 00:00 (77/87): perl-locale-1.10-502.fc39.noarch.rpm 1.2 MB/s | 14 kB 00:00 (78/87): perl-mro-1.28-502.fc39.aarch64.rpm 4.3 MB/s | 29 kB 00:00 (79/87): perl-overload-1.37-502.fc39.noarch.rpm 6.8 MB/s | 46 kB 00:00 (80/87): perl-overloading-0.02-502.fc39.noarch. 2.1 MB/s | 13 kB 00:00 (81/87): perl-vars-1.05-502.fc39.noarch.rpm 2.1 MB/s | 13 kB 00:00 (82/87): pyproject-rpm-macros-1.12.0-1.fc39.noa 6.4 MB/s | 41 kB 00:00 (83/87): python3-3.12.2-1.fc39.aarch64.rpm 4.1 MB/s | 27 kB 00:00 (84/87): python3-devel-3.12.2-1.fc39.aarch64.rp 30 MB/s | 312 kB 00:00 (85/87): tzdata-2024a-2.fc39.noarch.rpm 55 MB/s | 715 kB 00:00 (86/87): python3-libs-3.12.2-1.fc39.aarch64.rpm 259 MB/s | 9.2 MB 00:00 (87/87): python3-setuptools-67.7.2-7.fc39.noarc 4.5 MB/s | 1.5 MB 00:00 -------------------------------------------------------------------------------- Total 8.0 MB/s | 31 MB 00:03 Running transaction check Transaction check succeeded. Running transaction test Transaction test succeeded. Running transaction Preparing : 1/1 Installing : python-rpm-macros-3.12-4.fc39.noarch 1/87 Installing : python3-rpm-macros-3.12-4.fc39.noarch 2/87 Installing : expat-2.6.0-1.fc39.aarch64 3/87 Installing : pyproject-rpm-macros-1.12.0-1.fc39.noarch 4/87 Installing : tzdata-2024a-2.fc39.noarch 5/87 Installing : openssh-9.3p1-10.fc39.aarch64 6/87 Installing : ncurses-6.4-7.20230520.fc39.1.aarch64 7/87 Running scriptlet: groff-base-1.23.0-3.fc39.aarch64 8/87 Installing : groff-base-1.23.0-3.fc39.aarch64 8/87 Running scriptlet: groff-base-1.23.0-3.fc39.aarch64 8/87 Installing : perl-Digest-1.20-500.fc39.noarch 9/87 Installing : perl-Digest-MD5-2.58-500.fc39.aarch64 10/87 Installing : perl-B-1.88-502.fc39.aarch64 11/87 Installing : perl-FileHandle-2.05-502.fc39.noarch 12/87 Installing : perl-Data-Dumper-2.188-501.fc39.aarch64 13/87 Installing : perl-libnet-3.15-501.fc39.noarch 14/87 Installing : perl-AutoLoader-5.74-502.fc39.noarch 15/87 Installing : perl-base-2.27-502.fc39.noarch 16/87 Installing : perl-URI-5.21-1.fc39.noarch 17/87 Installing : perl-Pod-Escapes-1:1.07-500.fc39.noarch 18/87 Installing : perl-Text-Tabs+Wrap-2023.0511-3.fc39.noarch 19/87 Installing : perl-Time-Local-2:1.350-3.fc39.noarch 20/87 Installing : perl-Net-SSLeay-1.92-10.fc39.aarch64 21/87 Installing : perl-Mozilla-CA-20230801-1.fc39.noarch 22/87 Installing : perl-File-Path-2.18-500.fc39.noarch 23/87 Installing : perl-if-0.61.000-502.fc39.noarch 24/87 Installing : perl-locale-1.10-502.fc39.noarch 25/87 Installing : perl-IO-Socket-IP-0.42-1.fc39.noarch 26/87 Installing : perl-IO-Socket-SSL-2.083-3.fc39.noarch 27/87 Installing : perl-Term-ANSIColor-5.01-501.fc39.noarch 28/87 Installing : perl-Term-Cap-1.18-500.fc39.noarch 29/87 Installing : perl-Class-Struct-0.68-502.fc39.noarch 30/87 Installing : perl-POSIX-2.13-502.fc39.aarch64 31/87 Installing : perl-File-Temp-1:0.231.100-500.fc39.noarch 32/87 Installing : perl-HTTP-Tiny-0.088-3.fc39.noarch 33/87 Installing : perl-Pod-Simple-1:3.45-4.fc39.noarch 34/87 Installing : perl-IPC-Open3-1.22-502.fc39.noarch 35/87 Installing : perl-Socket-4:2.037-3.fc39.aarch64 36/87 Installing : perl-SelectSaver-1.02-502.fc39.noarch 37/87 Installing : perl-Symbol-1.09-502.fc39.noarch 38/87 Installing : perl-podlators-1:5.01-500.fc39.noarch 39/87 Installing : perl-Pod-Perldoc-3.28.01-501.fc39.noarch 40/87 Installing : perl-File-stat-1.13-502.fc39.noarch 41/87 Installing : perl-Text-ParseWords-3.31-500.fc39.noarch 42/87 Installing : perl-Fcntl-1.15-502.fc39.aarch64 43/87 Installing : perl-mro-1.28-502.fc39.aarch64 44/87 Installing : perl-Pod-Usage-4:2.03-500.fc39.noarch 45/87 Installing : perl-IO-1.52-502.fc39.aarch64 46/87 Installing : perl-overloading-0.02-502.fc39.noarch 47/87 Installing : perl-MIME-Base64-3.16-500.fc39.aarch64 48/87 Installing : perl-Scalar-List-Utils-5:1.63-500.fc39.aarch64 49/87 Installing : perl-constant-1.33-501.fc39.noarch 50/87 Installing : perl-parent-1:0.241-500.fc39.noarch 51/87 Installing : perl-Errno-1.37-502.fc39.aarch64 52/87 Installing : perl-File-Basename-2.86-502.fc39.noarch 53/87 Installing : perl-Getopt-Std-1.13-502.fc39.noarch 54/87 Installing : perl-Storable-1:3.32-500.fc39.aarch64 55/87 Installing : perl-Getopt-Long-1:2.54-500.fc39.noarch 56/87 Installing : perl-overload-1.37-502.fc39.noarch 57/87 Installing : perl-vars-1.05-502.fc39.noarch 58/87 Installing : perl-Exporter-5.77-500.fc39.noarch 59/87 Installing : perl-PathTools-3.89-500.fc39.aarch64 60/87 Installing : perl-Encode-4:3.19-500.fc39.aarch64 61/87 Installing : perl-DynaLoader-1.54-502.fc39.aarch64 62/87 Installing : perl-Carp-1.54-500.fc39.noarch 63/87 Installing : perl-libs-4:5.38.2-502.fc39.aarch64 64/87 Installing : perl-interpreter-4:5.38.2-502.fc39.aarch64 65/87 Installing : perl-Error-1:0.17029-13.fc39.noarch 66/87 Installing : perl-TermReadKey-2.38-18.fc39.aarch64 67/87 Installing : perl-File-Find-1.43-502.fc39.noarch 68/87 Installing : perl-lib-0.65-502.fc39.aarch64 69/87 Installing : python-pip-wheel-23.2.1-1.fc39.noarch 70/87 Installing : mpdecimal-2.5.1-7.fc39.aarch64 71/87 Installing : libedit-3.1-48.20230828cvs.fc39.aarch64 72/87 Installing : libcbor-0.10.2-2.fc39.aarch64 73/87 Installing : libfido2-1.13.0-3.fc39.aarch64 74/87 Installing : openssh-clients-9.3p1-10.fc39.aarch64 75/87 Running scriptlet: openssh-clients-9.3p1-10.fc39.aarch64 75/87 Installing : libb2-0.98.1-9.fc39.aarch64 76/87 Installing : python3-3.12.2-1.fc39.aarch64 77/87 Installing : python3-libs-3.12.2-1.fc39.aarch64 78/87 Installing : python3-packaging-23.1-4.fc39.noarch 79/87 Installing : python3-rpm-generators-14-7.fc39.noarch 80/87 Installing : less-633-2.fc39.aarch64 81/87 Installing : git-core-2.44.0-1.fc39.aarch64 82/87 Installing : git-core-doc-2.44.0-1.fc39.noarch 83/87 Installing : perl-Git-2.44.0-1.fc39.noarch 84/87 Installing : git-2.44.0-1.fc39.aarch64 85/87 Installing : python3-devel-3.12.2-1.fc39.aarch64 86/87 Installing : python3-setuptools-67.7.2-7.fc39.noarch 87/87 Running scriptlet: python3-setuptools-67.7.2-7.fc39.noarch 87/87 Verifying : less-633-2.fc39.aarch64 1/87 Verifying : libb2-0.98.1-9.fc39.aarch64 2/87 Verifying : libcbor-0.10.2-2.fc39.aarch64 3/87 Verifying : libedit-3.1-48.20230828cvs.fc39.aarch64 4/87 Verifying : libfido2-1.13.0-3.fc39.aarch64 5/87 Verifying : mpdecimal-2.5.1-7.fc39.aarch64 6/87 Verifying : perl-Carp-1.54-500.fc39.noarch 7/87 Verifying : perl-Data-Dumper-2.188-501.fc39.aarch64 8/87 Verifying : perl-Digest-1.20-500.fc39.noarch 9/87 Verifying : perl-Digest-MD5-2.58-500.fc39.aarch64 10/87 Verifying : perl-Encode-4:3.19-500.fc39.aarch64 11/87 Verifying : perl-Error-1:0.17029-13.fc39.noarch 12/87 Verifying : perl-Exporter-5.77-500.fc39.noarch 13/87 Verifying : perl-File-Path-2.18-500.fc39.noarch 14/87 Verifying : perl-File-Temp-1:0.231.100-500.fc39.noarch 15/87 Verifying : perl-Getopt-Long-1:2.54-500.fc39.noarch 16/87 Verifying : perl-HTTP-Tiny-0.088-3.fc39.noarch 17/87 Verifying : perl-IO-Socket-IP-0.42-1.fc39.noarch 18/87 Verifying : perl-IO-Socket-SSL-2.083-3.fc39.noarch 19/87 Verifying : perl-MIME-Base64-3.16-500.fc39.aarch64 20/87 Verifying : perl-Mozilla-CA-20230801-1.fc39.noarch 21/87 Verifying : perl-Net-SSLeay-1.92-10.fc39.aarch64 22/87 Verifying : perl-PathTools-3.89-500.fc39.aarch64 23/87 Verifying : perl-Pod-Escapes-1:1.07-500.fc39.noarch 24/87 Verifying : perl-Pod-Perldoc-3.28.01-501.fc39.noarch 25/87 Verifying : perl-Pod-Simple-1:3.45-4.fc39.noarch 26/87 Verifying : perl-Pod-Usage-4:2.03-500.fc39.noarch 27/87 Verifying : perl-Scalar-List-Utils-5:1.63-500.fc39.aarch64 28/87 Verifying : perl-Socket-4:2.037-3.fc39.aarch64 29/87 Verifying : perl-Storable-1:3.32-500.fc39.aarch64 30/87 Verifying : perl-Term-ANSIColor-5.01-501.fc39.noarch 31/87 Verifying : perl-Term-Cap-1.18-500.fc39.noarch 32/87 Verifying : perl-TermReadKey-2.38-18.fc39.aarch64 33/87 Verifying : perl-Text-ParseWords-3.31-500.fc39.noarch 34/87 Verifying : perl-Text-Tabs+Wrap-2023.0511-3.fc39.noarch 35/87 Verifying : perl-Time-Local-2:1.350-3.fc39.noarch 36/87 Verifying : perl-URI-5.21-1.fc39.noarch 37/87 Verifying : perl-constant-1.33-501.fc39.noarch 38/87 Verifying : perl-libnet-3.15-501.fc39.noarch 39/87 Verifying : perl-parent-1:0.241-500.fc39.noarch 40/87 Verifying : perl-podlators-1:5.01-500.fc39.noarch 41/87 Verifying : python-pip-wheel-23.2.1-1.fc39.noarch 42/87 Verifying : python-rpm-macros-3.12-4.fc39.noarch 43/87 Verifying : python3-packaging-23.1-4.fc39.noarch 44/87 Verifying : python3-rpm-generators-14-7.fc39.noarch 45/87 Verifying : python3-rpm-macros-3.12-4.fc39.noarch 46/87 Verifying : python3-setuptools-67.7.2-7.fc39.noarch 47/87 Verifying : expat-2.6.0-1.fc39.aarch64 48/87 Verifying : git-2.44.0-1.fc39.aarch64 49/87 Verifying : git-core-2.44.0-1.fc39.aarch64 50/87 Verifying : git-core-doc-2.44.0-1.fc39.noarch 51/87 Verifying : groff-base-1.23.0-3.fc39.aarch64 52/87 Verifying : ncurses-6.4-7.20230520.fc39.1.aarch64 53/87 Verifying : openssh-9.3p1-10.fc39.aarch64 54/87 Verifying : openssh-clients-9.3p1-10.fc39.aarch64 55/87 Verifying : perl-AutoLoader-5.74-502.fc39.noarch 56/87 Verifying : perl-B-1.88-502.fc39.aarch64 57/87 Verifying : perl-Class-Struct-0.68-502.fc39.noarch 58/87 Verifying : perl-DynaLoader-1.54-502.fc39.aarch64 59/87 Verifying : perl-Errno-1.37-502.fc39.aarch64 60/87 Verifying : perl-Fcntl-1.15-502.fc39.aarch64 61/87 Verifying : perl-File-Basename-2.86-502.fc39.noarch 62/87 Verifying : perl-File-Find-1.43-502.fc39.noarch 63/87 Verifying : perl-File-stat-1.13-502.fc39.noarch 64/87 Verifying : perl-FileHandle-2.05-502.fc39.noarch 65/87 Verifying : perl-Getopt-Std-1.13-502.fc39.noarch 66/87 Verifying : perl-Git-2.44.0-1.fc39.noarch 67/87 Verifying : perl-IO-1.52-502.fc39.aarch64 68/87 Verifying : perl-IPC-Open3-1.22-502.fc39.noarch 69/87 Verifying : perl-POSIX-2.13-502.fc39.aarch64 70/87 Verifying : perl-SelectSaver-1.02-502.fc39.noarch 71/87 Verifying : perl-Symbol-1.09-502.fc39.noarch 72/87 Verifying : perl-base-2.27-502.fc39.noarch 73/87 Verifying : perl-if-0.61.000-502.fc39.noarch 74/87 Verifying : perl-interpreter-4:5.38.2-502.fc39.aarch64 75/87 Verifying : perl-lib-0.65-502.fc39.aarch64 76/87 Verifying : perl-libs-4:5.38.2-502.fc39.aarch64 77/87 Verifying : perl-locale-1.10-502.fc39.noarch 78/87 Verifying : perl-mro-1.28-502.fc39.aarch64 79/87 Verifying : perl-overload-1.37-502.fc39.noarch 80/87 Verifying : perl-overloading-0.02-502.fc39.noarch 81/87 Verifying : perl-vars-1.05-502.fc39.noarch 82/87 Verifying : pyproject-rpm-macros-1.12.0-1.fc39.noarch 83/87 Verifying : python3-3.12.2-1.fc39.aarch64 84/87 Verifying : python3-devel-3.12.2-1.fc39.aarch64 85/87 Verifying : python3-libs-3.12.2-1.fc39.aarch64 86/87 Verifying : tzdata-2024a-2.fc39.noarch 87/87 Installed: expat-2.6.0-1.fc39.aarch64 git-2.44.0-1.fc39.aarch64 git-core-2.44.0-1.fc39.aarch64 git-core-doc-2.44.0-1.fc39.noarch groff-base-1.23.0-3.fc39.aarch64 less-633-2.fc39.aarch64 libb2-0.98.1-9.fc39.aarch64 libcbor-0.10.2-2.fc39.aarch64 libedit-3.1-48.20230828cvs.fc39.aarch64 libfido2-1.13.0-3.fc39.aarch64 mpdecimal-2.5.1-7.fc39.aarch64 ncurses-6.4-7.20230520.fc39.1.aarch64 openssh-9.3p1-10.fc39.aarch64 openssh-clients-9.3p1-10.fc39.aarch64 perl-AutoLoader-5.74-502.fc39.noarch perl-B-1.88-502.fc39.aarch64 perl-Carp-1.54-500.fc39.noarch perl-Class-Struct-0.68-502.fc39.noarch perl-Data-Dumper-2.188-501.fc39.aarch64 perl-Digest-1.20-500.fc39.noarch perl-Digest-MD5-2.58-500.fc39.aarch64 perl-DynaLoader-1.54-502.fc39.aarch64 perl-Encode-4:3.19-500.fc39.aarch64 perl-Errno-1.37-502.fc39.aarch64 perl-Error-1:0.17029-13.fc39.noarch perl-Exporter-5.77-500.fc39.noarch perl-Fcntl-1.15-502.fc39.aarch64 perl-File-Basename-2.86-502.fc39.noarch perl-File-Find-1.43-502.fc39.noarch perl-File-Path-2.18-500.fc39.noarch perl-File-Temp-1:0.231.100-500.fc39.noarch perl-File-stat-1.13-502.fc39.noarch perl-FileHandle-2.05-502.fc39.noarch perl-Getopt-Long-1:2.54-500.fc39.noarch perl-Getopt-Std-1.13-502.fc39.noarch perl-Git-2.44.0-1.fc39.noarch perl-HTTP-Tiny-0.088-3.fc39.noarch perl-IO-1.52-502.fc39.aarch64 perl-IO-Socket-IP-0.42-1.fc39.noarch perl-IO-Socket-SSL-2.083-3.fc39.noarch perl-IPC-Open3-1.22-502.fc39.noarch perl-MIME-Base64-3.16-500.fc39.aarch64 perl-Mozilla-CA-20230801-1.fc39.noarch perl-Net-SSLeay-1.92-10.fc39.aarch64 perl-POSIX-2.13-502.fc39.aarch64 perl-PathTools-3.89-500.fc39.aarch64 perl-Pod-Escapes-1:1.07-500.fc39.noarch perl-Pod-Perldoc-3.28.01-501.fc39.noarch perl-Pod-Simple-1:3.45-4.fc39.noarch perl-Pod-Usage-4:2.03-500.fc39.noarch perl-Scalar-List-Utils-5:1.63-500.fc39.aarch64 perl-SelectSaver-1.02-502.fc39.noarch perl-Socket-4:2.037-3.fc39.aarch64 perl-Storable-1:3.32-500.fc39.aarch64 perl-Symbol-1.09-502.fc39.noarch perl-Term-ANSIColor-5.01-501.fc39.noarch perl-Term-Cap-1.18-500.fc39.noarch perl-TermReadKey-2.38-18.fc39.aarch64 perl-Text-ParseWords-3.31-500.fc39.noarch perl-Text-Tabs+Wrap-2023.0511-3.fc39.noarch perl-Time-Local-2:1.350-3.fc39.noarch perl-URI-5.21-1.fc39.noarch perl-base-2.27-502.fc39.noarch perl-constant-1.33-501.fc39.noarch perl-if-0.61.000-502.fc39.noarch perl-interpreter-4:5.38.2-502.fc39.aarch64 perl-lib-0.65-502.fc39.aarch64 perl-libnet-3.15-501.fc39.noarch perl-libs-4:5.38.2-502.fc39.aarch64 perl-locale-1.10-502.fc39.noarch perl-mro-1.28-502.fc39.aarch64 perl-overload-1.37-502.fc39.noarch perl-overloading-0.02-502.fc39.noarch perl-parent-1:0.241-500.fc39.noarch perl-podlators-1:5.01-500.fc39.noarch perl-vars-1.05-502.fc39.noarch pyproject-rpm-macros-1.12.0-1.fc39.noarch python-pip-wheel-23.2.1-1.fc39.noarch python-rpm-macros-3.12-4.fc39.noarch python3-3.12.2-1.fc39.aarch64 python3-devel-3.12.2-1.fc39.aarch64 python3-libs-3.12.2-1.fc39.aarch64 python3-packaging-23.1-4.fc39.noarch python3-rpm-generators-14-7.fc39.noarch python3-rpm-macros-3.12-4.fc39.noarch python3-setuptools-67.7.2-7.fc39.noarch tzdata-2024a-2.fc39.noarch Complete! Finish: build setup for litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.src.rpm Start: rpmbuild litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.src.rpm Building target platforms: aarch64 Building for target aarch64 setting SOURCE_DATE_EPOCH=1637193600 Executing(%prep): /bin/sh -e /var/tmp/rpm-tmp.028BOZ + umask 022 + cd /builddir/build/BUILD + cd /builddir/build/BUILD + rm -rf litex-pythondata-cpu-rocket + /usr/bin/mkdir -p litex-pythondata-cpu-rocket + cd litex-pythondata-cpu-rocket + rm -rf /builddir/build/BUILD/litex-pythondata-cpu-rocket-SPECPARTS + /usr/bin/mkdir -p /builddir/build/BUILD/litex-pythondata-cpu-rocket-SPECPARTS + /usr/bin/chmod -Rf a+rX,u+w,g-w,o-w . + git clone --depth 1 -n -b master https://github.com/litex-hub/pythondata-cpu-rocket.git . Cloning into '.'... + git fetch --depth 1 origin 55d7e42913e46ba33e2ade792eef13191c895852 From https://github.com/litex-hub/pythondata-cpu-rocket * branch 55d7e42913e46ba33e2ade792eef13191c895852 -> FETCH_HEAD + git reset --hard 55d7e42913e46ba33e2ade792eef13191c895852 HEAD is now at 55d7e42 update.sh: factor out variant generation and build + git log --format=fuller commit 55d7e42913e46ba33e2ade792eef13191c895852 Author: Gabriel Somlo AuthorDate: Mon Feb 19 18:29:01 2024 -0500 Commit: Gabriel Somlo CommitDate: Mon Feb 19 19:48:33 2024 -0500 update.sh: factor out variant generation and build Signed-off-by: Gabriel Somlo + RPM_EC=0 ++ jobs -p + exit 0 Executing(%build): /bin/sh -e /var/tmp/rpm-tmp.JctKRt + umask 022 + cd /builddir/build/BUILD + CFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -mbranch-protection=standard -fasynchronous-unwind-tables -fstack-clash-protection -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer ' + export CFLAGS + CXXFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -mbranch-protection=standard -fasynchronous-unwind-tables -fstack-clash-protection -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer ' + export CXXFLAGS + FFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -mbranch-protection=standard -fasynchronous-unwind-tables -fstack-clash-protection -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -I/usr/lib64/gfortran/modules ' + export FFLAGS + FCFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -mbranch-protection=standard -fasynchronous-unwind-tables -fstack-clash-protection -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -I/usr/lib64/gfortran/modules ' + export FCFLAGS + VALAFLAGS=-g + export VALAFLAGS + RUSTFLAGS='-Copt-level=3 -Cdebuginfo=2 -Ccodegen-units=1 -Cstrip=none -Cforce-frame-pointers=yes -Clink-arg=-specs=/usr/lib/rpm/redhat/redhat-package-notes' + export RUSTFLAGS + LDFLAGS='-Wl,-z,relro -Wl,--as-needed -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -Wl,--build-id=sha1 -specs=/usr/lib/rpm/redhat/redhat-package-notes ' + export LDFLAGS + LT_SYS_LIBRARY_PATH=/usr/lib64: + export LT_SYS_LIBRARY_PATH + CC=gcc + export CC + CXX=g++ + export CXX + cd litex-pythondata-cpu-rocket + CFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -mbranch-protection=standard -fasynchronous-unwind-tables -fstack-clash-protection -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer ' + LDFLAGS='-Wl,-z,relro -Wl,--as-needed -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -Wl,--build-id=sha1 -specs=/usr/lib/rpm/redhat/redhat-package-notes ' + /usr/bin/python3 setup.py build '--executable=/usr/bin/python3 -sP' running build running build_py creating build creating build/lib creating build/lib/pythondata_cpu_rocket copying pythondata_cpu_rocket/__init__.py -> build/lib/pythondata_cpu_rocket running egg_info creating pythondata_cpu_rocket.egg-info writing pythondata_cpu_rocket.egg-info/PKG-INFO writing dependency_links to pythondata_cpu_rocket.egg-info/dependency_links.txt writing top-level names to pythondata_cpu_rocket.egg-info/top_level.txt writing manifest file 'pythondata_cpu_rocket.egg-info/SOURCES.txt' reading manifest file 'pythondata_cpu_rocket.egg-info/SOURCES.txt' reading manifest template 'MANIFEST.in' warning: no previously-included files matching '*.py[cod]' found anywhere in distribution adding license file 'LICENSE' writing manifest file 'pythondata_cpu_rocket.egg-info/SOURCES.txt' /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_rocket.verilog' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_rocket.verilog' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_rocket.verilog' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_rocket.verilog' to be distributed and are already explicitly excluding 'pythondata_cpu_rocket.verilog' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_rocket.verilog.vsrc' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_rocket.verilog.vsrc' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_rocket.verilog.vsrc' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_rocket.verilog.vsrc' to be distributed and are already explicitly excluding 'pythondata_cpu_rocket.verilog.vsrc' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) creating build/lib/pythondata_cpu_rocket/verilog copying pythondata_cpu_rocket/verilog/.gitignore -> build/lib/pythondata_cpu_rocket/verilog copying pythondata_cpu_rocket/verilog/README.md -> build/lib/pythondata_cpu_rocket/verilog copying pythondata_cpu_rocket/verilog/_upstream.rev -> build/lib/pythondata_cpu_rocket/verilog copying pythondata_cpu_rocket/verilog/update.sh -> build/lib/pythondata_cpu_rocket/verilog creating build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/TestHarness.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0x2010000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.l2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0x2010000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.l2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0x2010000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.l2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0x2010000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.l2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src creating build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/AsyncResetReg.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/ClockDivider2.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/ClockDivider3.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/EICG_wrapper.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/RoccBlackBox.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/SimDTM.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/SimJTAG.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/TestDriver.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/plusarg_reader.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc + RPM_EC=0 ++ jobs -p + exit 0 Executing(%install): /bin/sh -e /var/tmp/rpm-tmp.Jsx8Ka + umask 022 + cd /builddir/build/BUILD + '[' /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64 '!=' / ']' + rm -rf /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64 ++ dirname /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64 + mkdir -p /builddir/build/BUILDROOT + mkdir /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64 + CFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -mbranch-protection=standard -fasynchronous-unwind-tables -fstack-clash-protection -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer ' + export CFLAGS + CXXFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -mbranch-protection=standard -fasynchronous-unwind-tables -fstack-clash-protection -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer ' + export CXXFLAGS + FFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -mbranch-protection=standard -fasynchronous-unwind-tables -fstack-clash-protection -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -I/usr/lib64/gfortran/modules ' + export FFLAGS + FCFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -mbranch-protection=standard -fasynchronous-unwind-tables -fstack-clash-protection -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -I/usr/lib64/gfortran/modules ' + export FCFLAGS + VALAFLAGS=-g + export VALAFLAGS + RUSTFLAGS='-Copt-level=3 -Cdebuginfo=2 -Ccodegen-units=1 -Cstrip=none -Cforce-frame-pointers=yes -Clink-arg=-specs=/usr/lib/rpm/redhat/redhat-package-notes' + export RUSTFLAGS + LDFLAGS='-Wl,-z,relro -Wl,--as-needed -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -Wl,--build-id=sha1 -specs=/usr/lib/rpm/redhat/redhat-package-notes ' + export LDFLAGS + LT_SYS_LIBRARY_PATH=/usr/lib64: + export LT_SYS_LIBRARY_PATH + CC=gcc + export CC + CXX=g++ + export CXX + cd litex-pythondata-cpu-rocket + CFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -mbranch-protection=standard -fasynchronous-unwind-tables -fstack-clash-protection -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer ' + LDFLAGS='-Wl,-z,relro -Wl,--as-needed -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -Wl,--build-id=sha1 -specs=/usr/lib/rpm/redhat/redhat-package-notes ' + /usr/bin/python3 setup.py install -O1 --skip-build --root /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64 --prefix /usr running install /usr/lib/python3.12/site-packages/setuptools/_distutils/cmd.py:66: SetuptoolsDeprecationWarning: setup.py install is deprecated. !! ******************************************************************************** Please avoid running ``setup.py`` directly. Instead, use pypa/build, pypa/installer, pypa/build or other standards-based tools. Follow the current Python packaging guidelines when building Python RPM packages. See https://blog.ganssle.io/articles/2021/10/setup-py-deprecated.html and https://docs.fedoraproject.org/en-US/packaging-guidelines/Python/ for details. ******************************************************************************** !! self.initialize_options() running install_lib creating /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr creating /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib creating /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12 creating /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages creating /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket creating /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog creating /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/plusarg_reader.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/TestDriver.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/SimJTAG.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/SimDTM.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/RoccBlackBox.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/EICG_wrapper.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/ClockDivider3.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/ClockDivider2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/AsyncResetReg.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/vsrc creating /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.l2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0x2010000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.l2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0x2010000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.l2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0x2010000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.l2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0x2010000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/TestHarness.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/update.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog copying build/lib/pythondata_cpu_rocket/verilog/_upstream.rev -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog copying build/lib/pythondata_cpu_rocket/verilog/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog copying build/lib/pythondata_cpu_rocket/verilog/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog copying build/lib/pythondata_cpu_rocket/__init__.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/__init__.py to __init__.cpython-312.pyc writing byte-compilation script '/tmp/tmpo768n10l.py' /usr/bin/python3 /tmp/tmpo768n10l.py removing /tmp/tmpo768n10l.py running install_egg_info running egg_info writing pythondata_cpu_rocket.egg-info/PKG-INFO writing dependency_links to pythondata_cpu_rocket.egg-info/dependency_links.txt writing top-level names to pythondata_cpu_rocket.egg-info/top_level.txt reading manifest file 'pythondata_cpu_rocket.egg-info/SOURCES.txt' reading manifest template 'MANIFEST.in' warning: no previously-included files matching '*.py[cod]' found anywhere in distribution adding license file 'LICENSE' writing manifest file 'pythondata_cpu_rocket.egg-info/SOURCES.txt' Copying pythondata_cpu_rocket.egg-info to /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_rocket-0.0.post7146-py3.12.egg-info running install_scripts + rm -rfv /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/bin/__pycache__ + /usr/bin/find-debuginfo -j4 --strict-build-id -m -i --build-id-seed 2023.12-20240219.0.git55d7e429.fc39 --unique-debug-suffix -2023.12-20240219.0.git55d7e429.fc39.aarch64 --unique-debug-src-base litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64 --run-dwz --dwz-low-mem-die-limit 10000000 --dwz-max-die-limit 50000000 -S debugsourcefiles.list /builddir/build/BUILD/litex-pythondata-cpu-rocket find-debuginfo: starting Extracting debug info from 0 files Creating .debug symlinks for symlinks to ELF files find: ‘debug’: No such file or directory find-debuginfo: done + /usr/lib/rpm/check-buildroot + /usr/lib/rpm/redhat/brp-ldconfig + /usr/lib/rpm/brp-compress + /usr/lib/rpm/redhat/brp-strip-lto /usr/bin/strip + /usr/lib/rpm/brp-strip-static-archive /usr/bin/strip + /usr/lib/rpm/check-rpaths + /usr/lib/rpm/redhat/brp-mangle-shebangs + /usr/lib/rpm/brp-remove-la-files + env /usr/lib/rpm/redhat/brp-python-bytecompile '' 1 0 -j4 Bytecompiling .py files below /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/lib/python3.12 using python3.12 + /usr/lib/rpm/redhat/brp-python-hardlink Processing files: litex-pythondata-cpu-rocket-python3-2023.12-20240219.0.git55d7e429.fc39.noarch Executing(%doc): /bin/sh -e /var/tmp/rpm-tmp.KB32xx + umask 022 + cd /builddir/build/BUILD + cd litex-pythondata-cpu-rocket + DOCDIR=/builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/share/doc/litex-pythondata-cpu-rocket-python3 + export LC_ALL= + LC_ALL= + export DOCDIR + /usr/bin/mkdir -p /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/share/doc/litex-pythondata-cpu-rocket-python3 + cp -pr /builddir/build/BUILD/litex-pythondata-cpu-rocket/README.md /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/share/doc/litex-pythondata-cpu-rocket-python3 + RPM_EC=0 ++ jobs -p + exit 0 Executing(%license): /bin/sh -e /var/tmp/rpm-tmp.ZGedJ9 + umask 022 + cd /builddir/build/BUILD + cd litex-pythondata-cpu-rocket + LICENSEDIR=/builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/share/licenses/litex-pythondata-cpu-rocket-python3 + export LC_ALL= + LC_ALL= + export LICENSEDIR + /usr/bin/mkdir -p /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/share/licenses/litex-pythondata-cpu-rocket-python3 + cp -pr /builddir/build/BUILD/litex-pythondata-cpu-rocket/LICENSE /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64/usr/share/licenses/litex-pythondata-cpu-rocket-python3 + RPM_EC=0 ++ jobs -p + exit 0 Provides: litex-pythondata-cpu-rocket-python3 = 2023.12-20240219.0.git55d7e429.fc39 python3.12dist(pythondata-cpu-rocket) = 0^post7146 python3dist(pythondata-cpu-rocket) = 0^post7146 pythondata-cpu-rocket Requires(rpmlib): rpmlib(CompressedFileNames) <= 3.0.4-1 rpmlib(FileDigests) <= 4.6.0-1 rpmlib(PartialHardlinkSets) <= 4.0.4-1 rpmlib(PayloadFilesHavePrefix) <= 4.0-1 Requires: /usr/bin/sh python(abi) = 3.12 Checking for unpackaged file(s): /usr/lib/rpm/check-files /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64 Wrote: /builddir/build/RPMS/litex-pythondata-cpu-rocket-python3-2023.12-20240219.0.git55d7e429.fc39.noarch.rpm Executing(%clean): /bin/sh -e /var/tmp/rpm-tmp.9xpvAU + umask 022 + cd /builddir/build/BUILD + cd litex-pythondata-cpu-rocket + /usr/bin/rm -rf /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.aarch64 + RPM_EC=0 ++ jobs -p + exit 0 Executing(rmbuild): /bin/sh -e /var/tmp/rpm-tmp.YEdoFz + umask 022 + cd /builddir/build/BUILD + rm -rf /builddir/build/BUILD/litex-pythondata-cpu-rocket-SPECPARTS + rm -rf litex-pythondata-cpu-rocket litex-pythondata-cpu-rocket.gemspec + RPM_EC=0 ++ jobs -p + exit 0 Finish: rpmbuild litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.src.rpm Finish: build phase for litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.src.rpm INFO: chroot_scan: 3 files copied to /var/lib/copr-rpmbuild/results/chroot_scan INFO: /var/lib/mock/fedora-39-aarch64-1709342025.186079/root/var/log/dnf.rpm.log /var/lib/mock/fedora-39-aarch64-1709342025.186079/root/var/log/dnf.librepo.log /var/lib/mock/fedora-39-aarch64-1709342025.186079/root/var/log/dnf.log INFO: Done(/var/lib/copr-rpmbuild/results/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.src.rpm) Config(child) 3 minutes 37 seconds INFO: Results and/or logs in: /var/lib/copr-rpmbuild/results INFO: Cleaning up build root ('cleanup_on_success=True') Start: clean chroot INFO: unmounting tmpfs. Finish: clean chroot Finish: run Running RPMResults tool Package info: { "packages": [ { "name": "litex-pythondata-cpu-rocket-python3", "epoch": null, "version": "2023.12", "release": "20240219.0.git55d7e429.fc39", "arch": "noarch" }, { "name": "litex-pythondata-cpu-rocket", "epoch": null, "version": "2023.12", "release": "20240219.0.git55d7e429.fc39", "arch": "src" } ] } RPMResults finished