Mock Version: 4.1 ENTER ['do_with_status'](['bash', '--login', '-c', '/usr/bin/rpmbuild -bs --target x86_64 --nodeps /builddir/build/SPECS/litex-pythondata-cpu-cv32e40p.spec'], chrootPath='/var/lib/mock/fedora-rawhide-x86_64-1688731539.442348/root'env={'TERM': 'vt100', 'SHELL': '/bin/bash', 'HOME': '/builddir', 'HOSTNAME': 'mock', 'PATH': '/usr/bin:/bin:/usr/sbin:/sbin', 'PROMPT_COMMAND': 'printf "\\033]0;\\007"', 'PS1': ' \\s-\\v\\$ ', 'LANG': 'C.UTF-8'}shell=Falselogger=timeout=0uid=1000gid=135user='mockbuild'nspawn_args=['--capability=cap_ipc_lock', '--rlimit=RLIMIT_NOFILE=10240', '--capability=cap_ipc_lock', '--bind=/tmp/mock-resolv.rh6xcgw2:/etc/resolv.conf', '--bind=/dev/btrfs-control', '--bind=/dev/mapper/control', '--bind=/dev/loop-control', '--bind=/dev/loop0', '--bind=/dev/loop1', '--bind=/dev/loop2', '--bind=/dev/loop3', '--bind=/dev/loop4', '--bind=/dev/loop5', '--bind=/dev/loop6', '--bind=/dev/loop7', '--bind=/dev/loop8', '--bind=/dev/loop9', '--bind=/dev/loop10', '--bind=/dev/loop11']unshare_net=FalseprintOutput=True) Using nspawn with args ['--capability=cap_ipc_lock', '--rlimit=RLIMIT_NOFILE=10240', '--capability=cap_ipc_lock', '--bind=/tmp/mock-resolv.rh6xcgw2:/etc/resolv.conf', '--bind=/dev/btrfs-control', '--bind=/dev/mapper/control', '--bind=/dev/loop-control', '--bind=/dev/loop0', '--bind=/dev/loop1', '--bind=/dev/loop2', '--bind=/dev/loop3', '--bind=/dev/loop4', '--bind=/dev/loop5', '--bind=/dev/loop6', '--bind=/dev/loop7', '--bind=/dev/loop8', '--bind=/dev/loop9', '--bind=/dev/loop10', '--bind=/dev/loop11'] Executing command: ['/usr/bin/systemd-nspawn', '-q', '-M', '85312c62f5494ecd8e05cca508f07b4c', '-D', '/var/lib/mock/fedora-rawhide-x86_64-1688731539.442348/root', '-a', '-u', 'mockbuild', '--capability=cap_ipc_lock', '--rlimit=RLIMIT_NOFILE=10240', '--capability=cap_ipc_lock', '--bind=/tmp/mock-resolv.rh6xcgw2:/etc/resolv.conf', '--bind=/dev/btrfs-control', '--bind=/dev/mapper/control', '--bind=/dev/loop-control', '--bind=/dev/loop0', '--bind=/dev/loop1', '--bind=/dev/loop2', '--bind=/dev/loop3', '--bind=/dev/loop4', '--bind=/dev/loop5', '--bind=/dev/loop6', '--bind=/dev/loop7', '--bind=/dev/loop8', '--bind=/dev/loop9', '--bind=/dev/loop10', '--bind=/dev/loop11', '--console=pipe', '--setenv=TERM=vt100', '--setenv=SHELL=/bin/bash', '--setenv=HOME=/builddir', '--setenv=HOSTNAME=mock', '--setenv=PATH=/usr/bin:/bin:/usr/sbin:/sbin', '--setenv=PROMPT_COMMAND=printf "\\033]0;\\007"', '--setenv=PS1= \\s-\\v\\$ ', '--setenv=LANG=C.UTF-8', '--resolv-conf=off', 'bash', '--login', '-c', '/usr/bin/rpmbuild -bs --target x86_64 --nodeps /builddir/build/SPECS/litex-pythondata-cpu-cv32e40p.spec'] with env {'TERM': 'vt100', 'SHELL': '/bin/bash', 'HOME': '/builddir', 'HOSTNAME': 'mock', 'PATH': '/usr/bin:/bin:/usr/sbin:/sbin', 'PROMPT_COMMAND': 'printf "\\033]0;\\007"', 'PS1': ' \\s-\\v\\$ ', 'LANG': 'C.UTF-8', 'SYSTEMD_NSPAWN_TMPFS_TMP': '0', 'SYSTEMD_SECCOMP': '0'} and shell False Building target platforms: x86_64 Building for target x86_64 setting SOURCE_DATE_EPOCH=1637193600 Wrote: /builddir/build/SRPMS/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.src.rpm Child return code was: 0 ENTER ['do_with_status'](['bash', '--login', '-c', '/usr/bin/rpmbuild -bb --target x86_64 --nodeps /builddir/build/SPECS/litex-pythondata-cpu-cv32e40p.spec'], chrootPath='/var/lib/mock/fedora-rawhide-x86_64-1688731539.442348/root'env={'TERM': 'vt100', 'SHELL': '/bin/bash', 'HOME': '/builddir', 'HOSTNAME': 'mock', 'PATH': '/usr/bin:/bin:/usr/sbin:/sbin', 'PROMPT_COMMAND': 'printf "\\033]0;\\007"', 'PS1': ' \\s-\\v\\$ ', 'LANG': 'C.UTF-8'}shell=Falselogger=timeout=0uid=1000gid=135user='mockbuild'nspawn_args=['--capability=cap_ipc_lock', '--rlimit=RLIMIT_NOFILE=10240', '--capability=cap_ipc_lock', '--bind=/tmp/mock-resolv.rh6xcgw2:/etc/resolv.conf', '--bind=/dev/btrfs-control', '--bind=/dev/mapper/control', '--bind=/dev/loop-control', '--bind=/dev/loop0', '--bind=/dev/loop1', '--bind=/dev/loop2', '--bind=/dev/loop3', '--bind=/dev/loop4', '--bind=/dev/loop5', '--bind=/dev/loop6', '--bind=/dev/loop7', '--bind=/dev/loop8', '--bind=/dev/loop9', '--bind=/dev/loop10', '--bind=/dev/loop11']unshare_net=FalseprintOutput=True) Using nspawn with args ['--capability=cap_ipc_lock', '--rlimit=RLIMIT_NOFILE=10240', '--capability=cap_ipc_lock', '--bind=/tmp/mock-resolv.rh6xcgw2:/etc/resolv.conf', '--bind=/dev/btrfs-control', '--bind=/dev/mapper/control', '--bind=/dev/loop-control', '--bind=/dev/loop0', '--bind=/dev/loop1', '--bind=/dev/loop2', '--bind=/dev/loop3', '--bind=/dev/loop4', '--bind=/dev/loop5', '--bind=/dev/loop6', '--bind=/dev/loop7', '--bind=/dev/loop8', '--bind=/dev/loop9', '--bind=/dev/loop10', '--bind=/dev/loop11'] Executing command: ['/usr/bin/systemd-nspawn', '-q', '-M', 'e8b961a60f5b4d088a0ae5f18c13324b', '-D', '/var/lib/mock/fedora-rawhide-x86_64-1688731539.442348/root', '-a', '-u', 'mockbuild', '--capability=cap_ipc_lock', '--rlimit=RLIMIT_NOFILE=10240', '--capability=cap_ipc_lock', '--bind=/tmp/mock-resolv.rh6xcgw2:/etc/resolv.conf', '--bind=/dev/btrfs-control', '--bind=/dev/mapper/control', '--bind=/dev/loop-control', '--bind=/dev/loop0', '--bind=/dev/loop1', '--bind=/dev/loop2', '--bind=/dev/loop3', '--bind=/dev/loop4', '--bind=/dev/loop5', '--bind=/dev/loop6', '--bind=/dev/loop7', '--bind=/dev/loop8', '--bind=/dev/loop9', '--bind=/dev/loop10', '--bind=/dev/loop11', '--console=pipe', '--setenv=TERM=vt100', '--setenv=SHELL=/bin/bash', '--setenv=HOME=/builddir', '--setenv=HOSTNAME=mock', '--setenv=PATH=/usr/bin:/bin:/usr/sbin:/sbin', '--setenv=PROMPT_COMMAND=printf "\\033]0;\\007"', '--setenv=PS1= \\s-\\v\\$ ', '--setenv=LANG=C.UTF-8', '--resolv-conf=off', 'bash', '--login', '-c', '/usr/bin/rpmbuild -bb --target x86_64 --nodeps /builddir/build/SPECS/litex-pythondata-cpu-cv32e40p.spec'] with env {'TERM': 'vt100', 'SHELL': '/bin/bash', 'HOME': '/builddir', 'HOSTNAME': 'mock', 'PATH': '/usr/bin:/bin:/usr/sbin:/sbin', 'PROMPT_COMMAND': 'printf "\\033]0;\\007"', 'PS1': ' \\s-\\v\\$ ', 'LANG': 'C.UTF-8', 'SYSTEMD_NSPAWN_TMPFS_TMP': '0', 'SYSTEMD_SECCOMP': '0'} and shell False Building target platforms: x86_64 Building for target x86_64 setting SOURCE_DATE_EPOCH=1637193600 Executing(%prep): /bin/sh -e /var/tmp/rpm-tmp.Qpond2 + umask 022 + cd /builddir/build/BUILD + cd /builddir/build/BUILD + rm -rf litex-pythondata-cpu-cv32e40p + /usr/bin/mkdir -p litex-pythondata-cpu-cv32e40p + cd litex-pythondata-cpu-cv32e40p + /usr/bin/mkdir -p SPECPARTS + /usr/bin/chmod -Rf a+rX,u+w,g-w,o-w . + find /builddir/build/BUILD -name SPECPARTS -exec rm -rf '{}' + + git clone --depth 1 -n -b master https://github.com/litex-hub/pythondata-cpu-cv32e40p.git . Cloning into '.'... + git fetch --depth 1 origin c897dc0a291185a7ed6ef6904da1dc698909d6ed From https://github.com/litex-hub/pythondata-cpu-cv32e40p * branch c897dc0a291185a7ed6ef6904da1dc698909d6ed -> FETCH_HEAD + git reset --hard c897dc0a291185a7ed6ef6904da1dc698909d6ed HEAD is now at c897dc0 Updating pythondata-cpu-cv32e40p to 0.0.post152 + git log --format=fuller commit c897dc0a291185a7ed6ef6904da1dc698909d6ed Author: LiteX Robot AuthorDate: Mon May 30 19:55:45 2022 +0000 Commit: LiteX Robot CommitDate: Mon May 30 19:55:45 2022 +0000 Updating pythondata-cpu-cv32e40p to 0.0.post152 Updated data to v0.0-10-g087cb61 based on 087cb61a182f6bc4f757d3430865482aaff61cba from https://github.com/antmicro/cv32e40p. > commit 087cb61a182f6bc4f757d3430865482aaff61cba > Author: Piotr Binkowski > Date: Wed May 20 14:40:57 2020 +0200 > > disable sim tracer > Updated using 0.0.post142 from https://github.com/litex-hub/litex-data-auto + RPM_EC=0 ++ jobs -p + exit 0 Executing(%build): /bin/sh -e /var/tmp/rpm-tmp.CqNogS + umask 022 + cd /builddir/build/BUILD + CFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -m64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer ' + export CFLAGS + CXXFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -m64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer ' + export CXXFLAGS + FFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -m64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -I/usr/lib64/gfortran/modules ' + export FFLAGS + FCFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -m64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -I/usr/lib64/gfortran/modules ' + export FCFLAGS + VALAFLAGS=-g + export VALAFLAGS + RUSTFLAGS='-Copt-level=3 -Cdebuginfo=2 -Ccodegen-units=1 -Cforce-frame-pointers=yes -Clink-arg=-Wl,-z,relro -Clink-arg=-Wl,-z,now -Clink-arg=-specs=/usr/lib/rpm/redhat/redhat-package-notes --cap-lints=warn' + export RUSTFLAGS + LDFLAGS='-Wl,-z,relro -Wl,--as-needed -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -Wl,--build-id=sha1 -specs=/usr/lib/rpm/redhat/redhat-package-notes ' + export LDFLAGS + LT_SYS_LIBRARY_PATH=/usr/lib64: + export LT_SYS_LIBRARY_PATH + CC=gcc + export CC + CXX=g++ + export CXX + cd litex-pythondata-cpu-cv32e40p + CFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -m64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer ' + LDFLAGS='-Wl,-z,relro -Wl,--as-needed -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -Wl,--build-id=sha1 -specs=/usr/lib/rpm/redhat/redhat-package-notes ' + /usr/bin/python3 setup.py build '--executable=/usr/bin/python3 -sP' running build running build_py creating build creating build/lib creating build/lib/pythondata_cpu_cv32e40p copying pythondata_cpu_cv32e40p/__init__.py -> build/lib/pythondata_cpu_cv32e40p running egg_info creating pythondata_cpu_cv32e40p.egg-info writing pythondata_cpu_cv32e40p.egg-info/PKG-INFO writing dependency_links to pythondata_cpu_cv32e40p.egg-info/dependency_links.txt writing top-level names to pythondata_cpu_cv32e40p.egg-info/top_level.txt writing manifest file 'pythondata_cpu_cv32e40p.egg-info/SOURCES.txt' reading manifest file 'pythondata_cpu_cv32e40p.egg-info/SOURCES.txt' reading manifest template 'MANIFEST.in' warning: no previously-included files matching '*.py[cod]' found anywhere in distribution adding license file 'LICENSE' writing manifest file 'pythondata_cpu_cv32e40p.egg-info/SOURCES.txt' /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e40p.system_verilog' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e40p.system_verilog' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e40p.system_verilog' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e40p.system_verilog' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e40p.system_verilog' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e40p.system_verilog.ci' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e40p.system_verilog.ci' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e40p.system_verilog.ci' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e40p.system_verilog.ci' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e40p.system_verilog.ci' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e40p.system_verilog.doc' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e40p.system_verilog.doc' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e40p.system_verilog.doc' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e40p.system_verilog.doc' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e40p.system_verilog.doc' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e40p.system_verilog.pd' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e40p.system_verilog.pd' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e40p.system_verilog.pd' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e40p.system_verilog.pd' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e40p.system_verilog.pd' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e40p.system_verilog.rtl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e40p.system_verilog.rtl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e40p.system_verilog.rtl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e40p.system_verilog.rtl' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e40p.system_verilog.rtl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e40p.system_verilog.rtl.include' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e40p.system_verilog.rtl.include' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e40p.system_verilog.rtl.include' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e40p.system_verilog.rtl.include' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e40p.system_verilog.rtl.include' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e40p.system_verilog.tb.core' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e40p.system_verilog.tb.core' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e40p.system_verilog.tb.core' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e40p.system_verilog.tb.core' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e40p.system_verilog.tb.core' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e40p.system_verilog.tb.core.csmith' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e40p.system_verilog.tb.core.csmith' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e40p.system_verilog.tb.core.csmith' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e40p.system_verilog.tb.core.csmith' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e40p.system_verilog.tb.core.csmith' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e40p.system_verilog.tb.core.custom' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e40p.system_verilog.tb.core.custom' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e40p.system_verilog.tb.core.custom' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e40p.system_verilog.tb.core.custom' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e40p.system_verilog.tb.core.custom' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e40p.system_verilog.tb.core.custom_fp' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e40p.system_verilog.tb.core.custom_fp' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e40p.system_verilog.tb.core.custom_fp' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e40p.system_verilog.tb.core.custom_fp' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e40p.system_verilog.tb.core.custom_fp' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e40p.system_verilog.tb.core.firmware' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e40p.system_verilog.tb.core.firmware' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e40p.system_verilog.tb.core.firmware' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e40p.system_verilog.tb.core.firmware' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e40p.system_verilog.tb.core.firmware' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e40p.system_verilog.tb.core.interrupt_test' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e40p.system_verilog.tb.core.interrupt_test' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e40p.system_verilog.tb.core.interrupt_test' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e40p.system_verilog.tb.core.interrupt_test' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e40p.system_verilog.tb.core.interrupt_test' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_compliance_tests' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_compliance_tests' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_compliance_tests' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_compliance_tests' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_compliance_tests' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_compliance_tests.disabled' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_compliance_tests.disabled' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_compliance_tests.disabled' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_compliance_tests.disabled' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_compliance_tests.disabled' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.macros.scalar' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.macros.scalar' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.macros.scalar' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.macros.scalar' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.macros.scalar' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv32mi' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv32mi' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv32mi' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv32mi' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv32mi' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv32si' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv32si' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv32si' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv32si' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv32si' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv32ua' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv32ua' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv32ua' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv32ua' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv32ua' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv32uc' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv32uc' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv32uc' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv32uc' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv32uc' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv32ud' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv32ud' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv32ud' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv32ud' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv32ud' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv32uf' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv32uf' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv32uf' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv32uf' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv32uf' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv32ui' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv32ui' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv32ui' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv32ui' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv32ui' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv32um' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv32um' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv32um' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv32um' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv32um' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv64mi' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv64mi' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv64mi' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv64mi' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv64mi' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv64si' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv64si' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv64si' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv64si' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv64si' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv64ua' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv64ua' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv64ua' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv64ua' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv64ua' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv64uc' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv64uc' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv64uc' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv64uc' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv64uc' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv64ud' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv64ud' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv64ud' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv64ud' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv64ud' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv64uf' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv64uf' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv64uf' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv64uf' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv64uf' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) creating build/lib/pythondata_cpu_cv32e40p/system_verilog copying pythondata_cpu_cv32e40p/system_verilog/.dir-locals.el -> build/lib/pythondata_cpu_cv32e40p/system_verilog copying pythondata_cpu_cv32e40p/system_verilog/.gitignore -> build/lib/pythondata_cpu_cv32e40p/system_verilog copying pythondata_cpu_cv32e40p/system_verilog/.gitlab-ci.yml -> build/lib/pythondata_cpu_cv32e40p/system_verilog copying pythondata_cpu_cv32e40p/system_verilog/.gitmodules -> build/lib/pythondata_cpu_cv32e40p/system_verilog copying pythondata_cpu_cv32e40p/system_verilog/.travis.yml -> build/lib/pythondata_cpu_cv32e40p/system_verilog copying pythondata_cpu_cv32e40p/system_verilog/Bender.yml -> build/lib/pythondata_cpu_cv32e40p/system_verilog copying pythondata_cpu_cv32e40p/system_verilog/CONTRIBUTING.md -> build/lib/pythondata_cpu_cv32e40p/system_verilog copying pythondata_cpu_cv32e40p/system_verilog/LICENSE -> build/lib/pythondata_cpu_cv32e40p/system_verilog copying pythondata_cpu_cv32e40p/system_verilog/Makefile -> build/lib/pythondata_cpu_cv32e40p/system_verilog copying pythondata_cpu_cv32e40p/system_verilog/README.md -> build/lib/pythondata_cpu_cv32e40p/system_verilog copying pythondata_cpu_cv32e40p/system_verilog/cv32e40p_dm_manifest.flist -> build/lib/pythondata_cpu_cv32e40p/system_verilog copying pythondata_cpu_cv32e40p/system_verilog/cv32e40p_fpu_manifest.flist -> build/lib/pythondata_cpu_cv32e40p/system_verilog copying pythondata_cpu_cv32e40p/system_verilog/cv32e40p_manifest.flist -> build/lib/pythondata_cpu_cv32e40p/system_verilog copying pythondata_cpu_cv32e40p/system_verilog/cv32e40p_trace_manifest.flist -> build/lib/pythondata_cpu_cv32e40p/system_verilog copying pythondata_cpu_cv32e40p/system_verilog/src_files.yml -> build/lib/pythondata_cpu_cv32e40p/system_verilog creating build/lib/pythondata_cpu_cv32e40p/system_verilog/ci copying pythondata_cpu_cv32e40p/system_verilog/ci/Jenkinsfile -> build/lib/pythondata_cpu_cv32e40p/system_verilog/ci copying pythondata_cpu_cv32e40p/system_verilog/ci/build-riscv-gcc.sh -> build/lib/pythondata_cpu_cv32e40p/system_verilog/ci copying pythondata_cpu_cv32e40p/system_verilog/ci/download-pulp-gcc.sh -> build/lib/pythondata_cpu_cv32e40p/system_verilog/ci copying pythondata_cpu_cv32e40p/system_verilog/ci/get-openocd.sh -> build/lib/pythondata_cpu_cv32e40p/system_verilog/ci copying pythondata_cpu_cv32e40p/system_verilog/ci/install-verilator.sh -> build/lib/pythondata_cpu_cv32e40p/system_verilog/ci copying pythondata_cpu_cv32e40p/system_verilog/ci/make-tmp.sh -> build/lib/pythondata_cpu_cv32e40p/system_verilog/ci copying pythondata_cpu_cv32e40p/system_verilog/ci/openocd-to-junit.py -> build/lib/pythondata_cpu_cv32e40p/system_verilog/ci copying pythondata_cpu_cv32e40p/system_verilog/ci/run-openocd-compliance.sh -> build/lib/pythondata_cpu_cv32e40p/system_verilog/ci copying pythondata_cpu_cv32e40p/system_verilog/ci/rv32tests-to-junit.py -> build/lib/pythondata_cpu_cv32e40p/system_verilog/ci copying pythondata_cpu_cv32e40p/system_verilog/ci/veri-run-openocd-compliance.sh -> build/lib/pythondata_cpu_cv32e40p/system_verilog/ci creating build/lib/pythondata_cpu_cv32e40p/system_verilog/doc copying pythondata_cpu_cv32e40p/system_verilog/doc/NONSECURED_RI5CY_DEBUG_reference.xlsx -> build/lib/pythondata_cpu_cv32e40p/system_verilog/doc copying pythondata_cpu_cv32e40p/system_verilog/doc/SECURED_RI5CY_DEBUG_reference.xlsx -> build/lib/pythondata_cpu_cv32e40p/system_verilog/doc copying pythondata_cpu_cv32e40p/system_verilog/doc/user_manual.doc -> build/lib/pythondata_cpu_cv32e40p/system_verilog/doc creating build/lib/pythondata_cpu_cv32e40p/system_verilog/pd copying pythondata_cpu_cv32e40p/system_verilog/pd/README.md -> build/lib/pythondata_cpu_cv32e40p/system_verilog/pd creating build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl copying pythondata_cpu_cv32e40p/system_verilog/rtl/cv32e40p_sim_clock_gate.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl copying pythondata_cpu_cv32e40p/system_verilog/rtl/register_file_test_wrap.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl copying pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_L0_buffer.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl copying pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_alu.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl copying pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_alu_div.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv64ui' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv64ui' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv64ui' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv64ui' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv64ui' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv64um' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv64um' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv64um' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv64um' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e40p.system_verilog.tb.core.riscv_tests.rv64um' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e40p.system_verilog.tb.dm' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e40p.system_verilog.tb.dm' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e40p.system_verilog.tb.dm' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e40p.system_verilog.tb.dm' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e40p.system_verilog.tb.dm' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e40p.system_verilog.tb.dm.prog' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e40p.system_verilog.tb.dm.prog' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e40p.system_verilog.tb.dm.prog' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e40p.system_verilog.tb.dm.prog' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e40p.system_verilog.tb.dm.prog' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e40p.system_verilog.tb.dm.remote_bitbang' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e40p.system_verilog.tb.dm.remote_bitbang' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e40p.system_verilog.tb.dm.remote_bitbang' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e40p.system_verilog.tb.dm.remote_bitbang' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e40p.system_verilog.tb.dm.remote_bitbang' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e40p.system_verilog.tb.dm.unused' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e40p.system_verilog.tb.dm.unused' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e40p.system_verilog.tb.dm.unused' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e40p.system_verilog.tb.dm.unused' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e40p.system_verilog.tb.dm.unused' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e40p.system_verilog.tb.scripts' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e40p.system_verilog.tb.scripts' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e40p.system_verilog.tb.scripts' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e40p.system_verilog.tb.scripts' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e40p.system_verilog.tb.scripts' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e40p.system_verilog.tb.serDiv' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e40p.system_verilog.tb.serDiv' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e40p.system_verilog.tb.serDiv' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e40p.system_verilog.tb.serDiv' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e40p.system_verilog.tb.serDiv' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e40p.system_verilog.tb.serDiv.scripts' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e40p.system_verilog.tb.serDiv.scripts' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e40p.system_verilog.tb.serDiv.scripts' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e40p.system_verilog.tb.serDiv.scripts' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e40p.system_verilog.tb.serDiv.scripts' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e40p.system_verilog.tb.tb_MPU' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e40p.system_verilog.tb.tb_MPU' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e40p.system_verilog.tb.tb_MPU' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e40p.system_verilog.tb.tb_MPU' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e40p.system_verilog.tb.tb_MPU' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e40p.system_verilog.tb.tb_riscv' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e40p.system_verilog.tb.tb_riscv' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e40p.system_verilog.tb.tb_riscv' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e40p.system_verilog.tb.tb_riscv' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e40p.system_verilog.tb.tb_riscv' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e40p.system_verilog.tb.tb_riscv.include' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e40p.system_verilog.tb.tb_riscv.include' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e40p.system_verilog.tb.tb_riscv.include' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e40p.system_verilog.tb.tb_riscv.include' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e40p.system_verilog.tb.tb_riscv.include' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e40p.system_verilog.tb' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e40p.system_verilog.tb' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e40p.system_verilog.tb' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e40p.system_verilog.tb' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e40p.system_verilog.tb' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) copying pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_apu_disp.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl copying pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_compressed_decoder.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl copying pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_controller.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl copying pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_core.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl copying pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_cs_registers.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl copying pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_decoder.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl copying pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_ex_stage.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl copying pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_fetch_fifo.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl copying pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_hwloop_controller.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl copying pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_hwloop_regs.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl copying pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_id_stage.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl copying pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_if_stage.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl copying pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_int_controller.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl copying pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_load_store_unit.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl copying pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_mult.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl copying pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_pmp.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl copying pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_prefetch_L0_buffer.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl copying pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_prefetch_buffer.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl copying pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_register_file.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl copying pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_register_file_latch.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl copying pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_tracer.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl creating build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl/include copying pythondata_cpu_cv32e40p/system_verilog/rtl/include/apu_core_package.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl/include copying pythondata_cpu_cv32e40p/system_verilog/rtl/include/apu_macros.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl/include copying pythondata_cpu_cv32e40p/system_verilog/rtl/include/riscv_config.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl/include copying pythondata_cpu_cv32e40p/system_verilog/rtl/include/riscv_defines.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl/include copying pythondata_cpu_cv32e40p/system_verilog/rtl/include/riscv_tracer_defines.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl/include creating build/lib/pythondata_cpu_cv32e40p/system_verilog/tb creating build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core copying pythondata_cpu_cv32e40p/system_verilog/tb/core/.clang-format -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core copying pythondata_cpu_cv32e40p/system_verilog/tb/core/.gitignore -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core copying pythondata_cpu_cv32e40p/system_verilog/tb/core/Makefile -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core copying pythondata_cpu_cv32e40p/system_verilog/tb/core/README.md -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core copying pythondata_cpu_cv32e40p/system_verilog/tb/core/amo_shim.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core copying pythondata_cpu_cv32e40p/system_verilog/tb/core/dp_ram.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core copying pythondata_cpu_cv32e40p/system_verilog/tb/core/mm_ram.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_wrapper.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core copying pythondata_cpu_cv32e40p/system_verilog/tb/core/software.tcl -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core copying pythondata_cpu_cv32e40p/system_verilog/tb/core/tb_top.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core copying pythondata_cpu_cv32e40p/system_verilog/tb/core/tb_top_verilator.cpp -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core copying pythondata_cpu_cv32e40p/system_verilog/tb/core/tb_top_verilator.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core copying pythondata_cpu_cv32e40p/system_verilog/tb/core/vsim.tcl -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core copying pythondata_cpu_cv32e40p/system_verilog/tb/core/waves.tcl -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core creating build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/csmith copying pythondata_cpu_cv32e40p/system_verilog/tb/core/csmith/license_notes -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/csmith copying pythondata_cpu_cv32e40p/system_verilog/tb/core/csmith/link.ld -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/csmith copying pythondata_cpu_cv32e40p/system_verilog/tb/core/csmith/riscv-isa-sim.diff -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/csmith copying pythondata_cpu_cv32e40p/system_verilog/tb/core/csmith/start.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/csmith copying pythondata_cpu_cv32e40p/system_verilog/tb/core/csmith/syscalls.c -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/csmith creating build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/custom copying pythondata_cpu_cv32e40p/system_verilog/tb/core/custom/crt0.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/custom copying pythondata_cpu_cv32e40p/system_verilog/tb/core/custom/hello_world.c -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/custom copying pythondata_cpu_cv32e40p/system_verilog/tb/core/custom/link.ld -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/custom copying pythondata_cpu_cv32e40p/system_verilog/tb/core/custom/syscalls.c -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/custom copying pythondata_cpu_cv32e40p/system_verilog/tb/core/custom/vectors.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/custom creating build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/custom_fp copying pythondata_cpu_cv32e40p/system_verilog/tb/core/custom_fp/main.c -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/custom_fp copying pythondata_cpu_cv32e40p/system_verilog/tb/core/custom_fp/matmulNxN.c -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/custom_fp creating build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware copying pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware/README -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware copying pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware/firmware.h -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware copying pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware/link.ld -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware copying pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware/makehex.py -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware copying pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware/multest.c -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware copying pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware/print.c -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware copying pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware/riscv.ld -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware copying pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware/riscv.ld.orig -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware copying pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware/sieve.c -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware copying pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware/start.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware copying pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware/stats.c -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware creating build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/interrupt_test copying pythondata_cpu_cv32e40p/system_verilog/tb/core/interrupt_test/interrupt_test.c -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/interrupt_test copying pythondata_cpu_cv32e40p/system_verilog/tb/core/interrupt_test/isr.h -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/interrupt_test copying pythondata_cpu_cv32e40p/system_verilog/tb/core/interrupt_test/matrix.h -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/interrupt_test copying pythondata_cpu_cv32e40p/system_verilog/tb/core/interrupt_test/vectors.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/interrupt_test creating build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-ADD-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-ADDI-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-AND-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-ANDI-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-AUIPC-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-BEQ-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-BGE-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-BGEU-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-BLT-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-BLTU-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-BNE-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-CSRRC-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-CSRRCI-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-CSRRS-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-CSRRSI-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-CSRRW-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-CSRRWI-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-DELAY_SLOTS-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-EBREAK-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-ECALL-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-ENDIANESS-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-FENCE.I-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-IO.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-JAL-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-JALR-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-LB-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-LBU-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-LH-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-LHU-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-LUI-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-LW-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-NOP-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-OR-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-ORI-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-RF_size-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-RF_width-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-RF_x0-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-SLL-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-SLLI-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-SLT-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-SLTI-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-SLTIU-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-SLTU-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-SRA-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-SRAI-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-SRL-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-SRLI-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-SUB-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-SW-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-XOR-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-XORI-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/aw_test_macros.h -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/compliance_io.h -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/compliance_test.h -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/riscv_test.h -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/test_macros.h -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests creating build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/disabled copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/disabled/I-FENCE.I-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/disabled copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/disabled/I-MISALIGN_JMP-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/disabled copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/disabled/I-MISALIGN_LDST-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/disabled copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/disabled/I-SB-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/disabled copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/disabled/I-SH-01.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/disabled creating build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/LICENSE -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/README.md -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/riscv_test.h -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests creating build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/macros creating build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/macros/scalar copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/macros/scalar/test_macros.h -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/macros/scalar creating build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32mi copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32mi/Makefrag -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32mi copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32mi/breakpoint.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32mi copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32mi/csr.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32mi copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32mi/illegal.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32mi copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32mi/ma_addr.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32mi copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32mi/ma_fetch.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32mi copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32mi/mcsr.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32mi copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32mi/sbreak.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32mi copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32mi/scall.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32mi copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32mi/shamt.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32mi creating build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32si copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32si/Makefrag -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32si copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32si/csr.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32si copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32si/dirty.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32si copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32si/ma_fetch.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32si copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32si/sbreak.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32si copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32si/scall.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32si copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32si/wfi.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32si creating build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua/Makefrag -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua/amoadd_w.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua/amoand_w.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua/amomax_w.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua/amomaxu_w.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua/amomin_w.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua/amominu_w.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua/amoor_w.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua/amoswap_w.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua/amoxor_w.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua/lrsc.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua creating build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uc copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uc/Makefrag -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uc copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uc/rvc.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uc creating build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud/Makefrag -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud/fadd.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud/fclass.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud/fcmp.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud/fcvt.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud/fcvt_w.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud/fdiv.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud/fmadd.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud/fmin.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud/ldst.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud/move.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud/recoding.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud creating build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf/Makefrag -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf/fadd.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf/fclass.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf/fcmp.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf/fcvt.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf/fcvt_w.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf/fdiv.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf/fmadd.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf/fmin.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf/ldst.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf/move.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf/recoding.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf creating build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/Makefrag -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/add.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/addi.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/and.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/andi.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/auipc.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/beq.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/bge.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/bgeu.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/blt.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/bltu.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/bne.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/fence_i.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/jal.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/jalr.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/lb.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/lbu.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/lh.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/lhu.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/lui.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/lw.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/or.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/ori.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/sb.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/sh.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/simple.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/sll.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/slli.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/slt.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/slti.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/sltiu.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/sltu.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/sra.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/srai.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/srl.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/srli.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/sub.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/sw.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/xor.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/xori.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui creating build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32um copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32um/Makefrag -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32um copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32um/div.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32um copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32um/divu.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32um copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32um/mul.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32um copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32um/mulh.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32um copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32um/mulhsu.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32um copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32um/mulhu.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32um copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32um/rem.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32um copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32um/remu.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32um creating build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64mi copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64mi/Makefrag -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64mi copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64mi/access.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64mi copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64mi/breakpoint.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64mi copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64mi/csr.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64mi copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64mi/illegal.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64mi copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64mi/ma_addr.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64mi copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64mi/ma_fetch.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64mi copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64mi/mcsr.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64mi copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64mi/sbreak.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64mi copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64mi/scall.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64mi creating build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64si copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64si/Makefrag -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64si copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64si/csr.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64si copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64si/dirty.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64si copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64si/ma_fetch.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64si copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64si/sbreak.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64si copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64si/scall.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64si copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64si/wfi.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64si creating build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua/Makefrag -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua/amoadd_d.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua/amoadd_w.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua/amoand_d.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua/amoand_w.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua/amomax_d.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua/amomax_w.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua/amomaxu_d.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua/amomaxu_w.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua/amomin_d.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua/amomin_w.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua/amominu_d.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua/amominu_w.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua/amoor_d.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua/amoor_w.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua/amoswap_d.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua/amoswap_w.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua/amoxor_d.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua/amoxor_w.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua/lrsc.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua creating build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uc copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uc/Makefrag -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uc copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uc/rvc.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uc creating build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud/Makefrag -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud/fadd.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud/fclass.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud/fcmp.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud/fcvt.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud/fcvt_w.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud/fdiv.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud/fmadd.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud/fmin.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud/ldst.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud/move.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud/recoding.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud/structural.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud creating build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf/Makefrag -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf/fadd.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf/fclass.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf/fcmp.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf/fcvt.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf/fcvt_w.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf/fdiv.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf/fmadd.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf/fmin.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf/ldst.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf/move.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf/recoding.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf creating build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/Makefrag -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/add.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/addi.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/addiw.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/addw.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/and.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/andi.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/auipc.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/beq.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/bge.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/bgeu.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/blt.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/bltu.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/bne.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/fence_i.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/jal.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/jalr.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/lb.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/lbu.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/ld.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/lh.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/lhu.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/lui.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/lw.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/lwu.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/or.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/ori.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/sb.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/sd.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/sh.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/simple.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/sll.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/slli.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/slliw.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/sllw.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/slt.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/slti.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/sltiu.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/sltu.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/sra.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/srai.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/sraiw.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/sraw.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/srl.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/srli.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/srliw.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/srlw.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/sub.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/subw.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/sw.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/xor.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/xori.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui creating build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um/Makefrag -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um/div.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um/divu.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um/divuw.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um/divw.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um/mul.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um/mulh.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um/mulhsu.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um/mulhu.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um/mulw.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um/rem.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um/remu.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um/remuw.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um copying pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um/remw.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um creating build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm copying pythondata_cpu_cv32e40p/system_verilog/tb/dm/.clang-format -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm copying pythondata_cpu_cv32e40p/system_verilog/tb/dm/.gitignore -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm copying pythondata_cpu_cv32e40p/system_verilog/tb/dm/LICENSE.Berkeley -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm copying pythondata_cpu_cv32e40p/system_verilog/tb/dm/LICENSE.SiFive -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm copying pythondata_cpu_cv32e40p/system_verilog/tb/dm/Makefile -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm copying pythondata_cpu_cv32e40p/system_verilog/tb/dm/README.md -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm copying pythondata_cpu_cv32e40p/system_verilog/tb/dm/SimJTAG.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm copying pythondata_cpu_cv32e40p/system_verilog/tb/dm/boot_rom.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm copying pythondata_cpu_cv32e40p/system_verilog/tb/dm/dp_ram.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm copying pythondata_cpu_cv32e40p/system_verilog/tb/dm/mm_ram.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm copying pythondata_cpu_cv32e40p/system_verilog/tb/dm/pulpissimo_compliance_test.cfg -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm copying pythondata_cpu_cv32e40p/system_verilog/tb/dm/pulpissimo_debug.cfg -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm copying pythondata_cpu_cv32e40p/system_verilog/tb/dm/riscv_tb_pkg.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm copying pythondata_cpu_cv32e40p/system_verilog/tb/dm/tb_test_env.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm copying pythondata_cpu_cv32e40p/system_verilog/tb/dm/tb_top.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm copying pythondata_cpu_cv32e40p/system_verilog/tb/dm/tb_top_verilator.cpp -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm copying pythondata_cpu_cv32e40p/system_verilog/tb/dm/tb_top_verilator.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm copying pythondata_cpu_cv32e40p/system_verilog/tb/dm/vsim_batch.tcl -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm copying pythondata_cpu_cv32e40p/system_verilog/tb/dm/vsim_gui.tcl -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm copying pythondata_cpu_cv32e40p/system_verilog/tb/dm/waves.tcl -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm creating build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/prog copying pythondata_cpu_cv32e40p/system_verilog/tb/dm/prog/link.ld -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/prog copying pythondata_cpu_cv32e40p/system_verilog/tb/dm/prog/start.S -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/prog copying pythondata_cpu_cv32e40p/system_verilog/tb/dm/prog/syscalls.c -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/prog copying pythondata_cpu_cv32e40p/system_verilog/tb/dm/prog/test.c -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/prog creating build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/remote_bitbang copying pythondata_cpu_cv32e40p/system_verilog/tb/dm/remote_bitbang/.gitignore -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/remote_bitbang copying pythondata_cpu_cv32e40p/system_verilog/tb/dm/remote_bitbang/Makefile -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/remote_bitbang copying pythondata_cpu_cv32e40p/system_verilog/tb/dm/remote_bitbang/rbs_test.c -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/remote_bitbang copying pythondata_cpu_cv32e40p/system_verilog/tb/dm/remote_bitbang/remote_bitbang.c -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/remote_bitbang copying pythondata_cpu_cv32e40p/system_verilog/tb/dm/remote_bitbang/remote_bitbang.h -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/remote_bitbang copying pythondata_cpu_cv32e40p/system_verilog/tb/dm/remote_bitbang/sim_jtag.c -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/remote_bitbang creating build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/unused copying pythondata_cpu_cv32e40p/system_verilog/tb/dm/unused/SimDTM.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/unused creating build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/scripts copying pythondata_cpu_cv32e40p/system_verilog/tb/scripts/pulptrace -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/scripts creating build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/serDiv copying pythondata_cpu_cv32e40p/system_verilog/tb/serDiv/tb.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/serDiv copying pythondata_cpu_cv32e40p/system_verilog/tb/serDiv/tb_div.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/serDiv copying pythondata_cpu_cv32e40p/system_verilog/tb/serDiv/tb_rem.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/serDiv copying pythondata_cpu_cv32e40p/system_verilog/tb/serDiv/tb_udiv.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/serDiv copying pythondata_cpu_cv32e40p/system_verilog/tb/serDiv/tb_urem.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/serDiv creating build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/serDiv/scripts copying pythondata_cpu_cv32e40p/system_verilog/tb/serDiv/scripts/compile.sh -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/serDiv/scripts copying pythondata_cpu_cv32e40p/system_verilog/tb/serDiv/scripts/sim.sh -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/serDiv/scripts copying pythondata_cpu_cv32e40p/system_verilog/tb/serDiv/scripts/tb.do -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/serDiv/scripts copying pythondata_cpu_cv32e40p/system_verilog/tb/serDiv/scripts/tb_nogui.do -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/serDiv/scripts copying pythondata_cpu_cv32e40p/system_verilog/tb/serDiv/scripts/wave.do -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/serDiv/scripts creating build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/tb_MPU copying pythondata_cpu_cv32e40p/system_verilog/tb/tb_MPU/tb.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/tb_MPU creating build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/tb_riscv copying pythondata_cpu_cv32e40p/system_verilog/tb/tb_riscv/README.md -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/tb_riscv copying pythondata_cpu_cv32e40p/system_verilog/tb/tb_riscv/riscv_perturbation.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/tb_riscv copying pythondata_cpu_cv32e40p/system_verilog/tb/tb_riscv/riscv_random_interrupt_generator.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/tb_riscv copying pythondata_cpu_cv32e40p/system_verilog/tb/tb_riscv/riscv_random_stall.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/tb_riscv copying pythondata_cpu_cv32e40p/system_verilog/tb/tb_riscv/riscv_simchecker.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/tb_riscv copying pythondata_cpu_cv32e40p/system_verilog/tb/tb_riscv/tb_riscv_core.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/tb_riscv creating build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/tb_riscv/include copying pythondata_cpu_cv32e40p/system_verilog/tb/tb_riscv/include/perturbation_defines.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/tb_riscv/include creating build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/verilator-model copying pythondata_cpu_cv32e40p/system_verilog/tb/verilator-model/.gitignore -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/verilator-model copying pythondata_cpu_cv32e40p/system_verilog/tb/verilator-model/Makefile -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/verilator-model copying pythondata_cpu_cv32e40p/system_verilog/tb/verilator-model/README.md -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/verilator-model copying pythondata_cpu_cv32e40p/system_verilog/tb/verilator-model/dp_ram.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/verilator-model copying pythondata_cpu_cv32e40p/system_verilog/tb/verilator-model/ram.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/verilator-model copying pythondata_cpu_cv32e40p/system_verilog/tb/verilator-model/testbench.cpp -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/verilator-model copying pythondata_cpu_cv32e40p/system_verilog/tb/verilator-model/top.sv -> build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/verilator-model Executing(%install): /bin/sh -e /var/tmp/rpm-tmp.yG0O72 running install running install_lib creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12 creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/verilator-model copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/verilator-model/top.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/verilator-model copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/verilator-model/testbench.cpp -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/verilator-model copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/verilator-model/ram.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/verilator-model copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/verilator-model/dp_ram.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/verilator-model copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/verilator-model/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/verilator-model copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/verilator-model/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/verilator-model copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/verilator-model/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/verilator-model creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/tb_riscv creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/tb_riscv/include copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/tb_riscv/include/perturbation_defines.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/tb_riscv/include copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/tb_riscv/tb_riscv_core.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/tb_riscv copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/tb_riscv/riscv_simchecker.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/tb_riscv copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/tb_riscv/riscv_random_stall.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/tb_riscv copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/tb_riscv/riscv_random_interrupt_generator.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/tb_riscv copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/tb_riscv/riscv_perturbation.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/tb_riscv copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/tb_riscv/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/tb_riscv creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/tb_MPU copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/tb_MPU/tb.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/tb_MPU creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/serDiv creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/serDiv/scripts copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/serDiv/scripts/wave.do -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/serDiv/scripts copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/serDiv/scripts/tb_nogui.do -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/serDiv/scripts copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/serDiv/scripts/tb.do -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/serDiv/scripts copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/serDiv/scripts/sim.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/serDiv/scripts copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/serDiv/scripts/compile.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/serDiv/scripts copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/serDiv/tb_urem.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/serDiv copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/serDiv/tb_udiv.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/serDiv copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/serDiv/tb_rem.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/serDiv copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/serDiv/tb_div.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/serDiv copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/serDiv/tb.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/serDiv creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/scripts copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/scripts/pulptrace -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/scripts creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/dm creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/dm/unused copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/unused/SimDTM.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/dm/unused creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/dm/remote_bitbang copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/remote_bitbang/sim_jtag.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/dm/remote_bitbang copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/remote_bitbang/remote_bitbang.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/dm/remote_bitbang copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/remote_bitbang/remote_bitbang.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/dm/remote_bitbang copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/remote_bitbang/rbs_test.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/dm/remote_bitbang copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/remote_bitbang/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/dm/remote_bitbang copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/remote_bitbang/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/dm/remote_bitbang creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/dm/prog copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/prog/test.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/dm/prog copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/prog/syscalls.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/dm/prog copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/prog/start.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/dm/prog copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/prog/link.ld -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/dm/prog copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/waves.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/dm copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/vsim_gui.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/dm copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/vsim_batch.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/dm copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/tb_top_verilator.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/dm copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/tb_top_verilator.cpp -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/dm copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/tb_top.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/dm copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/tb_test_env.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/dm copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/riscv_tb_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/dm copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/pulpissimo_debug.cfg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/dm copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/pulpissimo_compliance_test.cfg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/dm copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/mm_ram.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/dm copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/dp_ram.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/dm copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/boot_rom.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/dm copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/SimJTAG.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/dm copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/dm copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/dm copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/LICENSE.SiFive -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/dm copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/LICENSE.Berkeley -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/dm copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/dm copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/dm/.clang-format -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/dm creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um/remw.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um/remuw.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um/remu.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um/rem.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um/mulw.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um/mulhu.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um/mulhsu.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um/mulh.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um/mul.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um/divw.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um/divuw.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um/divu.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um/div.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um/Makefrag -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64um creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/xori.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/xor.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/sw.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/subw.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/sub.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/srlw.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/srliw.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/srli.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/srl.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/sraw.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/sraiw.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/srai.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/sra.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/sltu.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/sltiu.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/slti.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/slt.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/sllw.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/slliw.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/slli.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/sll.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/simple.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/sh.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/sd.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/sb.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/ori.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/or.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/lwu.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/lw.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/lui.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/lhu.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/lh.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/ld.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/lbu.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/lb.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/jalr.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/jal.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/fence_i.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/bne.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/bltu.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/blt.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/bgeu.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/bge.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/beq.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/auipc.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/andi.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/and.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/addw.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/addiw.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/addi.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/add.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui/Makefrag -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ui creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf/recoding.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf/move.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf/ldst.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf/fmin.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf/fmadd.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf/fdiv.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf/fcvt_w.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf/fcvt.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf/fcmp.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf/fclass.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf/fadd.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf/Makefrag -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uf creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud/structural.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud/recoding.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud/move.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud/ldst.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud/fmin.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud/fmadd.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud/fdiv.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud/fcvt_w.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud/fcvt.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud/fcmp.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud/fclass.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud/fadd.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud/Makefrag -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ud creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uc copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uc/rvc.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uc copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uc/Makefrag -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64uc creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua/lrsc.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua/amoxor_w.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua/amoxor_d.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua/amoswap_w.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua/amoswap_d.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua/amoor_w.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua/amoor_d.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua/amominu_w.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua/amominu_d.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua/amomin_w.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua/amomin_d.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua/amomaxu_w.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua/amomaxu_d.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua/amomax_w.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua/amomax_d.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua/amoand_w.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua/amoand_d.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua/amoadd_w.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua/amoadd_d.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua/Makefrag -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64ua creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64si copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64si/wfi.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64si copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64si/scall.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64si copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64si/sbreak.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64si copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64si/ma_fetch.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64si copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64si/dirty.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64si copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64si/csr.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64si copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64si/Makefrag -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64si + RPM_EC=0 ++ jobs -p + exit 0 + umask 022 + cd /builddir/build/BUILD + '[' /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64 '!=' / ']' + rm -rf /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64 ++ dirname /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64 + mkdir -p /builddir/build/BUILDROOT + mkdir /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64 + CFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -m64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer ' + export CFLAGS + CXXFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -m64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer ' + export CXXFLAGS + FFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -m64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -I/usr/lib64/gfortran/modules ' + export FFLAGS + FCFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -m64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -I/usr/lib64/gfortran/modules ' + export FCFLAGS + VALAFLAGS=-g + export VALAFLAGS + RUSTFLAGS='-Copt-level=3 -Cdebuginfo=2 -Ccodegen-units=1 -Cforce-frame-pointers=yes -Clink-arg=-Wl,-z,relro -Clink-arg=-Wl,-z,now -Clink-arg=-specs=/usr/lib/rpm/redhat/redhat-package-notes --cap-lints=warn' + export RUSTFLAGS + LDFLAGS='-Wl,-z,relro -Wl,--as-needed -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -Wl,--build-id=sha1 -specs=/usr/lib/rpm/redhat/redhat-package-notes ' + export LDFLAGS + LT_SYS_LIBRARY_PATH=/usr/lib64: + export LT_SYS_LIBRARY_PATH + CC=gcc + export CC + CXX=g++ + export CXX + cd litex-pythondata-cpu-cv32e40p + CFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -m64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer ' + LDFLAGS='-Wl,-z,relro -Wl,--as-needed -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -Wl,--build-id=sha1 -specs=/usr/lib/rpm/redhat/redhat-package-notes ' + /usr/bin/python3 setup.py install -O1 --skip-build --root /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64 --prefix /usr /usr/lib/python3.12/site-packages/setuptools/_distutils/cmd.py:66: SetuptoolsDeprecationWarning: setup.py install is deprecated. !! ******************************************************************************** Please avoid running ``setup.py`` directly. Instead, use pypa/build, pypa/installer, pypa/build or other standards-based tools. Follow the current Python packaging guidelines when building Python RPM packages. See https://blog.ganssle.io/articles/2021/10/setup-py-deprecated.html and https://docs.fedoraproject.org/en-US/packaging-guidelines/Python/ for details. ******************************************************************************** !! self.initialize_options() creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64mi copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64mi/scall.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64mi copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64mi/sbreak.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64mi copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64mi/mcsr.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64mi copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64mi/ma_fetch.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64mi copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64mi/ma_addr.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64mi copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64mi/illegal.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64mi copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64mi/csr.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64mi copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64mi/breakpoint.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64mi copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64mi/access.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64mi copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64mi/Makefrag -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv64mi creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32um copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32um/remu.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32um copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32um/rem.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32um copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32um/mulhu.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32um copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32um/mulhsu.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32um copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32um/mulh.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32um copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32um/mul.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32um copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32um/divu.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32um copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32um/div.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32um copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32um/Makefrag -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32um creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/xori.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/xor.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/sw.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/sub.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/srli.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/srl.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/srai.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/sra.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/sltu.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/sltiu.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/slti.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/slt.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/slli.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/sll.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/simple.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/sh.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/sb.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/ori.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/or.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/lw.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/lui.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/lhu.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/lh.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/lbu.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/lb.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/jalr.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/jal.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/fence_i.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/bne.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/bltu.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/blt.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/bgeu.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/bge.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/beq.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/auipc.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/andi.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/and.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/addi.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/add.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui/Makefrag -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ui creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf/recoding.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf/move.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf/ldst.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf/fmin.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf/fmadd.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf/fdiv.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf/fcvt_w.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf/fcvt.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf/fcmp.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf/fclass.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf/fadd.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf/Makefrag -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uf creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud/recoding.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud/move.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud/ldst.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud/fmin.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud/fmadd.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud/fdiv.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud/fcvt_w.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud/fcvt.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud/fcmp.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud/fclass.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud/fadd.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud/Makefrag -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ud creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uc copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uc/rvc.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uc copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uc/Makefrag -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32uc creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua/lrsc.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua/amoxor_w.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua/amoswap_w.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua/amoor_w.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua/amominu_w.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua/amomin_w.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua/amomaxu_w.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua/amomax_w.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua/amoand_w.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua/amoadd_w.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua/Makefrag -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32ua creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32si copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32si/wfi.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32si copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32si/scall.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32si copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32si/sbreak.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32si copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32si/ma_fetch.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32si copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32si/dirty.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32si copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32si/csr.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32si copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32si/Makefrag -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32si creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32mi copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32mi/shamt.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32mi copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32mi/scall.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32mi copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32mi/sbreak.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32mi copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32mi/mcsr.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32mi copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32mi/ma_fetch.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32mi copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32mi/ma_addr.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32mi copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32mi/illegal.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32mi copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32mi/csr.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32mi copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32mi/breakpoint.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32mi copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32mi/Makefrag -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/rv32mi creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/macros creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/macros/scalar copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/macros/scalar/test_macros.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/macros/scalar copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/riscv_test.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests/LICENSE -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_tests creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/disabled copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/disabled/I-SH-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/disabled copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/disabled/I-SB-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/disabled copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/disabled/I-MISALIGN_LDST-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/disabled copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/disabled/I-MISALIGN_JMP-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/disabled copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/disabled/I-FENCE.I-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/disabled copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/test_macros.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/riscv_test.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/compliance_test.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/compliance_io.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/aw_test_macros.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-XORI-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-XOR-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-SW-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-SUB-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-SRLI-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-SRL-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-SRAI-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-SRA-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-SLTU-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-SLTIU-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-SLTI-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-SLT-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-SLLI-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-SLL-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-RF_x0-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-RF_width-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-RF_size-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-ORI-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-OR-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-NOP-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-LW-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-LUI-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-LHU-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-LH-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-LBU-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-LB-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-JALR-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-JAL-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-IO.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-FENCE.I-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-ENDIANESS-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-ECALL-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-EBREAK-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-DELAY_SLOTS-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-CSRRWI-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-CSRRW-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-CSRRSI-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-CSRRS-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-CSRRCI-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-CSRRC-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-BNE-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-BLTU-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-BLT-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-BGEU-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-BGE-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-BEQ-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-AUIPC-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-ANDI-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-AND-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-ADDI-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests/I-ADD-01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_compliance_tests creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/interrupt_test copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/interrupt_test/vectors.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/interrupt_test copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/interrupt_test/matrix.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/interrupt_test copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/interrupt_test/isr.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/interrupt_test copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/interrupt_test/interrupt_test.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/interrupt_test creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware/stats.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware/start.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware/sieve.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware/riscv.ld.orig -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware/riscv.ld -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware/print.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware/multest.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware/makehex.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware/link.ld -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware/firmware.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware/README -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/custom_fp copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/custom_fp/matmulNxN.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/custom_fp copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/custom_fp/main.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/custom_fp creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/custom copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/custom/vectors.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/custom copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/custom/syscalls.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/custom copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/custom/link.ld -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/custom copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/custom/hello_world.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/custom copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/custom/crt0.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/custom creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/csmith copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/csmith/syscalls.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/csmith copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/csmith/start.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/csmith copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/csmith/riscv-isa-sim.diff -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/csmith copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/csmith/link.ld -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/csmith copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/csmith/license_notes -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/csmith copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/waves.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/vsim.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/tb_top_verilator.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/tb_top_verilator.cpp -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/tb_top.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/software.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/riscv_wrapper.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/mm_ram.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/dp_ram.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/amo_shim.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core copying build/lib/pythondata_cpu_cv32e40p/system_verilog/tb/core/.clang-format -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/include copying build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl/include/riscv_tracer_defines.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/include copying build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl/include/riscv_defines.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/include copying build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl/include/riscv_config.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/include copying build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl/include/apu_macros.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/include copying build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl/include/apu_core_package.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/include copying build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_tracer.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_register_file_latch.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_register_file.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_prefetch_buffer.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_prefetch_L0_buffer.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_pmp.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_mult.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_load_store_unit.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_int_controller.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_if_stage.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_id_stage.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_hwloop_regs.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_hwloop_controller.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_fetch_fifo.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_ex_stage.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_decoder.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_cs_registers.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_core.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_controller.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_compressed_decoder.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_apu_disp.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_alu_div.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_alu.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_L0_buffer.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl/register_file_test_wrap.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e40p/system_verilog/rtl/cv32e40p_sim_clock_gate.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/pd copying build/lib/pythondata_cpu_cv32e40p/system_verilog/pd/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/pd creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/doc copying build/lib/pythondata_cpu_cv32e40p/system_verilog/doc/user_manual.doc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/doc copying build/lib/pythondata_cpu_cv32e40p/system_verilog/doc/SECURED_RI5CY_DEBUG_reference.xlsx -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/doc copying build/lib/pythondata_cpu_cv32e40p/system_verilog/doc/NONSECURED_RI5CY_DEBUG_reference.xlsx -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/doc creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/ci copying build/lib/pythondata_cpu_cv32e40p/system_verilog/ci/veri-run-openocd-compliance.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/ci copying build/lib/pythondata_cpu_cv32e40p/system_verilog/ci/rv32tests-to-junit.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/ci copying build/lib/pythondata_cpu_cv32e40p/system_verilog/ci/run-openocd-compliance.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/ci copying build/lib/pythondata_cpu_cv32e40p/system_verilog/ci/openocd-to-junit.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/ci copying build/lib/pythondata_cpu_cv32e40p/system_verilog/ci/make-tmp.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/ci copying build/lib/pythondata_cpu_cv32e40p/system_verilog/ci/install-verilator.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/ci copying build/lib/pythondata_cpu_cv32e40p/system_verilog/ci/get-openocd.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/ci copying build/lib/pythondata_cpu_cv32e40p/system_verilog/ci/download-pulp-gcc.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/ci copying build/lib/pythondata_cpu_cv32e40p/system_verilog/ci/build-riscv-gcc.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/ci copying build/lib/pythondata_cpu_cv32e40p/system_verilog/ci/Jenkinsfile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/ci copying build/lib/pythondata_cpu_cv32e40p/system_verilog/src_files.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog copying build/lib/pythondata_cpu_cv32e40p/system_verilog/cv32e40p_trace_manifest.flist -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog copying build/lib/pythondata_cpu_cv32e40p/system_verilog/cv32e40p_manifest.flist -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog copying build/lib/pythondata_cpu_cv32e40p/system_verilog/cv32e40p_fpu_manifest.flist -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog copying build/lib/pythondata_cpu_cv32e40p/system_verilog/cv32e40p_dm_manifest.flist -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog copying build/lib/pythondata_cpu_cv32e40p/system_verilog/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog copying build/lib/pythondata_cpu_cv32e40p/system_verilog/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog copying build/lib/pythondata_cpu_cv32e40p/system_verilog/LICENSE -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog copying build/lib/pythondata_cpu_cv32e40p/system_verilog/CONTRIBUTING.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog copying build/lib/pythondata_cpu_cv32e40p/system_verilog/Bender.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog copying build/lib/pythondata_cpu_cv32e40p/system_verilog/.travis.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog copying build/lib/pythondata_cpu_cv32e40p/system_verilog/.gitmodules -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog copying build/lib/pythondata_cpu_cv32e40p/system_verilog/.gitlab-ci.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog copying build/lib/pythondata_cpu_cv32e40p/system_verilog/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog copying build/lib/pythondata_cpu_cv32e40p/system_verilog/.dir-locals.el -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog copying build/lib/pythondata_cpu_cv32e40p/__init__.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/core/firmware/makehex.py to makehex.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/ci/rv32tests-to-junit.py to rv32tests-to-junit.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/ci/openocd-to-junit.py to openocd-to-junit.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/__init__.py to __init__.cpython-312.pyc writing byte-compilation script '/tmp/tmp2v3uxmvn.py' /usr/bin/python3 /tmp/tmp2v3uxmvn.py removing /tmp/tmp2v3uxmvn.py running install_egg_info running egg_info writing pythondata_cpu_cv32e40p.egg-info/PKG-INFO writing dependency_links to pythondata_cpu_cv32e40p.egg-info/dependency_links.txt writing top-level names to pythondata_cpu_cv32e40p.egg-info/top_level.txt reading manifest file 'pythondata_cpu_cv32e40p.egg-info/SOURCES.txt' reading manifest template 'MANIFEST.in' adding license file 'LICENSE' writing manifest file 'pythondata_cpu_cv32e40p.egg-info/SOURCES.txt' Copying pythondata_cpu_cv32e40p.egg-info to /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p-0.0.post152-py3.12.egg-info running install_scripts warning: no previously-included files matching '*.py[cod]' found anywhere in distribution + rm -rfv /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/bin/__pycache__ + /usr/lib/rpm/check-buildroot + /usr/lib/rpm/redhat/brp-ldconfig + /usr/lib/rpm/brp-compress + /usr/lib/rpm/brp-strip /bin/true + /usr/lib/rpm/brp-strip-comment-note /bin/true /usr/bin/objdump + /usr/lib/rpm/redhat/brp-strip-lto /bin/true + /usr/lib/rpm/brp-strip-static-archive /bin/true + /usr/lib/rpm/check-rpaths + /usr/lib/rpm/redhat/brp-mangle-shebangs mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/ci/build-riscv-gcc.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/ci/download-pulp-gcc.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/ci/get-openocd.sh from /usr/bin/env bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/ci/install-verilator.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/ci/make-tmp.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/ci/openocd-to-junit.py from /usr/bin/env python3 to #!/usr/bin/python3 mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/ci/run-openocd-compliance.sh from /usr/bin/env bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/ci/rv32tests-to-junit.py from /usr/bin/env python3 to #!/usr/bin/python3 mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/ci/veri-run-openocd-compliance.sh from /usr/bin/env bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/scripts/pulptrace from /usr/bin/env python3 to #!/usr/bin/python3 mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/serDiv/scripts/compile.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/tb/serDiv/scripts/sim.sh from /bin/bash to #!/usr/bin/bash + /usr/lib/rpm/brp-remove-la-files + env /usr/lib/rpm/redhat/brp-python-bytecompile '' 1 0 -j2 Bytecompiling .py files below /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/lib/python3.12 using python3.12 + /usr/lib/rpm/redhat/brp-python-hardlink Processing files: litex-pythondata-cpu-cv32e40p-python3-2022.08-20220530.3.gitc897dc0a.fc39.noarch Executing(%doc): /bin/sh -e /var/tmp/rpm-tmp.NX209a + umask 022 + cd /builddir/build/BUILD + cd litex-pythondata-cpu-cv32e40p + DOCDIR=/builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/share/doc/litex-pythondata-cpu-cv32e40p-python3 + export LC_ALL=C + LC_ALL=C + export DOCDIR + /usr/bin/mkdir -p /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/share/doc/litex-pythondata-cpu-cv32e40p-python3 + cp -pr /builddir/build/BUILD/litex-pythondata-cpu-cv32e40p/README.md /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/share/doc/litex-pythondata-cpu-cv32e40p-python3 + RPM_EC=0 ++ jobs -p + exit 0 Executing(%license): /bin/sh -e /var/tmp/rpm-tmp.EmyWzH + umask 022 + cd /builddir/build/BUILD + cd litex-pythondata-cpu-cv32e40p + LICENSEDIR=/builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/share/licenses/litex-pythondata-cpu-cv32e40p-python3 + export LC_ALL=C + LC_ALL=C + export LICENSEDIR + /usr/bin/mkdir -p /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/share/licenses/litex-pythondata-cpu-cv32e40p-python3 + cp -pr /builddir/build/BUILD/litex-pythondata-cpu-cv32e40p/LICENSE /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64/usr/share/licenses/litex-pythondata-cpu-cv32e40p-python3 + RPM_EC=0 ++ jobs -p + exit 0 Provides: litex-pythondata-cpu-cv32e40p-python3 = 2022.08-20220530.3.gitc897dc0a.fc39 python3.12dist(pythondata-cpu-cv32e40p) = 0^post152 python3dist(pythondata-cpu-cv32e40p) = 0^post152 pythondata-cpu-cv32e40p Requires(rpmlib): rpmlib(CompressedFileNames) <= 3.0.4-1 rpmlib(FileDigests) <= 4.6.0-1 rpmlib(PartialHardlinkSets) <= 4.0.4-1 rpmlib(PayloadFilesHavePrefix) <= 4.0-1 Requires: /usr/bin/bash /usr/bin/python3 python(abi) = 3.12 Checking for unpackaged file(s): /usr/lib/rpm/check-files /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64 Wrote: /builddir/build/RPMS/litex-pythondata-cpu-cv32e40p-python3-2022.08-20220530.3.gitc897dc0a.fc39.noarch.rpm Executing(%clean): /bin/sh -e /var/tmp/rpm-tmp.1ZZ8zu + umask 022 + cd /builddir/build/BUILD + cd litex-pythondata-cpu-cv32e40p + /usr/bin/rm -rf /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e40p-2022.08-20220530.3.gitc897dc0a.fc39.x86_64 + RPM_EC=0 ++ jobs -p + exit 0 Executing(rmbuild): /bin/sh -e /var/tmp/rpm-tmp.U2zPue + umask 022 + cd /builddir/build/BUILD + rm -rf litex-pythondata-cpu-cv32e40p litex-pythondata-cpu-cv32e40p.gemspec + RPM_EC=0 ++ jobs -p + exit 0 Child return code was: 0