Warning: Permanently added '13.218.120.70' (ED25519) to the list of known hosts.
Running (timeout=172800): unbuffer mock --spec /var/lib/copr-rpmbuild/workspace/workdir-almc4me2/litex-pythondata-cpu-cva6/litex-pythondata-cpu-cva6.spec --sources /var/lib/copr-rpmbuild/workspace/workdir-almc4me2/litex-pythondata-cpu-cva6 --resultdir /var/lib/copr-rpmbuild/results --uniqueext 1778795171.515428 -r /var/lib/copr-rpmbuild/results/configs/child.cfg
INFO: mock.py version 6.7 starting (python version = 3.14.2, NVR = mock-6.7-1.fc43), args: /usr/libexec/mock/mock --spec /var/lib/copr-rpmbuild/workspace/workdir-almc4me2/litex-pythondata-cpu-cva6/litex-pythondata-cpu-cva6.spec --sources /var/lib/copr-rpmbuild/workspace/workdir-almc4me2/litex-pythondata-cpu-cva6 --resultdir /var/lib/copr-rpmbuild/results --uniqueext 1778795171.515428 -r /var/lib/copr-rpmbuild/results/configs/child.cfg
Start(bootstrap): init plugins
INFO: tmpfs initialized
INFO: selinux enabled
INFO: chroot_scan: initialized
INFO: compress_logs: initialized
Finish(bootstrap): init plugins
Start: init plugins
INFO: tmpfs initialized
INFO: selinux enabled
INFO: chroot_scan: initialized
INFO: compress_logs: initialized
Finish: init plugins
INFO: Signal handler active
Start: run
INFO: Start(/var/lib/copr-rpmbuild/workspace/workdir-almc4me2/litex-pythondata-cpu-cva6/litex-pythondata-cpu-cva6.spec)  Config(fedora-42-aarch64)
Start: clean chroot
Finish: clean chroot
Mock Version: 6.7
INFO: Mock Version: 6.7
Start(bootstrap): chroot init
INFO: mounting tmpfs at /var/lib/mock/fedora-42-aarch64-bootstrap-1778795171.515428/root.
INFO: calling preinit hooks
INFO: enabled root cache
INFO: enabled package manager cache
Start(bootstrap): cleaning package manager metadata
Finish(bootstrap): cleaning package manager metadata
INFO: Guessed host environment type: unknown
INFO: Using container image: registry.fedoraproject.org/fedora:42
INFO: Pulling image: registry.fedoraproject.org/fedora:42
INFO: Tagging container image as mock-bootstrap-4da599c7-d22f-467c-8ba7-d36f09f0ab2f
INFO: Checking that afe88eac7a2cbe723a96a0a01b4c7bc0ce9d39508833ed61bd3c153366357a56 image matches host's architecture
INFO: Copy content of container afe88eac7a2cbe723a96a0a01b4c7bc0ce9d39508833ed61bd3c153366357a56 to /var/lib/mock/fedora-42-aarch64-bootstrap-1778795171.515428/root
INFO: mounting afe88eac7a2cbe723a96a0a01b4c7bc0ce9d39508833ed61bd3c153366357a56 with podman image mount
INFO: image afe88eac7a2cbe723a96a0a01b4c7bc0ce9d39508833ed61bd3c153366357a56 as /var/lib/containers/storage/overlay/aa5aaeaf2c253a26dc5990619ca94621eafab09a274e91c137aead0806619e41/merged
INFO: umounting image afe88eac7a2cbe723a96a0a01b4c7bc0ce9d39508833ed61bd3c153366357a56 (/var/lib/containers/storage/overlay/aa5aaeaf2c253a26dc5990619ca94621eafab09a274e91c137aead0806619e41/merged) with podman image umount
INFO: Removing image mock-bootstrap-4da599c7-d22f-467c-8ba7-d36f09f0ab2f
INFO: Package manager dnf5 detected and used (fallback)
INFO: Not updating bootstrap chroot, bootstrap_image_ready=True
Start(bootstrap): creating root cache
Finish(bootstrap): creating root cache
Finish(bootstrap): chroot init
Start: chroot init
INFO: mounting tmpfs at /var/lib/mock/fedora-42-aarch64-1778795171.515428/root.
INFO: calling preinit hooks
INFO: enabled root cache
INFO: enabled package manager cache
Start: cleaning package manager metadata
Finish: cleaning package manager metadata
INFO: enabled HW Info plugin
INFO: Package manager dnf5 detected and used (direct choice)
INFO: Buildroot is handled by package management downloaded with a bootstrap image:
  rpm-4.20.1-1.fc42.aarch64
  rpm-sequoia-1.10.1-1.fc42.aarch64
  dnf5-5.2.18.0-3.fc42.aarch64
  dnf5-plugins-5.2.18.0-3.fc42.aarch64
Start: installing minimal buildroot with dnf5
Updating and loading repositories:
 Copr repository                        100% | 412.8 KiB/s | 132.1 KiB |  00m00s
 updates                                100% |  28.9 MiB/s |  32.4 MiB |  00m01s
 fedora                                 100% |  13.9 MiB/s |  34.2 MiB |  00m02s
Repositories loaded.
Package                            Arch    Version                     Repository      Size
Installing group/module packages:
 bash                              aarch64 5.2.37-1.fc42               fedora       8.2 MiB
 bzip2                             aarch64 1.0.8-20.fc42               fedora     171.3 KiB
 coreutils                         aarch64 9.6-8.fc42                  updates      8.2 MiB
 cpio                              aarch64 2.15-4.fc42                 fedora       1.1 MiB
 diffutils                         aarch64 3.12-1.fc42                 updates      1.6 MiB
 fedora-release-common             noarch  42-30                       updates     20.2 KiB
 findutils                         aarch64 1:4.10.0-5.fc42             fedora       1.9 MiB
 gawk                              aarch64 5.3.1-1.fc42                fedora       2.4 MiB
 glibc-minimal-langpack            aarch64 2.41-18.fc42                updates      0.0   B
 grep                              aarch64 3.11-10.fc42                fedora       1.0 MiB
 gzip                              aarch64 1.13-3.fc42                 fedora     424.7 KiB
 info                              aarch64 7.2-3.fc42                  fedora     421.6 KiB
 patch                             aarch64 2.8-1.fc42                  updates    262.5 KiB
 redhat-rpm-config                 noarch  342-4.fc42                  updates    185.5 KiB
 rpm-build                         aarch64 4.20.1-1.fc42               fedora     524.4 KiB
 sed                               aarch64 4.9-4.fc42                  fedora     873.2 KiB
 shadow-utils                      aarch64 2:4.17.4-1.fc42             fedora       4.5 MiB
 tar                               aarch64 2:1.35-5.fc42               fedora       3.0 MiB
 unzip                             aarch64 6.0-66.fc42                 fedora     470.2 KiB
 util-linux                        aarch64 2.40.4-10.fc42              updates      6.6 MiB
 which                             aarch64 2.23-2.fc42                 updates    123.4 KiB
 xz                                aarch64 1:5.8.1-4.fc42              updates      1.4 MiB
Installing dependencies:
 add-determinism                   aarch64 0.6.0-3.fc42                updates      2.1 MiB
 alternatives                      aarch64 1.33-3.fc42                 updates     90.2 KiB
 ansible-srpm-macros               noarch  1-17.1.fc42                 fedora      35.7 KiB
 audit-libs                        aarch64 4.1.4-1.fc42                updates    486.9 KiB
 basesystem                        noarch  11-22.fc42                  fedora       0.0   B
 binutils                          aarch64 2.44-12.fc42                updates     29.3 MiB
 build-reproducibility-srpm-macros noarch  0.6.0-3.fc42                updates    735.0   B
 bzip2-libs                        aarch64 1.0.8-20.fc42               fedora      72.6 KiB
 ca-certificates                   noarch  2025.2.80_v9.0.304-1.1.fc42 updates      2.7 MiB
 coreutils-common                  aarch64 9.6-8.fc42                  updates     11.1 MiB
 crypto-policies                   noarch  20251125-1.git3839d0e.fc42  updates    143.1 KiB
 curl                              aarch64 8.11.1-8.fc42               updates    454.7 KiB
 cyrus-sasl-lib                    aarch64 2.1.28-30.fc42              fedora       2.4 MiB
 debugedit                         aarch64 5.1-7.fc42                  updates    244.6 KiB
 dwz                               aarch64 0.16-1.fc42                 updates    322.6 KiB
 ed                                aarch64 1.21-2.fc42                 fedora     154.5 KiB
 efi-srpm-macros                   noarch  6-3.fc42                    updates     40.1 KiB
 elfutils                          aarch64 0.195-1.fc42                updates      3.6 MiB
 elfutils-debuginfod-client        aarch64 0.195-1.fc42                updates    144.0 KiB
 elfutils-default-yama-scope       noarch  0.195-1.fc42                updates      1.8 KiB
 elfutils-libelf                   aarch64 0.195-1.fc42                updates      1.2 MiB
 elfutils-libs                     aarch64 0.195-1.fc42                updates    746.7 KiB
 fedora-gpg-keys                   noarch  42-1                        fedora     128.2 KiB
 fedora-release                    noarch  42-30                       updates      0.0   B
 fedora-release-identity-basic     noarch  42-30                       updates    646.0   B
 fedora-repos                      noarch  42-1                        fedora       4.9 KiB
 file                              aarch64 5.46-3.fc42                 updates    140.2 KiB
 file-libs                         aarch64 5.46-3.fc42                 updates     11.9 MiB
 filesystem                        aarch64 3.18-47.fc42                updates    112.0   B
 filesystem-srpm-macros            noarch  3.18-47.fc42                updates     38.2 KiB
 fonts-srpm-macros                 noarch  1:2.0.5-22.fc42             updates     55.8 KiB
 forge-srpm-macros                 noarch  0.4.0-2.fc42                fedora      38.9 KiB
 fpc-srpm-macros                   noarch  1.3-14.fc42                 fedora     144.0   B
 gdb-minimal                       aarch64 17.1-1.fc42                 updates     13.4 MiB
 gdbm-libs                         aarch64 1:1.23-9.fc42               fedora     234.0 KiB
 ghc-srpm-macros                   noarch  1.9.2-2.fc42                fedora     779.0   B
 glibc                             aarch64 2.41-18.fc42                updates      6.2 MiB
 glibc-common                      aarch64 2.41-18.fc42                updates      1.3 MiB
 glibc-gconv-extra                 aarch64 2.41-18.fc42                updates     18.6 MiB
 gmp                               aarch64 1:6.3.0-4.fc42              fedora     657.9 KiB
 gnat-srpm-macros                  noarch  6-7.fc42                    fedora       1.0 KiB
 gnulib-l10n                       noarch  20241231-1.fc42             updates    655.0 KiB
 go-srpm-macros                    noarch  3.8.0-1.fc42                updates     61.9 KiB
 jansson                           aarch64 2.14-2.fc42                 fedora      93.2 KiB
 json-c                            aarch64 0.18-2.fc42                 fedora     138.7 KiB
 kernel-srpm-macros                noarch  1.0-25.fc42                 fedora       1.9 KiB
 keyutils-libs                     aarch64 1.6.3-5.fc42                fedora      98.3 KiB
 krb5-libs                         aarch64 1.21.3-7.fc42               updates      2.5 MiB
 libacl                            aarch64 2.3.2-3.fc42                fedora      66.3 KiB
 libarchive                        aarch64 3.8.1-1.fc42                updates    975.0 KiB
 libattr                           aarch64 2.5.2-5.fc42                fedora      67.1 KiB
 libblkid                          aarch64 2.40.4-10.fc42              updates    290.5 KiB
 libbrotli                         aarch64 1.2.0-1.fc42                updates    909.5 KiB
 libcap                            aarch64 2.73-3.fc42                 updates    506.8 KiB
 libcap-ng                         aarch64 0.9.3-1.fc42                updates    161.1 KiB
 libcom_err                        aarch64 1.47.2-3.fc42               fedora     111.2 KiB
 libcurl                           aarch64 8.11.1-8.fc42               updates    794.0 KiB
 libeconf                          aarch64 0.7.6-2.fc42                updates     80.6 KiB
 libevent                          aarch64 2.1.12-15.fc42              fedora       1.1 MiB
 libfdisk                          aarch64 2.40.4-10.fc42              updates    418.8 KiB
 libffi                            aarch64 3.4.6-5.fc42                fedora     154.4 KiB
 libgcc                            aarch64 15.2.1-7.fc42               updates    222.2 KiB
 libgomp                           aarch64 15.2.1-7.fc42               updates    517.0 KiB
 libidn2                           aarch64 2.3.8-1.fc42                fedora     560.6 KiB
 libmount                          aarch64 2.40.4-10.fc42              updates    355.8 KiB
 libnghttp2                        aarch64 1.64.0-3.fc42               fedora     198.1 KiB
 libpkgconf                        aarch64 2.3.0-2.fc42                fedora     134.0 KiB
 libpsl                            aarch64 0.21.5-5.fc42               fedora     132.5 KiB
 libselinux                        aarch64 3.8-3.fc42                  updates    201.1 KiB
 libsemanage                       aarch64 3.8.1-2.fc42                updates    360.0 KiB
 libsepol                          aarch64 3.8-1.fc42                  fedora     809.9 KiB
 libsmartcols                      aarch64 2.40.4-10.fc42              updates    224.4 KiB
 libssh                            aarch64 0.11.4-1.fc42               updates    587.7 KiB
 libssh-config                     noarch  0.11.4-1.fc42               updates    277.0   B
 libstdc++                         aarch64 15.2.1-7.fc42               updates      2.8 MiB
 libtasn1                          aarch64 4.20.0-1.fc42               fedora     220.3 KiB
 libtool-ltdl                      aarch64 2.5.4-4.fc42                fedora      94.0 KiB
 libunistring                      aarch64 1.1-9.fc42                  fedora       1.7 MiB
 libuuid                           aarch64 2.40.4-10.fc42              updates     69.4 KiB
 libverto                          aarch64 0.3.2-10.fc42               fedora      69.4 KiB
 libxcrypt                         aarch64 4.5.2-1.fc42                updates    273.4 KiB
 libxml2                           aarch64 2.12.10-1.fc42              fedora       1.9 MiB
 libzstd                           aarch64 1.5.7-1.fc42                fedora     667.7 KiB
 lua-libs                          aarch64 5.4.8-4.fc42                updates    329.9 KiB
 lua-srpm-macros                   noarch  1-15.fc42                   fedora       1.3 KiB
 lz4-libs                          aarch64 1.10.0-2.fc42               fedora     197.4 KiB
 mpfr                              aarch64 4.2.2-1.fc42                fedora     755.6 KiB
 ncurses-base                      noarch  6.5-5.20250125.fc42         fedora     326.8 KiB
 ncurses-libs                      aarch64 6.5-5.20250125.fc42         fedora       1.2 MiB
 ocaml-srpm-macros                 noarch  10-4.fc42                   fedora       1.9 KiB
 openblas-srpm-macros              noarch  2-19.fc42                   fedora     112.0   B
 openldap                          aarch64 2.6.13-1.fc42               updates    764.3 KiB
 openssl-libs                      aarch64 1:3.2.6-4.fc42              updates      6.3 MiB
 p11-kit                           aarch64 0.26.2-1.fc42               updates      2.7 MiB
 p11-kit-trust                     aarch64 0.26.2-1.fc42               updates    530.3 KiB
 package-notes-srpm-macros         noarch  0.5-13.fc42                 fedora       1.6 KiB
 pam-libs                          aarch64 1.7.0-7.fc42                updates    222.9 KiB
 pcre2                             aarch64 10.46-1.fc42                updates    713.6 KiB
 pcre2-syntax                      noarch  10.46-1.fc42                updates    275.3 KiB
 perl-srpm-macros                  noarch  1-57.fc42                   fedora     861.0   B
 pkgconf                           aarch64 2.3.0-2.fc42                fedora     112.4 KiB
 pkgconf-m4                        noarch  2.3.0-2.fc42                fedora      14.4 KiB
 pkgconf-pkg-config                aarch64 2.3.0-2.fc42                fedora     990.0   B
 popt                              aarch64 1.19-8.fc42                 fedora     144.8 KiB
 publicsuffix-list-dafsa           noarch  20260116-1.fc42             updates     70.4 KiB
 pyproject-srpm-macros             noarch  1.19.0-1.fc42               updates      1.9 KiB
 python-srpm-macros                noarch  3.13-5.fc42                 updates     51.0 KiB
 qt5-srpm-macros                   noarch  5.15.18-1.fc42              updates    500.0   B
 qt6-srpm-macros                   noarch  6.10.2-1.fc42               updates    472.0   B
 readline                          aarch64 8.2-13.fc42                 fedora     561.0 KiB
 rpm                               aarch64 4.20.1-1.fc42               fedora       3.3 MiB
 rpm-build-libs                    aarch64 4.20.1-1.fc42               fedora     198.6 KiB
 rpm-libs                          aarch64 4.20.1-1.fc42               fedora     733.5 KiB
 rpm-sequoia                       aarch64 1.10.1-1.fc42               updates      2.2 MiB
 rust-srpm-macros                  noarch  28.4-1.fc42                 updates      5.5 KiB
 setup                             noarch  2.15.0-13.fc42              fedora     720.9 KiB
 sqlite-libs                       aarch64 3.47.2-5.fc42               updates      1.5 MiB
 systemd-libs                      aarch64 257.13-1.fc42               updates      2.3 MiB
 systemd-standalone-sysusers       aarch64 257.13-1.fc42               updates    329.4 KiB
 tree-sitter-srpm-macros           noarch  0.1.0-8.fc42                fedora       6.5 KiB
 util-linux-core                   aarch64 2.40.4-10.fc42              updates      2.4 MiB
 xxhash-libs                       aarch64 0.8.3-2.fc42                fedora      85.9 KiB
 xz-libs                           aarch64 1:5.8.1-4.fc42              updates    201.5 KiB
 zig-srpm-macros                   noarch  1-4.fc42                    fedora       1.1 KiB
 zip                               aarch64 3.0-43.fc42                 fedora     762.5 KiB
 zlib-ng-compat                    aarch64 2.2.5-2.fc42                updates    133.4 KiB
 zstd                              aarch64 1.5.7-1.fc42                fedora       1.5 MiB
Installing groups:
 Buildsystem building group                                                                

Transaction Summary:
 Installing:       149 packages

Total size of inbound packages is 51 MiB. Need to download 51 MiB.
After this operation, 204 MiB extra will be used (install 204 MiB, remove 0 B).
[  1/149] bzip2-0:1.0.8-20.fc42.aarch64 100% | 122.0 KiB/s |  52.0 KiB |  00m00s
[  2/149] cpio-0:2.15-4.fc42.aarch64    100% | 528.3 KiB/s | 291.1 KiB |  00m01s
[  3/149] bash-0:5.2.37-1.fc42.aarch64  100% |   2.3 MiB/s |   1.8 MiB |  00m01s
[  4/149] findutils-1:4.10.0-5.fc42.aar 100% |   1.4 MiB/s | 554.3 KiB |  00m00s
[  5/149] grep-0:3.11-10.fc42.aarch64   100% |   2.6 MiB/s | 296.5 KiB |  00m00s
[  6/149] gawk-0:5.3.1-1.fc42.aarch64   100% |   3.1 MiB/s |   1.1 MiB |  00m00s
[  7/149] gzip-0:1.13-3.fc42.aarch64    100% |   1.1 MiB/s | 168.1 KiB |  00m00s
[  8/149] rpm-build-0:4.20.1-1.fc42.aar 100% | 667.1 KiB/s |  82.7 KiB |  00m00s
[  9/149] info-0:7.2-3.fc42.aarch64     100% |   1.3 MiB/s | 179.5 KiB |  00m00s
[ 10/149] sed-0:4.9-4.fc42.aarch64      100% |   2.0 MiB/s | 314.8 KiB |  00m00s
[ 11/149] unzip-0:6.0-66.fc42.aarch64   100% |   1.1 MiB/s | 183.0 KiB |  00m00s
[ 12/149] shadow-utils-2:4.17.4-1.fc42. 100% |   5.2 MiB/s |   1.3 MiB |  00m00s
[ 13/149] tar-2:1.35-5.fc42.aarch64     100% |   3.3 MiB/s | 853.0 KiB |  00m00s
[ 14/149] fedora-release-common-0:42-30 100% | 499.8 KiB/s |  24.5 KiB |  00m00s
[ 15/149] glibc-minimal-langpack-0:2.41 100% |   1.6 MiB/s |  63.9 KiB |  00m00s
[ 16/149] diffutils-0:3.12-1.fc42.aarch 100% |   2.9 MiB/s | 390.5 KiB |  00m00s
[ 17/149] patch-0:2.8-1.fc42.aarch64    100% |   2.3 MiB/s | 111.7 KiB |  00m00s
[ 18/149] coreutils-0:9.6-8.fc42.aarch6 100% |   7.3 MiB/s |   1.1 MiB |  00m00s
[ 19/149] redhat-rpm-config-0:342-4.fc4 100% |   2.8 MiB/s |  81.1 KiB |  00m00s
[ 20/149] which-0:2.23-2.fc42.aarch64   100% |   1.3 MiB/s |  41.4 KiB |  00m00s
[ 21/149] xz-1:5.8.1-4.fc42.aarch64     100% |  15.6 MiB/s | 573.5 KiB |  00m00s
[ 22/149] util-linux-0:2.40.4-10.fc42.a 100% |  12.8 MiB/s |   1.1 MiB |  00m00s
[ 23/149] ncurses-libs-0:6.5-5.20250125 100% |   2.4 MiB/s | 324.2 KiB |  00m00s
[ 24/149] bzip2-libs-0:1.0.8-20.fc42.aa 100% | 340.2 KiB/s |  41.2 KiB |  00m00s
[ 25/149] gmp-1:6.3.0-4.fc42.aarch64    100% |   2.6 MiB/s | 272.4 KiB |  00m00s
[ 26/149] mpfr-0:4.2.2-1.fc42.aarch64   100% |   3.5 MiB/s | 322.3 KiB |  00m00s
[ 27/149] pkgconf-pkg-config-0:2.3.0-2. 100% | 105.3 KiB/s |   9.9 KiB |  00m00s
[ 28/149] readline-0:8.2-13.fc42.aarch6 100% |   1.7 MiB/s | 211.7 KiB |  00m00s
[ 29/149] popt-0:1.19-8.fc42.aarch64    100% | 419.5 KiB/s |  65.4 KiB |  00m00s
[ 30/149] rpm-build-libs-0:4.20.1-1.fc4 100% | 645.6 KiB/s |  94.3 KiB |  00m00s
[ 31/149] rpm-0:4.20.1-1.fc42.aarch64   100% |   3.0 MiB/s | 550.4 KiB |  00m00s
[ 32/149] rpm-libs-0:4.20.1-1.fc42.aarc 100% |   3.1 MiB/s | 305.2 KiB |  00m00s
[ 33/149] libacl-0:2.3.2-3.fc42.aarch64 100% | 212.6 KiB/s |  22.8 KiB |  00m00s
[ 34/149] zstd-0:1.5.7-1.fc42.aarch64   100% |   3.0 MiB/s | 445.4 KiB |  00m00s
[ 35/149] coreutils-common-0:9.6-8.fc42 100% |  48.5 MiB/s |   2.1 MiB |  00m00s
[ 36/149] setup-0:2.15.0-13.fc42.noarch 100% |   1.1 MiB/s | 155.8 KiB |  00m00s
[ 37/149] glibc-0:2.41-18.fc42.aarch64  100% |  70.1 MiB/s |   1.8 MiB |  00m00s
[ 38/149] libattr-0:2.5.2-5.fc42.aarch6 100% | 152.3 KiB/s |  16.4 KiB |  00m00s
[ 39/149] fedora-repos-0:42-1.noarch    100% | 113.9 KiB/s |   9.2 KiB |  00m00s
[ 40/149] glibc-common-0:2.41-18.fc42.a 100% |  19.5 MiB/s | 338.8 KiB |  00m00s
[ 41/149] forge-srpm-macros-0:0.4.0-2.f 100% | 209.0 KiB/s |  19.9 KiB |  00m00s
[ 42/149] ed-0:1.21-2.fc42.aarch64      100% | 795.4 KiB/s |  81.9 KiB |  00m00s
[ 43/149] ansible-srpm-macros-0:1-17.1. 100% | 188.1 KiB/s |  20.3 KiB |  00m00s
[ 44/149] ghc-srpm-macros-0:1.9.2-2.fc4 100% | 107.7 KiB/s |   9.2 KiB |  00m00s
[ 45/149] fpc-srpm-macros-0:1.3-14.fc42 100% |  66.8 KiB/s |   8.0 KiB |  00m00s
[ 46/149] gnat-srpm-macros-0:6-7.fc42.n 100% |  74.2 KiB/s |   8.6 KiB |  00m00s
[ 47/149] ocaml-srpm-macros-0:10-4.fc42 100% |  94.9 KiB/s |   9.2 KiB |  00m00s
[ 48/149] kernel-srpm-macros-0:1.0-25.f 100% |  61.7 KiB/s |   9.9 KiB |  00m00s
[ 49/149] lua-srpm-macros-0:1-15.fc42.n 100% |  64.6 KiB/s |   8.9 KiB |  00m00s
[ 50/149] perl-srpm-macros-0:1-57.fc42. 100% |  72.7 KiB/s |   8.5 KiB |  00m00s
[ 51/149] package-notes-srpm-macros-0:0 100% |  50.6 KiB/s |   9.3 KiB |  00m00s
[ 52/149] openblas-srpm-macros-0:2-19.f 100% |  34.8 KiB/s |   7.8 KiB |  00m00s
[ 53/149] tree-sitter-srpm-macros-0:0.1 100% | 114.6 KiB/s |  11.2 KiB |  00m00s
[ 54/149] libblkid-0:2.40.4-10.fc42.aar 100% |   7.4 MiB/s | 120.7 KiB |  00m00s
[ 55/149] zig-srpm-macros-0:1-4.fc42.no 100% |  95.9 KiB/s |   8.2 KiB |  00m00s
[ 56/149] libfdisk-0:2.40.4-10.fc42.aar 100% |   4.5 MiB/s | 151.5 KiB |  00m00s
[ 57/149] libmount-0:2.40.4-10.fc42.aar 100% |   8.6 MiB/s | 150.1 KiB |  00m00s
[ 58/149] libsmartcols-0:2.40.4-10.fc42 100% |   4.9 MiB/s |  79.9 KiB |  00m00s
[ 59/149] libuuid-0:2.40.4-10.fc42.aarc 100% |   1.7 MiB/s |  25.5 KiB |  00m00s
[ 60/149] util-linux-core-0:2.40.4-10.f 100% |  28.2 MiB/s | 520.4 KiB |  00m00s
[ 61/149] xz-libs-1:5.8.1-4.fc42.aarch6 100% |   6.8 MiB/s | 111.0 KiB |  00m00s
[ 62/149] zip-0:3.0-43.fc42.aarch64     100% |   2.0 MiB/s | 261.1 KiB |  00m00s
[ 63/149] pkgconf-m4-0:2.3.0-2.fc42.noa 100% | 215.7 KiB/s |  14.2 KiB |  00m00s
[ 64/149] libzstd-0:1.5.7-1.fc42.aarch6 100% |   2.0 MiB/s | 283.3 KiB |  00m00s
[ 65/149] pkgconf-0:2.3.0-2.fc42.aarch6 100% | 187.8 KiB/s |  44.7 KiB |  00m00s
[ 66/149] gnulib-l10n-0:20241231-1.fc42 100% |   9.2 MiB/s | 150.1 KiB |  00m00s
[ 67/149] ncurses-base-0:6.5-5.20250125 100% | 332.3 KiB/s |  88.1 KiB |  00m00s
[ 68/149] glibc-gconv-extra-0:2.41-18.f 100% |  32.3 MiB/s |   1.7 MiB |  00m00s
[ 69/149] basesystem-0:11-22.fc42.noarc 100% |  95.9 KiB/s |   7.3 KiB |  00m00s
[ 70/149] lz4-libs-0:1.10.0-2.fc42.aarc 100% | 352.1 KiB/s |  79.6 KiB |  00m00s
[ 71/149] libgcc-0:15.2.1-7.fc42.aarch6 100% |   7.4 MiB/s | 120.5 KiB |  00m00s
[ 72/149] fedora-gpg-keys-0:42-1.noarch 100% | 645.6 KiB/s | 135.6 KiB |  00m00s
[ 73/149] libstdc++-0:15.2.1-7.fc42.aar 100% |  41.7 MiB/s | 854.1 KiB |  00m00s
[ 74/149] zlib-ng-compat-0:2.2.5-2.fc42 100% |   4.0 MiB/s |  65.8 KiB |  00m00s
[ 75/149] libselinux-0:3.8-3.fc42.aarch 100% |   5.8 MiB/s |  95.7 KiB |  00m00s
[ 76/149] audit-libs-0:4.1.4-1.fc42.aar 100% |   8.5 MiB/s | 139.8 KiB |  00m00s
[ 77/149] filesystem-0:3.18-47.fc42.aar 100% |  60.6 MiB/s |   1.3 MiB |  00m00s
[ 78/149] libpkgconf-0:2.3.0-2.fc42.aar 100% | 241.9 KiB/s |  38.2 KiB |  00m00s
[ 79/149] libeconf-0:0.7.6-2.fc42.aarch 100% | 951.0 KiB/s |  35.2 KiB |  00m00s
[ 80/149] libsemanage-0:3.8.1-2.fc42.aa 100% |   3.6 MiB/s | 118.6 KiB |  00m00s
[ 81/149] libxcrypt-0:4.5.2-1.fc42.aarc 100% |   7.6 MiB/s | 125.2 KiB |  00m00s
[ 82/149] pam-libs-0:1.7.0-7.fc42.aarch 100% |   3.5 MiB/s |  56.6 KiB |  00m00s
[ 83/149] libcap-0:2.73-3.fc42.aarch64  100% |   5.5 MiB/s |  84.6 KiB |  00m00s
[ 84/149] lua-libs-0:5.4.8-4.fc42.aarch 100% |   7.9 MiB/s | 129.2 KiB |  00m00s
[ 85/149] rpm-sequoia-0:1.10.1-1.fc42.a 100% |  42.1 MiB/s | 862.6 KiB |  00m00s
[ 86/149] sqlite-libs-0:3.47.2-5.fc42.a 100% |  28.7 MiB/s | 734.2 KiB |  00m00s
[ 87/149] elfutils-libelf-0:0.195-1.fc4 100% |  12.6 MiB/s | 206.5 KiB |  00m00s
[ 88/149] elfutils-libs-0:0.195-1.fc42. 100% |  14.5 MiB/s | 266.4 KiB |  00m00s
[ 89/149] libsepol-0:3.8-1.fc42.aarch64 100% |   1.7 MiB/s | 323.9 KiB |  00m00s
[ 90/149] elfutils-debuginfod-client-0: 100% |   1.4 MiB/s |  45.4 KiB |  00m00s
[ 91/149] elfutils-0:0.195-1.fc42.aarch 100% |  12.1 MiB/s | 568.3 KiB |  00m00s
[ 92/149] file-libs-0:5.46-3.fc42.aarch 100% |  21.8 MiB/s | 847.5 KiB |  00m00s
[ 93/149] file-0:5.46-3.fc42.aarch64    100% |   1.0 MiB/s |  48.9 KiB |  00m00s
[ 94/149] libgomp-0:15.2.1-7.fc42.aarch 100% |  19.8 MiB/s | 365.4 KiB |  00m00s
[ 95/149] json-c-0:0.18-2.fc42.aarch64  100% | 436.1 KiB/s |  44.9 KiB |  00m00s
[ 96/149] debugedit-0:5.1-7.fc42.aarch6 100% |   2.3 MiB/s |  78.6 KiB |  00m00s
[ 97/149] binutils-0:2.44-12.fc42.aarch 100% |  68.1 MiB/s |   6.1 MiB |  00m00s
[ 98/149] libarchive-0:3.8.1-1.fc42.aar 100% |  18.3 MiB/s | 412.0 KiB |  00m00s
[ 99/149] jansson-0:2.14-2.fc42.aarch64 100% | 497.7 KiB/s |  46.8 KiB |  00m00s
[100/149] curl-0:8.11.1-8.fc42.aarch64  100% |  13.1 MiB/s | 214.9 KiB |  00m00s
[101/149] pcre2-0:10.46-1.fc42.aarch64  100% |  13.9 MiB/s | 242.5 KiB |  00m00s
[102/149] pcre2-syntax-0:10.46-1.fc42.n 100% |   9.9 MiB/s | 162.0 KiB |  00m00s
[103/149] libcap-ng-0:0.9.3-1.fc42.aarc 100% |   2.2 MiB/s |  34.5 KiB |  00m00s
[104/149] systemd-libs-0:257.13-1.fc42. 100% |  32.7 MiB/s | 770.2 KiB |  00m00s
[105/149] openssl-libs-1:3.2.6-4.fc42.a 100% | 103.6 MiB/s |   2.2 MiB |  00m00s
[106/149] build-reproducibility-srpm-ma 100% | 331.4 KiB/s |  11.9 KiB |  00m00s
[107/149] add-determinism-0:0.6.0-3.fc4 100% |  21.5 MiB/s | 836.0 KiB |  00m00s
[108/149] libxml2-0:2.12.10-1.fc42.aarc 100% |   5.9 MiB/s | 679.8 KiB |  00m00s
[109/149] dwz-0:0.16-1.fc42.aarch64     100% |   3.9 MiB/s | 132.2 KiB |  00m00s
[110/149] efi-srpm-macros-0:6-3.fc42.no 100% | 592.0 KiB/s |  22.5 KiB |  00m00s
[111/149] fonts-srpm-macros-1:2.0.5-22. 100% |   1.1 MiB/s |  27.2 KiB |  00m00s
[112/149] filesystem-srpm-macros-0:3.18 100% | 724.3 KiB/s |  26.1 KiB |  00m00s
[113/149] go-srpm-macros-0:3.8.0-1.fc42 100% |   1.0 MiB/s |  28.3 KiB |  00m00s
[114/149] pyproject-srpm-macros-0:1.19. 100% | 414.8 KiB/s |  13.3 KiB |  00m00s
[115/149] python-srpm-macros-0:3.13-5.f 100% | 591.1 KiB/s |  22.5 KiB |  00m00s
[116/149] qt5-srpm-macros-0:5.15.18-1.f 100% | 286.6 KiB/s |   8.6 KiB |  00m00s
[117/149] qt6-srpm-macros-0:6.10.2-1.fc 100% | 300.6 KiB/s |   9.0 KiB |  00m00s
[118/149] rust-srpm-macros-0:28.4-1.fc4 100% | 471.1 KiB/s |  10.8 KiB |  00m00s
[119/149] ca-certificates-0:2025.2.80_v 100% |  52.8 MiB/s | 972.7 KiB |  00m00s
[120/149] crypto-policies-0:20251125-1. 100% |   6.2 MiB/s |  94.7 KiB |  00m00s
[121/149] elfutils-default-yama-scope-0 100% | 747.4 KiB/s |  11.2 KiB |  00m00s
[122/149] p11-kit-0:0.26.2-1.fc42.aarch 100% |  25.6 MiB/s | 524.0 KiB |  00m00s
[123/149] p11-kit-trust-0:0.26.2-1.fc42 100% |   8.5 MiB/s | 139.6 KiB |  00m00s
[124/149] alternatives-0:1.33-3.fc42.aa 100% |   2.6 MiB/s |  39.9 KiB |  00m00s
[125/149] libffi-0:3.4.6-5.fc42.aarch64 100% | 425.8 KiB/s |  38.3 KiB |  00m00s
[126/149] systemd-standalone-sysusers-0 100% |   8.8 MiB/s | 143.8 KiB |  00m00s
[127/149] fedora-release-0:42-30.noarch 100% | 365.3 KiB/s |  13.5 KiB |  00m00s
[128/149] libtasn1-0:4.20.0-1.fc42.aarc 100% | 695.4 KiB/s |  73.7 KiB |  00m00s
[129/149] fedora-release-identity-basic 100% | 476.5 KiB/s |  14.3 KiB |  00m00s
[130/149] libcurl-0:8.11.1-8.fc42.aarch 100% |  22.0 MiB/s | 360.8 KiB |  00m00s
[131/149] libssh-0:0.11.4-1.fc42.aarch6 100% |  14.1 MiB/s | 231.6 KiB |  00m00s
[132/149] xxhash-libs-0:0.8.3-2.fc42.aa 100% | 313.7 KiB/s |  34.8 KiB |  00m00s
[133/149] gdb-minimal-0:17.1-1.fc42.aar 100% |  34.3 MiB/s |   4.2 MiB |  00m00s
[134/149] libnghttp2-0:1.64.0-3.fc42.aa 100% | 346.5 KiB/s |  76.9 KiB |  00m00s
[135/149] libssh-config-0:0.11.4-1.fc42 100% | 611.1 KiB/s |   9.2 KiB |  00m00s
[136/149] libidn2-0:2.3.8-1.fc42.aarch6 100% | 605.9 KiB/s | 175.1 KiB |  00m00s
[137/149] publicsuffix-list-dafsa-0:202 100% |   3.9 MiB/s |  60.3 KiB |  00m00s
[138/149] libpsl-0:0.21.5-5.fc42.aarch6 100% | 225.3 KiB/s |  64.2 KiB |  00m00s
[139/149] krb5-libs-0:1.21.3-7.fc42.aar 100% |  43.2 MiB/s | 751.7 KiB |  00m00s
[140/149] libunistring-0:1.1-9.fc42.aar 100% |   3.2 MiB/s | 539.4 KiB |  00m00s
[141/149] keyutils-libs-0:1.6.3-5.fc42. 100% | 228.5 KiB/s |  31.8 KiB |  00m00s
[142/149] libbrotli-0:1.2.0-1.fc42.aarc 100% |  21.4 MiB/s | 350.4 KiB |  00m00s
[143/149] libcom_err-0:1.47.2-3.fc42.aa 100% | 179.8 KiB/s |  26.8 KiB |  00m00s
[144/149] openldap-0:2.6.13-1.fc42.aarc 100% |  15.3 MiB/s | 251.0 KiB |  00m00s
[145/149] libverto-0:0.3.2-10.fc42.aarc 100% | 221.5 KiB/s |  20.8 KiB |  00m00s
[146/149] libtool-ltdl-0:2.5.4-4.fc42.a 100% | 166.4 KiB/s |  35.4 KiB |  00m00s
[147/149] libevent-0:2.1.12-15.fc42.aar 100% |   1.0 MiB/s | 254.7 KiB |  00m00s
[148/149] cyrus-sasl-lib-0:2.1.28-30.fc 100% |   2.4 MiB/s | 776.2 KiB |  00m00s
[149/149] gdbm-libs-1:1.23-9.fc42.aarch 100% | 230.1 KiB/s |  56.2 KiB |  00m00s
--------------------------------------------------------------------------------
[149/149] Total                         100% |  10.3 MiB/s |  51.3 MiB |  00m05s
Running transaction
Importing OpenPGP key 0x105EF944:
 UserID     : "Fedora (42) <fedora-42-primary@fedoraproject.org>"
 Fingerprint: B0F4950458F69E1150C6C5EDC8AC4916105EF944
 From       : file:///usr/share/distribution-gpg-keys/fedora/RPM-GPG-KEY-fedora-42-primary
The key was successfully imported.
[  1/151] Verify package files          100% | 699.0   B/s | 149.0   B |  00m00s
[  2/151] Prepare transaction           100% |   2.6 KiB/s | 149.0   B |  00m00s
[  3/151] Installing libgcc-0:15.2.1-7. 100% | 109.3 MiB/s | 223.9 KiB |  00m00s
[  4/151] Installing publicsuffix-list- 100% |  69.4 MiB/s |  71.1 KiB |  00m00s
[  5/151] Installing libssh-config-0:0. 100% |   0.0   B/s | 816.0   B |  00m00s
[  6/151] Installing fedora-release-ide 100% | 882.8 KiB/s | 904.0   B |  00m00s
[  7/151] Installing fedora-gpg-keys-0: 100% |  28.4 MiB/s | 174.8 KiB |  00m00s
[  8/151] Installing fedora-repos-0:42- 100% |   0.0   B/s |   5.7 KiB |  00m00s
[  9/151] Installing fedora-release-com 100% |  23.9 MiB/s |  24.5 KiB |  00m00s
[ 10/151] Installing fedora-release-0:4 100% |   7.6 KiB/s | 124.0   B |  00m00s
>>> Running sysusers scriptlet: setup-0:2.15.0-13.fc42.noarch                   
>>> Finished sysusers scriptlet: setup-0:2.15.0-13.fc42.noarch                  
>>> Scriptlet output:                                                           
>>> Creating group 'adm' with GID 4.                                            
>>> Creating group 'audio' with GID 63.                                         
>>> Creating group 'bin' with GID 1.                                            
>>> Creating group 'cdrom' with GID 11.                                         
>>> Creating group 'clock' with GID 103.                                        
>>> Creating group 'daemon' with GID 2.                                         
>>> Creating group 'dialout' with GID 18.                                       
>>> Creating group 'disk' with GID 6.                                           
>>> Creating group 'floppy' with GID 19.                                        
>>> Creating group 'ftp' with GID 50.                                           
>>> Creating group 'games' with GID 20.                                         
>>> Creating group 'input' with GID 104.                                        
>>> Creating group 'kmem' with GID 9.                                           
>>> Creating group 'kvm' with GID 36.                                           
>>> Creating group 'lock' with GID 54.                                          
>>> Creating group 'lp' with GID 7.                                             
>>> Creating group 'mail' with GID 12.                                          
>>> Creating group 'man' with GID 15.                                           
>>> Creating group 'mem' with GID 8.                                            
>>> Creating group 'nobody' with GID 65534.                                     
>>> Creating group 'render' with GID 105.                                       
>>> Creating group 'root' with GID 0.                                           
>>> Creating group 'sgx' with GID 106.                                          
>>> Creating group 'sys' with GID 3.                                            
>>> Creating group 'tape' with GID 33.                                          
>>> Creating group 'tty' with GID 5.                                            
>>> Creating group 'users' with GID 100.                                        
>>> Creating group 'utmp' with GID 22.                                          
>>> Creating group 'video' with GID 39.                                         
>>> Creating group 'wheel' with GID 10.                                         
>>>                                                                             
>>> Running sysusers scriptlet: setup-0:2.15.0-13.fc42.noarch                   
>>> Finished sysusers scriptlet: setup-0:2.15.0-13.fc42.noarch                  
>>> Scriptlet output:                                                           
>>> Creating user 'adm' (adm) with UID 3 and GID 4.                             
>>> Creating user 'bin' (bin) with UID 1 and GID 1.                             
>>> Creating user 'daemon' (daemon) with UID 2 and GID 2.                       
>>> Creating user 'ftp' (FTP User) with UID 14 and GID 50.                      
>>> Creating user 'games' (games) with UID 12 and GID 20.                       
>>> Creating user 'halt' (halt) with UID 7 and GID 0.                           
>>> Creating user 'lp' (lp) with UID 4 and GID 7.                               
>>> Creating user 'mail' (mail) with UID 8 and GID 12.                          
>>> Creating user 'nobody' (Kernel Overflow User) with UID 65534 and GID 65534. 
>>> Creating user 'operator' (operator) with UID 11 and GID 0.                  
>>> Creating user 'root' (Super User) with UID 0 and GID 0.                     
>>> Creating user 'shutdown' (shutdown) with UID 6 and GID 0.                   
>>> Creating user 'sync' (sync) with UID 5 and GID 0.                           
>>>                                                                             
[ 11/151] Installing setup-0:2.15.0-13. 100% |  37.3 MiB/s | 726.7 KiB |  00m00s
[ 12/151] Installing filesystem-0:3.18- 100% |   1.9 MiB/s | 212.8 KiB |  00m00s
[ 13/151] Installing basesystem-0:11-22 100% |   0.0   B/s | 124.0   B |  00m00s
[ 14/151] Installing rust-srpm-macros-0 100% |   6.2 MiB/s |   6.4 KiB |  00m00s
[ 15/151] Installing qt6-srpm-macros-0: 100% |   0.0   B/s | 748.0   B |  00m00s
[ 16/151] Installing qt5-srpm-macros-0: 100% |   0.0   B/s | 776.0   B |  00m00s
[ 17/151] Installing pcre2-syntax-0:10. 100% | 135.6 MiB/s | 277.8 KiB |  00m00s
[ 18/151] Installing gnulib-l10n-0:2024 100% | 129.3 MiB/s | 661.9 KiB |  00m00s
[ 19/151] Installing coreutils-common-0 100% | 309.8 MiB/s |  11.2 MiB |  00m00s
[ 20/151] Installing pkgconf-m4-0:2.3.0 100% |  14.5 MiB/s |  14.8 KiB |  00m00s
[ 21/151] Installing ncurses-base-0:6.5 100% |  57.3 MiB/s | 352.2 KiB |  00m00s
[ 22/151] Installing glibc-minimal-lang 100% |   0.0   B/s | 124.0   B |  00m00s
[ 23/151] Installing ncurses-libs-0:6.5 100% | 207.9 MiB/s |   1.2 MiB |  00m00s
[ 24/151] Installing glibc-0:2.41-18.fc 100% | 160.6 MiB/s |   6.3 MiB |  00m00s
[ 25/151] Installing bash-0:5.2.37-1.fc 100% | 205.8 MiB/s |   8.2 MiB |  00m00s
[ 26/151] Installing glibc-common-0:2.4 100% |  57.6 MiB/s |   1.3 MiB |  00m00s
[ 27/151] Installing glibc-gconv-extra- 100% | 373.2 MiB/s |  18.7 MiB |  00m00s
[ 28/151] Installing zlib-ng-compat-0:2 100% | 131.1 MiB/s | 134.2 KiB |  00m00s
[ 29/151] Installing bzip2-libs-0:1.0.8 100% |  72.0 MiB/s |  73.7 KiB |  00m00s
[ 30/151] Installing xz-libs-1:5.8.1-4. 100% | 197.9 MiB/s | 202.6 KiB |  00m00s
[ 31/151] Installing libuuid-0:2.40.4-1 100% |  68.9 MiB/s |  70.5 KiB |  00m00s
[ 32/151] Installing libblkid-0:2.40.4- 100% | 284.8 MiB/s | 291.6 KiB |  00m00s
[ 33/151] Installing gmp-1:6.3.0-4.fc42 100% | 214.9 MiB/s | 660.1 KiB |  00m00s
[ 34/151] Installing readline-0:8.2-13. 100% | 275.0 MiB/s | 563.2 KiB |  00m00s
[ 35/151] Installing popt-0:1.19-8.fc42 100% |  49.3 MiB/s | 151.4 KiB |  00m00s
[ 36/151] Installing libzstd-0:1.5.7-1. 100% | 217.8 MiB/s | 669.0 KiB |  00m00s
[ 37/151] Installing elfutils-libelf-0: 100% | 294.4 MiB/s |   1.2 MiB |  00m00s
[ 38/151] Installing libstdc++-0:15.2.1 100% | 314.2 MiB/s |   2.8 MiB |  00m00s
[ 39/151] Installing libxcrypt-0:4.5.2- 100% | 134.8 MiB/s | 276.1 KiB |  00m00s
[ 40/151] Installing libattr-0:2.5.2-5. 100% |  66.5 MiB/s |  68.0 KiB |  00m00s
[ 41/151] Installing libacl-0:2.3.2-3.f 100% |  65.5 MiB/s |  67.1 KiB |  00m00s
[ 42/151] Installing dwz-0:0.16-1.fc42. 100% |  17.6 MiB/s | 324.0 KiB |  00m00s
[ 43/151] Installing mpfr-0:4.2.2-1.fc4 100% | 184.9 MiB/s | 757.2 KiB |  00m00s
[ 44/151] Installing gawk-0:5.3.1-1.fc4 100% |  98.1 MiB/s |   2.5 MiB |  00m00s
[ 45/151] Installing unzip-0:6.0-66.fc4 100% |  25.7 MiB/s | 473.7 KiB |  00m00s
[ 46/151] Installing file-libs-0:5.46-3 100% | 625.3 MiB/s |  11.9 MiB |  00m00s
[ 47/151] Installing file-0:5.46-3.fc42 100% |   5.5 MiB/s | 141.7 KiB |  00m00s
[ 48/151] Installing crypto-policies-0: 100% |  20.5 MiB/s | 168.1 KiB |  00m00s
[ 49/151] Installing libsmartcols-0:2.4 100% | 220.3 MiB/s | 225.6 KiB |  00m00s
[ 50/151] Installing lz4-libs-0:1.10.0- 100% | 193.9 MiB/s | 198.5 KiB |  00m00s
[ 51/151] Installing libsepol-0:3.8-1.f 100% | 264.0 MiB/s | 810.9 KiB |  00m00s
[ 52/151] Installing libeconf-0:0.7.6-2 100% |  80.4 MiB/s |  82.3 KiB |  00m00s
[ 53/151] Installing lua-libs-0:5.4.8-4 100% | 161.8 MiB/s | 331.4 KiB |  00m00s
[ 54/151] Installing pcre2-0:10.46-1.fc 100% | 232.7 MiB/s | 715.0 KiB |  00m00s
[ 55/151] Installing libselinux-0:3.8-3 100% |  98.8 MiB/s | 202.3 KiB |  00m00s
[ 56/151] Installing grep-0:3.11-10.fc4 100% |  43.1 MiB/s |   1.0 MiB |  00m00s
[ 57/151] Installing findutils-1:4.10.0 100% |  80.0 MiB/s |   1.9 MiB |  00m00s
[ 58/151] Installing sed-0:4.9-4.fc42.a 100% |  39.1 MiB/s | 881.4 KiB |  00m00s
[ 59/151] Installing xz-1:5.8.1-4.fc42. 100% |  56.5 MiB/s |   1.4 MiB |  00m00s
[ 60/151] Installing libmount-0:2.40.4- 100% | 174.2 MiB/s | 356.8 KiB |  00m00s
[ 61/151] Installing libcap-ng-0:0.9.3- 100% | 159.1 MiB/s | 162.9 KiB |  00m00s
[ 62/151] Installing audit-libs-0:4.1.4 100% | 239.0 MiB/s | 489.5 KiB |  00m00s
[ 63/151] Installing pam-libs-0:1.7.0-7 100% | 219.9 MiB/s | 225.2 KiB |  00m00s
[ 64/151] Installing libcap-0:2.73-3.fc 100% |  27.8 MiB/s | 511.8 KiB |  00m00s
[ 65/151] Installing systemd-libs-0:257 100% | 291.9 MiB/s |   2.3 MiB |  00m00s
[ 66/151] Installing libffi-0:3.4.6-5.f 100% | 152.1 MiB/s | 155.8 KiB |  00m00s
[ 67/151] Installing libtasn1-0:4.20.0- 100% | 108.5 MiB/s | 222.2 KiB |  00m00s
[ 68/151] Installing p11-kit-0:0.26.2-1 100% |  95.3 MiB/s |   2.8 MiB |  00m00s
[ 69/151] Installing alternatives-0:1.3 100% |   5.3 MiB/s |  91.8 KiB |  00m00s
[ 70/151] Installing libunistring-0:1.1 100% | 291.0 MiB/s |   1.7 MiB |  00m00s
[ 71/151] Installing libidn2-0:2.3.8-1. 100% | 138.4 MiB/s | 566.7 KiB |  00m00s
[ 72/151] Installing libpsl-0:0.21.5-5. 100% | 130.5 MiB/s | 133.6 KiB |  00m00s
[ 73/151] Installing p11-kit-trust-0:0. 100% |  19.2 MiB/s | 532.0 KiB |  00m00s
[ 74/151] Installing openssl-libs-1:3.2 100% | 287.9 MiB/s |   6.3 MiB |  00m00s
[ 75/151] Installing coreutils-0:9.6-8. 100% | 171.4 MiB/s |   8.2 MiB |  00m00s
[ 76/151] Installing ca-certificates-0: 100% |   1.4 MiB/s |   2.5 MiB |  00m02s
[ 77/151] Installing gzip-0:1.13-3.fc42 100% |  21.0 MiB/s | 430.2 KiB |  00m00s
[ 78/151] Installing rpm-sequoia-0:1.10 100% | 279.1 MiB/s |   2.2 MiB |  00m00s
[ 79/151] Installing libevent-0:2.1.12- 100% | 271.3 MiB/s |   1.1 MiB |  00m00s
[ 80/151] Installing util-linux-core-0: 100% |  91.7 MiB/s |   2.4 MiB |  00m00s
[ 81/151] Installing systemd-standalone 100% |  17.9 MiB/s | 329.9 KiB |  00m00s
[ 82/151] Installing libsemanage-0:3.8. 100% | 117.8 MiB/s | 361.8 KiB |  00m00s
[ 83/151] Installing shadow-utils-2:4.1 100% | 104.2 MiB/s |   4.6 MiB |  00m00s
[ 84/151] Installing tar-2:1.35-5.fc42. 100% | 111.3 MiB/s |   3.0 MiB |  00m00s
[ 85/151] Installing zstd-0:1.5.7-1.fc4 100% |  71.7 MiB/s |   1.5 MiB |  00m00s
[ 86/151] Installing zip-0:3.0-43.fc42. 100% |  39.4 MiB/s | 766.4 KiB |  00m00s
[ 87/151] Installing libfdisk-0:2.40.4- 100% | 205.0 MiB/s | 419.9 KiB |  00m00s
[ 88/151] Installing libxml2-0:2.12.10- 100% |  82.2 MiB/s |   1.9 MiB |  00m00s
[ 89/151] Installing libarchive-0:3.8.1 100% | 238.5 MiB/s | 977.0 KiB |  00m00s
[ 90/151] Installing bzip2-0:1.0.8-20.f 100% |  10.1 MiB/s | 175.8 KiB |  00m00s
[ 91/151] Installing sqlite-libs-0:3.47 100% | 250.2 MiB/s |   1.5 MiB |  00m00s
[ 92/151] Installing rpm-libs-0:4.20.1- 100% | 239.3 MiB/s | 735.1 KiB |  00m00s
[ 93/151] Installing add-determinism-0: 100% |  91.1 MiB/s |   2.1 MiB |  00m00s
[ 94/151] Installing build-reproducibil 100% |   0.0   B/s |   1.0 KiB |  00m00s
[ 95/151] Installing ed-0:1.21-2.fc42.a 100% |   9.0 MiB/s | 156.8 KiB |  00m00s
[ 96/151] Installing patch-0:2.8-1.fc42 100% |  14.3 MiB/s | 264.0 KiB |  00m00s
[ 97/151] Installing filesystem-srpm-ma 100% |  38.0 MiB/s |  38.9 KiB |  00m00s
[ 98/151] Installing elfutils-default-y 100% | 340.5 KiB/s |   2.0 KiB |  00m00s
[ 99/151] Installing elfutils-libs-0:0. 100% | 182.8 MiB/s | 748.6 KiB |  00m00s
[100/151] Installing cpio-0:2.15-4.fc42 100% |  45.6 MiB/s |   1.1 MiB |  00m00s
[101/151] Installing diffutils-0:3.12-1 100% |  67.6 MiB/s |   1.6 MiB |  00m00s
[102/151] Installing libpkgconf-0:2.3.0 100% | 132.0 MiB/s | 135.1 KiB |  00m00s
[103/151] Installing pkgconf-0:2.3.0-2. 100% |   6.6 MiB/s | 114.9 KiB |  00m00s
[104/151] Installing pkgconf-pkg-config 100% | 104.3 KiB/s |   1.8 KiB |  00m00s
[105/151] Installing json-c-0:0.18-2.fc 100% | 136.7 MiB/s | 139.9 KiB |  00m00s
[106/151] Installing libgomp-0:15.2.1-7 100% | 253.1 MiB/s | 518.4 KiB |  00m00s
[107/151] Installing rpm-build-libs-0:4 100% | 194.7 MiB/s | 199.4 KiB |  00m00s
[108/151] Installing jansson-0:2.14-2.f 100% |  92.3 MiB/s |  94.5 KiB |  00m00s
[109/151] Installing xxhash-libs-0:0.8. 100% |  85.3 MiB/s |  87.4 KiB |  00m00s
[110/151] Installing libnghttp2-0:1.64. 100% | 194.5 MiB/s | 199.2 KiB |  00m00s
[111/151] Installing keyutils-libs-0:1. 100% |  97.4 MiB/s |  99.8 KiB |  00m00s
[112/151] Installing libcom_err-0:1.47. 100% | 109.5 MiB/s | 112.2 KiB |  00m00s
[113/151] Installing libverto-0:0.3.2-1 100% |  69.5 MiB/s |  71.2 KiB |  00m00s
[114/151] Installing krb5-libs-0:1.21.3 100% | 253.2 MiB/s |   2.5 MiB |  00m00s
[115/151] Installing libssh-0:0.11.4-1. 100% | 192.0 MiB/s | 589.8 KiB |  00m00s
[116/151] Installing libbrotli-0:1.2.0- 100% | 222.6 MiB/s | 911.8 KiB |  00m00s
[117/151] Installing libtool-ltdl-0:2.5 100% |  92.9 MiB/s |  95.1 KiB |  00m00s
[118/151] Installing gdbm-libs-1:1.23-9 100% | 230.1 MiB/s | 235.7 KiB |  00m00s
[119/151] Installing cyrus-sasl-lib-0:2 100% |  96.7 MiB/s |   2.4 MiB |  00m00s
[120/151] Installing openldap-0:2.6.13- 100% | 187.5 MiB/s | 768.1 KiB |  00m00s
[121/151] Installing libcurl-0:8.11.1-8 100% | 258.8 MiB/s | 795.1 KiB |  00m00s
[122/151] Installing elfutils-debuginfo 100% |   7.9 MiB/s | 146.4 KiB |  00m00s
[123/151] Installing elfutils-0:0.195-1 100% | 132.9 MiB/s |   3.6 MiB |  00m00s
[124/151] Installing binutils-0:2.44-12 100% | 276.5 MiB/s |  29.3 MiB |  00m00s
[125/151] Installing gdb-minimal-0:17.1 100% | 234.2 MiB/s |  13.4 MiB |  00m00s
[126/151] Installing debugedit-0:5.1-7. 100% |  13.4 MiB/s | 247.3 KiB |  00m00s
[127/151] Installing curl-0:8.11.1-8.fc 100% |  15.9 MiB/s | 457.2 KiB |  00m00s
[128/151] Installing rpm-0:4.20.1-1.fc4 100% |  70.3 MiB/s |   2.7 MiB |  00m00s
[129/151] Installing lua-srpm-macros-0: 100% |   1.9 MiB/s |   1.9 KiB |  00m00s
[130/151] Installing tree-sitter-srpm-m 100% |   7.2 MiB/s |   7.4 KiB |  00m00s
[131/151] Installing zig-srpm-macros-0: 100% |   0.0   B/s |   1.7 KiB |  00m00s
[132/151] Installing efi-srpm-macros-0: 100% |  40.2 MiB/s |  41.1 KiB |  00m00s
[133/151] Installing perl-srpm-macros-0 100% |   0.0   B/s |   1.1 KiB |  00m00s
[134/151] Installing package-notes-srpm 100% |   0.0   B/s |   2.0 KiB |  00m00s
[135/151] Installing openblas-srpm-macr 100% |   0.0   B/s | 392.0   B |  00m00s
[136/151] Installing ocaml-srpm-macros- 100% |   0.0   B/s |   2.2 KiB |  00m00s
[137/151] Installing kernel-srpm-macros 100% |   0.0   B/s |   2.3 KiB |  00m00s
[138/151] Installing gnat-srpm-macros-0 100% |   0.0   B/s |   1.3 KiB |  00m00s
[139/151] Installing ghc-srpm-macros-0: 100% |   0.0   B/s |   1.0 KiB |  00m00s
[140/151] Installing fpc-srpm-macros-0: 100% |   0.0   B/s | 420.0   B |  00m00s
[141/151] Installing ansible-srpm-macro 100% |  35.4 MiB/s |  36.2 KiB |  00m00s
[142/151] Installing forge-srpm-macros- 100% |  39.3 MiB/s |  40.3 KiB |  00m00s
[143/151] Installing fonts-srpm-macros- 100% |  55.7 MiB/s |  57.0 KiB |  00m00s
[144/151] Installing go-srpm-macros-0:3 100% |  61.6 MiB/s |  63.0 KiB |  00m00s
[145/151] Installing python-srpm-macros 100% |  50.9 MiB/s |  52.2 KiB |  00m00s
[146/151] Installing redhat-rpm-config- 100% |  62.6 MiB/s | 192.2 KiB |  00m00s
[147/151] Installing rpm-build-0:4.20.1 100% |  26.0 MiB/s | 533.0 KiB |  00m00s
[148/151] Installing pyproject-srpm-mac 100% |   1.2 MiB/s |   2.5 KiB |  00m00s
[149/151] Installing util-linux-0:2.40. 100% | 127.5 MiB/s |   6.6 MiB |  00m00s
[150/151] Installing which-0:2.23-2.fc4 100% |   6.8 MiB/s | 125.6 KiB |  00m00s
[151/151] Installing info-0:7.2-3.fc42. 100% | 189.3 KiB/s | 422.0 KiB |  00m02s
Complete!
Finish: installing minimal buildroot with dnf5
Start: creating root cache
Finish: creating root cache
Finish: chroot init
INFO: Installed packages:
INFO: add-determinism-0.6.0-3.fc42.aarch64
alternatives-1.33-3.fc42.aarch64
ansible-srpm-macros-1-17.1.fc42.noarch
audit-libs-4.1.4-1.fc42.aarch64
basesystem-11-22.fc42.noarch
bash-5.2.37-1.fc42.aarch64
binutils-2.44-12.fc42.aarch64
build-reproducibility-srpm-macros-0.6.0-3.fc42.noarch
bzip2-1.0.8-20.fc42.aarch64
bzip2-libs-1.0.8-20.fc42.aarch64
ca-certificates-2025.2.80_v9.0.304-1.1.fc42.noarch
coreutils-9.6-8.fc42.aarch64
coreutils-common-9.6-8.fc42.aarch64
cpio-2.15-4.fc42.aarch64
crypto-policies-20251125-1.git3839d0e.fc42.noarch
curl-8.11.1-8.fc42.aarch64
cyrus-sasl-lib-2.1.28-30.fc42.aarch64
debugedit-5.1-7.fc42.aarch64
diffutils-3.12-1.fc42.aarch64
dwz-0.16-1.fc42.aarch64
ed-1.21-2.fc42.aarch64
efi-srpm-macros-6-3.fc42.noarch
elfutils-0.195-1.fc42.aarch64
elfutils-debuginfod-client-0.195-1.fc42.aarch64
elfutils-default-yama-scope-0.195-1.fc42.noarch
elfutils-libelf-0.195-1.fc42.aarch64
elfutils-libs-0.195-1.fc42.aarch64
fedora-gpg-keys-42-1.noarch
fedora-release-42-30.noarch
fedora-release-common-42-30.noarch
fedora-release-identity-basic-42-30.noarch
fedora-repos-42-1.noarch
file-5.46-3.fc42.aarch64
file-libs-5.46-3.fc42.aarch64
filesystem-3.18-47.fc42.aarch64
filesystem-srpm-macros-3.18-47.fc42.noarch
findutils-4.10.0-5.fc42.aarch64
fonts-srpm-macros-2.0.5-22.fc42.noarch
forge-srpm-macros-0.4.0-2.fc42.noarch
fpc-srpm-macros-1.3-14.fc42.noarch
gawk-5.3.1-1.fc42.aarch64
gdb-minimal-17.1-1.fc42.aarch64
gdbm-libs-1.23-9.fc42.aarch64
ghc-srpm-macros-1.9.2-2.fc42.noarch
glibc-2.41-18.fc42.aarch64
glibc-common-2.41-18.fc42.aarch64
glibc-gconv-extra-2.41-18.fc42.aarch64
glibc-minimal-langpack-2.41-18.fc42.aarch64
gmp-6.3.0-4.fc42.aarch64
gnat-srpm-macros-6-7.fc42.noarch
gnulib-l10n-20241231-1.fc42.noarch
go-srpm-macros-3.8.0-1.fc42.noarch
gpg-pubkey-105ef944-65ca83d1
grep-3.11-10.fc42.aarch64
gzip-1.13-3.fc42.aarch64
info-7.2-3.fc42.aarch64
jansson-2.14-2.fc42.aarch64
json-c-0.18-2.fc42.aarch64
kernel-srpm-macros-1.0-25.fc42.noarch
keyutils-libs-1.6.3-5.fc42.aarch64
krb5-libs-1.21.3-7.fc42.aarch64
libacl-2.3.2-3.fc42.aarch64
libarchive-3.8.1-1.fc42.aarch64
libattr-2.5.2-5.fc42.aarch64
libblkid-2.40.4-10.fc42.aarch64
libbrotli-1.2.0-1.fc42.aarch64
libcap-2.73-3.fc42.aarch64
libcap-ng-0.9.3-1.fc42.aarch64
libcom_err-1.47.2-3.fc42.aarch64
libcurl-8.11.1-8.fc42.aarch64
libeconf-0.7.6-2.fc42.aarch64
libevent-2.1.12-15.fc42.aarch64
libfdisk-2.40.4-10.fc42.aarch64
libffi-3.4.6-5.fc42.aarch64
libgcc-15.2.1-7.fc42.aarch64
libgomp-15.2.1-7.fc42.aarch64
libidn2-2.3.8-1.fc42.aarch64
libmount-2.40.4-10.fc42.aarch64
libnghttp2-1.64.0-3.fc42.aarch64
libpkgconf-2.3.0-2.fc42.aarch64
libpsl-0.21.5-5.fc42.aarch64
libselinux-3.8-3.fc42.aarch64
libsemanage-3.8.1-2.fc42.aarch64
libsepol-3.8-1.fc42.aarch64
libsmartcols-2.40.4-10.fc42.aarch64
libssh-0.11.4-1.fc42.aarch64
libssh-config-0.11.4-1.fc42.noarch
libstdc++-15.2.1-7.fc42.aarch64
libtasn1-4.20.0-1.fc42.aarch64
libtool-ltdl-2.5.4-4.fc42.aarch64
libunistring-1.1-9.fc42.aarch64
libuuid-2.40.4-10.fc42.aarch64
libverto-0.3.2-10.fc42.aarch64
libxcrypt-4.5.2-1.fc42.aarch64
libxml2-2.12.10-1.fc42.aarch64
libzstd-1.5.7-1.fc42.aarch64
lua-libs-5.4.8-4.fc42.aarch64
lua-srpm-macros-1-15.fc42.noarch
lz4-libs-1.10.0-2.fc42.aarch64
mpfr-4.2.2-1.fc42.aarch64
ncurses-base-6.5-5.20250125.fc42.noarch
ncurses-libs-6.5-5.20250125.fc42.aarch64
ocaml-srpm-macros-10-4.fc42.noarch
openblas-srpm-macros-2-19.fc42.noarch
openldap-2.6.13-1.fc42.aarch64
openssl-libs-3.2.6-4.fc42.aarch64
p11-kit-0.26.2-1.fc42.aarch64
p11-kit-trust-0.26.2-1.fc42.aarch64
package-notes-srpm-macros-0.5-13.fc42.noarch
pam-libs-1.7.0-7.fc42.aarch64
patch-2.8-1.fc42.aarch64
pcre2-10.46-1.fc42.aarch64
pcre2-syntax-10.46-1.fc42.noarch
perl-srpm-macros-1-57.fc42.noarch
pkgconf-2.3.0-2.fc42.aarch64
pkgconf-m4-2.3.0-2.fc42.noarch
pkgconf-pkg-config-2.3.0-2.fc42.aarch64
popt-1.19-8.fc42.aarch64
publicsuffix-list-dafsa-20260116-1.fc42.noarch
pyproject-srpm-macros-1.19.0-1.fc42.noarch
python-srpm-macros-3.13-5.fc42.noarch
qt5-srpm-macros-5.15.18-1.fc42.noarch
qt6-srpm-macros-6.10.2-1.fc42.noarch
readline-8.2-13.fc42.aarch64
redhat-rpm-config-342-4.fc42.noarch
rpm-4.20.1-1.fc42.aarch64
rpm-build-4.20.1-1.fc42.aarch64
rpm-build-libs-4.20.1-1.fc42.aarch64
rpm-libs-4.20.1-1.fc42.aarch64
rpm-sequoia-1.10.1-1.fc42.aarch64
rust-srpm-macros-28.4-1.fc42.noarch
sed-4.9-4.fc42.aarch64
setup-2.15.0-13.fc42.noarch
shadow-utils-4.17.4-1.fc42.aarch64
sqlite-libs-3.47.2-5.fc42.aarch64
systemd-libs-257.13-1.fc42.aarch64
systemd-standalone-sysusers-257.13-1.fc42.aarch64
tar-1.35-5.fc42.aarch64
tree-sitter-srpm-macros-0.1.0-8.fc42.noarch
unzip-6.0-66.fc42.aarch64
util-linux-2.40.4-10.fc42.aarch64
util-linux-core-2.40.4-10.fc42.aarch64
which-2.23-2.fc42.aarch64
xxhash-libs-0.8.3-2.fc42.aarch64
xz-5.8.1-4.fc42.aarch64
xz-libs-5.8.1-4.fc42.aarch64
zig-srpm-macros-1-4.fc42.noarch
zip-3.0-43.fc42.aarch64
zlib-ng-compat-2.2.5-2.fc42.aarch64
zstd-1.5.7-1.fc42.aarch64
Start: buildsrpm
Start: rpmbuild -bs
Building target platforms: aarch64
Building for target aarch64
setting SOURCE_DATE_EPOCH=1654300800
Wrote: /builddir/build/SRPMS/litex-pythondata-cpu-cva6-2025.12-20260511.0.git6b3a376b.fc42.src.rpm
Finish: rpmbuild -bs
INFO: chroot_scan: 1 files copied to /var/lib/copr-rpmbuild/results/chroot_scan
INFO: /var/lib/mock/fedora-42-aarch64-1778795171.515428/root/var/log/dnf5.log
INFO: chroot_scan: creating tarball /var/lib/copr-rpmbuild/results/chroot_scan.tar.gz
/bin/tar: Removing leading `/' from member names
Finish: buildsrpm
INFO: Done(/var/lib/copr-rpmbuild/workspace/workdir-almc4me2/litex-pythondata-cpu-cva6/litex-pythondata-cpu-cva6.spec) Config(child) 0 minutes 25 seconds
INFO: Results and/or logs in: /var/lib/copr-rpmbuild/results
INFO: Cleaning up build root ('cleanup_on_success=True')
Start: clean chroot
INFO: unmounting tmpfs.
Finish: clean chroot
INFO: Start(/var/lib/copr-rpmbuild/results/litex-pythondata-cpu-cva6-2025.12-20260511.0.git6b3a376b.fc42.src.rpm)  Config(fedora-42-aarch64)
Start(bootstrap): chroot init
INFO: mounting tmpfs at /var/lib/mock/fedora-42-aarch64-bootstrap-1778795171.515428/root.
INFO: reusing tmpfs at /var/lib/mock/fedora-42-aarch64-bootstrap-1778795171.515428/root.
INFO: calling preinit hooks
INFO: enabled root cache
INFO: enabled package manager cache
Start(bootstrap): cleaning package manager metadata
Finish(bootstrap): cleaning package manager metadata
Finish(bootstrap): chroot init
Start: chroot init
INFO: mounting tmpfs at /var/lib/mock/fedora-42-aarch64-1778795171.515428/root.
INFO: calling preinit hooks
INFO: enabled root cache
Start: unpacking root cache
Finish: unpacking root cache
INFO: enabled package manager cache
Start: cleaning package manager metadata
Finish: cleaning package manager metadata
INFO: enabled HW Info plugin
INFO: Buildroot is handled by package management downloaded with a bootstrap image:
  rpm-4.20.1-1.fc42.aarch64
  rpm-sequoia-1.10.1-1.fc42.aarch64
  dnf5-5.2.18.0-3.fc42.aarch64
  dnf5-plugins-5.2.18.0-3.fc42.aarch64
Finish: chroot init
Start: build phase for litex-pythondata-cpu-cva6-2025.12-20260511.0.git6b3a376b.fc42.src.rpm
Start: build setup for litex-pythondata-cpu-cva6-2025.12-20260511.0.git6b3a376b.fc42.src.rpm
Building target platforms: aarch64
Building for target aarch64
setting SOURCE_DATE_EPOCH=1654300800
Wrote: /builddir/build/SRPMS/litex-pythondata-cpu-cva6-2025.12-20260511.0.git6b3a376b.fc42.src.rpm
Updating and loading repositories:
 Copr repository                        100% |   2.5 KiB/s |   1.5 KiB |  00m01s
 fedora                                 100% |  17.7 KiB/s |  16.3 KiB |  00m01s
 updates                                100% |  14.3 KiB/s |  12.2 KiB |  00m01s
Repositories loaded.
Package                 Arch    Version                 Repository      Size
Installing:
 git                    aarch64 2.54.0-1.fc42           updates     57.7 KiB
 python3-devel          aarch64 3.13.13-1.fc42          updates      1.8 MiB
 python3-setuptools     noarch  74.1.3-7.fc42           updates      8.4 MiB
Installing dependencies:
 expat                  aarch64 2.7.3-1.fc42            updates    361.0 KiB
 git-core               aarch64 2.54.0-1.fc42           updates     24.3 MiB
 git-core-doc           noarch  2.54.0-1.fc42           updates     18.7 MiB
 groff-base             aarch64 1.23.0-8.fc42           fedora       4.2 MiB
 less                   aarch64 685-1.fc42              updates    557.2 KiB
 libb2                  aarch64 0.98.1-13.fc42          fedora      74.1 KiB
 libcbor                aarch64 0.11.0-3.fc42           fedora     137.9 KiB
 libedit                aarch64 3.1-56.20251016cvs.fc42 updates    280.2 KiB
 libfido2               aarch64 1.15.0-3.fc42           fedora     278.3 KiB
 mpdecimal              aarch64 4.0.1-1.fc42            updates    281.2 KiB
 ncurses                aarch64 6.5-5.20250125.fc42     fedora     891.9 KiB
 openssh                aarch64 9.9p1-14.fc42           updates      1.4 MiB
 openssh-clients        aarch64 9.9p1-14.fc42           updates      2.8 MiB
 perl-AutoLoader        noarch  5.74-520.fc42           updates     20.5 KiB
 perl-B                 aarch64 1.89-520.fc42           updates    542.0 KiB
 perl-Carp              noarch  1.54-512.fc42           fedora      46.6 KiB
 perl-Class-Struct      noarch  0.68-520.fc42           updates     25.4 KiB
 perl-Data-Dumper       aarch64 2.189-513.fc42          fedora     135.6 KiB
 perl-Digest            noarch  1.20-512.fc42           fedora      35.3 KiB
 perl-Digest-MD5        aarch64 2.59-6.fc42             fedora     103.7 KiB
 perl-DynaLoader        aarch64 1.56-520.fc42           updates     32.1 KiB
 perl-Encode            aarch64 4:3.21-512.fc42         fedora       4.8 MiB
 perl-Errno             aarch64 1.38-520.fc42           updates      8.3 KiB
 perl-Error             noarch  1:0.17030-1.fc42        fedora      76.7 KiB
 perl-Exporter          noarch  5.78-512.fc42           fedora      54.3 KiB
 perl-Fcntl             aarch64 1.18-520.fc42           updates     92.9 KiB
 perl-File-Basename     noarch  2.86-520.fc42           updates     14.0 KiB
 perl-File-Path         noarch  2.18-512.fc42           fedora      63.5 KiB
 perl-File-Temp         noarch  1:0.231.100-512.fc42    fedora     162.3 KiB
 perl-File-stat         noarch  1.14-520.fc42           updates     12.5 KiB
 perl-FileHandle        noarch  2.05-520.fc42           updates      9.3 KiB
 perl-Getopt-Long       noarch  1:2.58-3.fc42           fedora     144.5 KiB
 perl-Getopt-Std        noarch  1.14-520.fc42           updates     11.2 KiB
 perl-Git               noarch  2.54.0-1.fc42           updates     64.4 KiB
 perl-HTTP-Tiny         noarch  0.090-2.fc42            fedora     154.4 KiB
 perl-IO                aarch64 1.55-520.fc42           updates    191.0 KiB
 perl-IO-Socket-IP      noarch  0.43-2.fc42             fedora     100.3 KiB
 perl-IO-Socket-SSL     noarch  2.089-2.fc42            fedora     703.3 KiB
 perl-IPC-Open3         noarch  1.22-520.fc42           updates     22.5 KiB
 perl-MIME-Base32       noarch  1.303-23.fc42           fedora      30.7 KiB
 perl-MIME-Base64       aarch64 3.16-512.fc42           fedora      94.1 KiB
 perl-Net-SSLeay        aarch64 1.94-8.fc42             fedora       1.4 MiB
 perl-POSIX             aarch64 2.20-520.fc42           updates    263.1 KiB
 perl-PathTools         aarch64 3.91-513.fc42           fedora     224.0 KiB
 perl-Pod-Escapes       noarch  1:1.07-512.fc42         fedora      24.9 KiB
 perl-Pod-Perldoc       noarch  3.28.01-513.fc42        fedora     163.7 KiB
 perl-Pod-Simple        noarch  1:3.45-512.fc42         fedora     560.8 KiB
 perl-Pod-Usage         noarch  4:2.05-1.fc42           fedora      86.3 KiB
 perl-Scalar-List-Utils aarch64 5:1.70-1.fc42           updates    152.9 KiB
 perl-SelectSaver       noarch  1.02-520.fc42           updates      2.2 KiB
 perl-Socket            aarch64 4:2.038-512.fc42        fedora     144.0 KiB
 perl-Storable          aarch64 1:3.32-512.fc42         fedora     244.3 KiB
 perl-Symbol            noarch  1.09-520.fc42           updates      6.8 KiB
 perl-Term-ANSIColor    noarch  5.01-513.fc42           fedora      97.5 KiB
 perl-Term-Cap          noarch  1.18-512.fc42           fedora      29.3 KiB
 perl-TermReadKey       aarch64 2.38-24.fc42            fedora     108.0 KiB
 perl-Text-ParseWords   noarch  3.31-512.fc42           fedora      13.6 KiB
 perl-Text-Tabs+Wrap    noarch  2024.001-512.fc42       fedora      22.6 KiB
 perl-Time-Local        noarch  2:1.350-512.fc42        fedora      68.9 KiB
 perl-URI               noarch  5.31-2.fc42             fedora     257.0 KiB
 perl-base              noarch  2.27-520.fc42           updates     12.5 KiB
 perl-constant          noarch  1.33-513.fc42           fedora      26.2 KiB
 perl-if                noarch  0.61.000-520.fc42       updates      5.8 KiB
 perl-interpreter       aarch64 4:5.40.4-520.fc42       updates    174.5 KiB
 perl-lib               aarch64 0.65-520.fc42           updates      8.5 KiB
 perl-libnet            noarch  3.15-513.fc42           fedora     289.4 KiB
 perl-libs              aarch64 4:5.40.4-520.fc42       updates      9.9 MiB
 perl-locale            noarch  1.12-520.fc42           updates      6.5 KiB
 perl-mro               aarch64 1.29-520.fc42           updates     81.6 KiB
 perl-overload          noarch  1.37-520.fc42           updates     71.5 KiB
 perl-overloading       noarch  0.02-520.fc42           updates      4.8 KiB
 perl-parent            noarch  1:0.244-2.fc42          fedora      10.3 KiB
 perl-podlators         noarch  1:6.0.2-3.fc42          fedora     317.5 KiB
 perl-vars              noarch  1.05-520.fc42           updates      3.9 KiB
 pyproject-rpm-macros   noarch  1.19.0-1.fc42           updates    116.7 KiB
 python-pip-wheel       noarch  24.3.1-5.fc42           updates      1.2 MiB
 python-rpm-macros      noarch  3.13-5.fc42             updates     22.1 KiB
 python3                aarch64 3.13.13-1.fc42          updates     84.7 KiB
 python3-libs           aarch64 3.13.13-1.fc42          updates     42.3 MiB
 python3-packaging      noarch  24.2-3.fc42             fedora     555.7 KiB
 python3-rpm-generators noarch  14-12.fc42              fedora      81.7 KiB
 python3-rpm-macros     noarch  3.13-5.fc42             updates      6.4 KiB
 tzdata                 noarch  2025c-1.fc42            updates      1.6 MiB

Transaction Summary:
 Installing:        86 packages

Total size of inbound packages is 32 MiB. Need to download 32 MiB.
After this operation, 133 MiB extra will be used (install 133 MiB, remove 0 B).
[ 1/86] git-0:2.54.0-1.fc42.aarch64     100% | 103.7 KiB/s |  40.7 KiB |  00m00s
[ 2/86] python3-devel-0:3.13.13-1.fc42. 100% | 520.6 KiB/s | 408.1 KiB |  00m01s
[ 3/86] perl-Getopt-Long-1:2.58-3.fc42. 100% | 155.0 KiB/s |  63.7 KiB |  00m00s
[ 4/86] perl-TermReadKey-0:2.38-24.fc42 100% | 486.1 KiB/s |  35.5 KiB |  00m00s
[ 5/86] perl-PathTools-0:3.91-513.fc42. 100% | 317.3 KiB/s |  87.3 KiB |  00m00s
[ 6/86] python3-setuptools-0:74.1.3-7.f 100% | 879.7 KiB/s |   2.0 MiB |  00m02s
[ 7/86] perl-Git-0:2.54.0-1.fc42.noarch 100% | 296.4 KiB/s |  37.3 KiB |  00m00s
[ 8/86] python3-0:3.13.13-1.fc42.aarch6 100% | 414.1 KiB/s |  30.2 KiB |  00m00s
[ 9/86] python3-libs-0:3.13.13-1.fc42.a 100% |  10.4 MiB/s |   9.1 MiB |  00m01s
[10/86] perl-Exporter-0:5.78-512.fc42.n 100% | 224.6 KiB/s |  31.0 KiB |  00m00s
[11/86] perl-Pod-Usage-4:2.05-1.fc42.no 100% | 562.6 KiB/s |  40.5 KiB |  00m00s
[12/86] perl-Text-ParseWords-0:3.31-512 100% | 235.4 KiB/s |  16.5 KiB |  00m00s
[13/86] perl-constant-0:1.33-513.fc42.n 100% | 323.7 KiB/s |  23.0 KiB |  00m00s
[14/86] perl-Carp-0:1.54-512.fc42.noarc 100% | 406.5 KiB/s |  28.9 KiB |  00m00s
[15/86] perl-Error-1:0.17030-1.fc42.noa 100% | 553.1 KiB/s |  40.4 KiB |  00m00s
[16/86] libb2-0:0.98.1-13.fc42.aarch64  100% | 365.6 KiB/s |  26.0 KiB |  00m00s
[17/86] expat-0:2.7.3-1.fc42.aarch64    100% |   1.6 MiB/s | 116.1 KiB |  00m00s
[18/86] perl-Pod-Perldoc-0:3.28.01-513. 100% | 604.3 KiB/s |  85.8 KiB |  00m00s
[19/86] git-core-doc-0:2.54.0-1.fc42.no 100% |   1.0 MiB/s |   3.1 MiB |  00m03s
[20/86] perl-podlators-1:6.0.2-3.fc42.n 100% | 880.9 KiB/s | 128.6 KiB |  00m00s
[21/86] perl-Encode-4:3.21-512.fc42.aar 100% |   5.1 MiB/s |   1.0 MiB |  00m00s
[22/86] perl-File-Temp-1:0.231.100-512. 100% | 896.4 KiB/s |  59.2 KiB |  00m00s
[23/86] perl-HTTP-Tiny-0:0.090-2.fc42.n 100% | 843.7 KiB/s |  56.5 KiB |  00m00s
[24/86] perl-Pod-Simple-1:3.45-512.fc42 100% |   3.2 MiB/s | 219.0 KiB |  00m00s
[25/86] perl-parent-1:0.244-2.fc42.noar 100% | 230.7 KiB/s |  15.2 KiB |  00m00s
[26/86] groff-base-0:1.23.0-8.fc42.aarc 100% |   2.0 MiB/s |   1.1 MiB |  00m01s
[27/86] perl-Term-ANSIColor-0:5.01-513. 100% | 722.6 KiB/s |  47.7 KiB |  00m00s
[28/86] perl-Term-Cap-0:1.18-512.fc42.n 100% | 316.5 KiB/s |  22.2 KiB |  00m00s
[29/86] perl-MIME-Base64-0:3.16-512.fc4 100% | 448.5 KiB/s |  30.1 KiB |  00m00s
[30/86] perl-Storable-1:3.32-512.fc42.a 100% |   1.3 MiB/s |  96.1 KiB |  00m00s
[31/86] perl-File-Path-0:2.18-512.fc42. 100% | 533.0 KiB/s |  35.2 KiB |  00m00s
[32/86] perl-IO-Socket-SSL-0:2.089-2.fc 100% |   3.1 MiB/s | 230.2 KiB |  00m00s
[33/86] perl-Net-SSLeay-0:1.94-8.fc42.a 100% |   5.5 MiB/s | 378.4 KiB |  00m00s
[34/86] perl-Socket-4:2.038-512.fc42.aa 100% | 765.9 KiB/s |  55.1 KiB |  00m00s
[35/86] perl-Time-Local-2:1.350-512.fc4 100% | 522.1 KiB/s |  34.5 KiB |  00m00s
[36/86] perl-Pod-Escapes-1:1.07-512.fc4 100% | 287.2 KiB/s |  19.8 KiB |  00m00s
[37/86] perl-Text-Tabs+Wrap-0:2024.001- 100% | 330.3 KiB/s |  21.8 KiB |  00m00s
[38/86] ncurses-0:6.5-5.20250125.fc42.a 100% |   5.3 MiB/s | 422.0 KiB |  00m00s
[39/86] perl-IO-Socket-IP-0:0.43-2.fc42 100% | 632.3 KiB/s |  42.4 KiB |  00m00s
[40/86] perl-URI-0:5.31-2.fc42.noarch   100% |   2.0 MiB/s | 140.7 KiB |  00m00s
[41/86] perl-Data-Dumper-0:2.189-513.fc 100% | 833.7 KiB/s |  55.0 KiB |  00m00s
[42/86] perl-MIME-Base32-0:1.303-23.fc4 100% | 310.8 KiB/s |  20.5 KiB |  00m00s
[43/86] perl-libnet-0:3.15-513.fc42.noa 100% |   1.9 MiB/s | 128.4 KiB |  00m00s
[44/86] perl-Digest-MD5-0:2.59-6.fc42.a 100% | 544.2 KiB/s |  35.9 KiB |  00m00s
[45/86] perl-Digest-0:1.20-512.fc42.noa 100% | 377.8 KiB/s |  24.9 KiB |  00m00s
[46/86] git-core-0:2.54.0-1.fc42.aarch6 100% |   1.1 MiB/s |   5.2 MiB |  00m05s
[47/86] mpdecimal-0:4.0.1-1.fc42.aarch6 100% | 469.4 KiB/s |  95.8 KiB |  00m00s
[48/86] perl-libs-4:5.40.4-520.fc42.aar 100% |   6.7 MiB/s |   2.3 MiB |  00m00s
[49/86] perl-interpreter-4:5.40.4-520.f 100% | 978.8 KiB/s |  71.5 KiB |  00m00s
[50/86] perl-Errno-0:1.38-520.fc42.aarc 100% | 193.3 KiB/s |  14.1 KiB |  00m00s
[51/86] less-0:685-1.fc42.aarch64       100% |   2.7 MiB/s | 198.2 KiB |  00m00s
[52/86] openssh-clients-0:9.9p1-14.fc42 100% |   9.7 MiB/s | 752.5 KiB |  00m00s
[53/86] tzdata-0:2025c-1.fc42.noarch    100% |   1.0 MiB/s | 713.7 KiB |  00m01s
[54/86] libfido2-0:1.15.0-3.fc42.aarch6 100% |   1.4 MiB/s |  96.1 KiB |  00m00s
[55/86] libcbor-0:0.11.0-3.fc42.aarch64 100% | 483.1 KiB/s |  32.4 KiB |  00m00s
[56/86] perl-File-Basename-0:2.86-520.f 100% | 224.2 KiB/s |  16.4 KiB |  00m00s
[57/86] perl-IPC-Open3-0:1.22-520.fc42. 100% | 284.6 KiB/s |  21.1 KiB |  00m00s
[58/86] perl-lib-0:0.65-520.fc42.aarch6 100% | 193.5 KiB/s |  14.1 KiB |  00m00s
[59/86] openssh-0:9.9p1-14.fc42.aarch64 100% | 954.4 KiB/s | 345.5 KiB |  00m00s
[60/86] perl-Fcntl-0:1.18-520.fc42.aarc 100% | 398.0 KiB/s |  29.1 KiB |  00m00s
[61/86] perl-POSIX-0:2.20-520.fc42.aarc 100% |   1.1 MiB/s |  96.7 KiB |  00m00s
[62/86] python-pip-wheel-0:24.3.1-5.fc4 100% | 914.7 KiB/s |   1.2 MiB |  00m01s
[63/86] perl-FileHandle-0:2.05-520.fc42 100% | 201.5 KiB/s |  14.7 KiB |  00m00s
[64/86] perl-IO-0:1.55-520.fc42.aarch64 100% | 681.5 KiB/s |  81.1 KiB |  00m00s
[65/86] perl-base-0:2.27-520.fc42.noarc 100% | 211.1 KiB/s |  15.4 KiB |  00m00s
[66/86] perl-Symbol-0:1.09-520.fc42.noa 100% |  98.7 KiB/s |  13.4 KiB |  00m00s
[67/86] perl-Scalar-List-Utils-5:1.70-1 100% | 516.1 KiB/s |  72.8 KiB |  00m00s
[68/86] perl-overload-0:1.37-520.fc42.n 100% | 613.1 KiB/s |  44.8 KiB |  00m00s
[69/86] perl-DynaLoader-0:1.56-520.fc42 100% | 345.5 KiB/s |  25.2 KiB |  00m00s
[70/86] perl-vars-0:1.05-520.fc42.noarc 100% | 165.1 KiB/s |  12.2 KiB |  00m00s
[71/86] perl-if-0:0.61.000-520.fc42.noa 100% | 181.0 KiB/s |  13.2 KiB |  00m00s
[72/86] perl-AutoLoader-0:5.74-520.fc42 100% | 280.0 KiB/s |  20.4 KiB |  00m00s
[73/86] perl-Getopt-Std-0:1.14-520.fc42 100% | 201.3 KiB/s |  14.9 KiB |  00m00s
[74/86] perl-mro-0:1.29-520.fc42.aarch6 100% | 393.1 KiB/s |  28.7 KiB |  00m00s
[75/86] perl-overloading-0:0.02-520.fc4 100% | 163.7 KiB/s |  12.1 KiB |  00m00s
[76/86] perl-B-0:1.89-520.fc42.aarch64  100% |   1.8 MiB/s | 176.0 KiB |  00m00s
[77/86] perl-locale-0:1.12-520.fc42.noa 100% | 173.4 KiB/s |  12.8 KiB |  00m00s
[78/86] perl-File-stat-0:1.14-520.fc42. 100% | 222.7 KiB/s |  16.3 KiB |  00m00s
[79/86] perl-SelectSaver-0:1.02-520.fc4 100% | 147.8 KiB/s |  10.9 KiB |  00m00s
[80/86] perl-Class-Struct-0:0.68-520.fc 100% | 291.4 KiB/s |  21.3 KiB |  00m00s
[81/86] pyproject-rpm-macros-0:1.19.0-1 100% | 431.5 KiB/s |  44.9 KiB |  00m00s
[82/86] libedit-0:3.1-56.20251016cvs.fc 100% | 929.9 KiB/s | 104.1 KiB |  00m00s
[83/86] python-rpm-macros-0:3.13-5.fc42 100% | 205.2 KiB/s |  16.4 KiB |  00m00s
[84/86] python3-rpm-macros-0:3.13-5.fc4 100% | 131.7 KiB/s |  11.2 KiB |  00m00s
[85/86] python3-rpm-generators-0:14-12. 100% | 217.8 KiB/s |  29.2 KiB |  00m00s
[86/86] python3-packaging-0:24.2-3.fc42 100% | 579.0 KiB/s | 154.0 KiB |  00m00s
--------------------------------------------------------------------------------
[86/86] Total                           100% |   4.2 MiB/s |  31.8 MiB |  00m08s
Running transaction
[ 1/88] Verify package files            100% | 722.0   B/s |  86.0   B |  00m00s
[ 2/88] Prepare transaction             100% |   1.3 KiB/s |  86.0   B |  00m00s
[ 3/88] Installing python-rpm-macros-0: 100% |  22.3 MiB/s |  22.8 KiB |  00m00s
[ 4/88] Installing python3-rpm-macros-0 100% |   0.0   B/s |   6.7 KiB |  00m00s
[ 5/88] Installing expat-0:2.7.3-1.fc42 100% |  17.7 MiB/s | 363.1 KiB |  00m00s
[ 6/88] Installing pyproject-rpm-macros 100% | 115.9 MiB/s | 118.7 KiB |  00m00s
[ 7/88] Installing libedit-0:3.1-56.202 100% | 137.6 MiB/s | 281.8 KiB |  00m00s
[ 8/88] Installing libcbor-0:0.11.0-3.f 100% | 136.0 MiB/s | 139.3 KiB |  00m00s
[ 9/88] Installing libfido2-0:1.15.0-3. 100% | 136.6 MiB/s | 279.8 KiB |  00m00s
[10/88] Installing openssh-0:9.9p1-14.f 100% |  65.8 MiB/s |   1.4 MiB |  00m00s
[11/88] Installing openssh-clients-0:9. 100% |  88.1 MiB/s |   2.8 MiB |  00m00s
[12/88] Installing less-0:685-1.fc42.aa 100% |  27.4 MiB/s | 560.7 KiB |  00m00s
[13/88] Installing git-core-0:2.54.0-1. 100% | 280.2 MiB/s |  24.4 MiB |  00m00s
[14/88] Installing git-core-doc-0:2.54. 100% | 269.5 MiB/s |  18.9 MiB |  00m00s
[15/88] Installing tzdata-0:2025c-1.fc4 100% |  39.5 MiB/s |   1.9 MiB |  00m00s
[16/88] Installing python-pip-wheel-0:2 100% | 622.2 MiB/s |   1.2 MiB |  00m00s
[17/88] Installing mpdecimal-0:4.0.1-1. 100% | 138.1 MiB/s | 282.7 KiB |  00m00s
[18/88] Installing ncurses-0:6.5-5.2025 100% |  31.3 MiB/s | 898.4 KiB |  00m00s
[19/88] Installing groff-base-0:1.23.0- 100% |  95.4 MiB/s |   4.2 MiB |  00m00s
[20/88] Installing perl-Digest-0:1.20-5 100% |  36.2 MiB/s |  37.1 KiB |  00m00s
[21/88] Installing perl-Digest-MD5-0:2. 100% | 103.1 MiB/s | 105.6 KiB |  00m00s
[22/88] Installing perl-B-0:1.89-520.fc 100% | 177.5 MiB/s | 545.3 KiB |  00m00s
[23/88] Installing perl-FileHandle-0:2. 100% |   0.0   B/s |   9.8 KiB |  00m00s
[24/88] Installing perl-MIME-Base32-0:1 100% |  31.4 MiB/s |  32.2 KiB |  00m00s
[25/88] Installing perl-Data-Dumper-0:2 100% | 134.3 MiB/s | 137.5 KiB |  00m00s
[26/88] Installing perl-libnet-0:3.15-5 100% | 143.9 MiB/s | 294.7 KiB |  00m00s
[27/88] Installing perl-AutoLoader-0:5. 100% |   0.0   B/s |  20.9 KiB |  00m00s
[28/88] Installing perl-IO-Socket-IP-0: 100% |  99.8 MiB/s | 102.2 KiB |  00m00s
[29/88] Installing perl-URI-0:5.31-2.fc 100% |  65.8 MiB/s | 269.6 KiB |  00m00s
[30/88] Installing perl-Time-Local-2:1. 100% |  68.9 MiB/s |  70.6 KiB |  00m00s
[31/88] Installing perl-Text-Tabs+Wrap- 100% |  23.3 MiB/s |  23.9 KiB |  00m00s
[32/88] Installing perl-File-Path-0:2.1 100% |  63.0 MiB/s |  64.5 KiB |  00m00s
[33/88] Installing perl-Pod-Escapes-1:1 100% |  25.3 MiB/s |  25.9 KiB |  00m00s
[34/88] Installing perl-if-0:0.61.000-5 100% |   6.1 MiB/s |   6.2 KiB |  00m00s
[35/88] Installing perl-Net-SSLeay-0:1. 100% | 204.7 MiB/s |   1.4 MiB |  00m00s
[36/88] Installing perl-locale-0:1.12-5 100% |   0.0   B/s |   6.9 KiB |  00m00s
[37/88] Installing perl-IO-Socket-SSL-0 100% | 230.3 MiB/s | 707.4 KiB |  00m00s
[38/88] Installing perl-Term-ANSIColor- 100% |  96.9 MiB/s |  99.2 KiB |  00m00s
[39/88] Installing perl-Term-Cap-0:1.18 100% |  29.9 MiB/s |  30.6 KiB |  00m00s
[40/88] Installing perl-POSIX-0:2.20-52 100% | 129.1 MiB/s | 264.4 KiB |  00m00s
[41/88] Installing perl-File-Temp-1:0.2 100% | 160.2 MiB/s | 164.1 KiB |  00m00s
[42/88] Installing perl-IPC-Open3-0:1.2 100% |  22.7 MiB/s |  23.3 KiB |  00m00s
[43/88] Installing perl-HTTP-Tiny-0:0.0 100% | 152.8 MiB/s | 156.4 KiB |  00m00s
[44/88] Installing perl-Class-Struct-0: 100% |  25.3 MiB/s |  25.9 KiB |  00m00s
[45/88] Installing perl-Pod-Simple-1:3. 100% | 185.7 MiB/s | 570.4 KiB |  00m00s
[46/88] Installing perl-Socket-4:2.038- 100% | 142.6 MiB/s | 146.0 KiB |  00m00s
[47/88] Installing perl-Symbol-0:1.09-5 100% |   0.0   B/s |   7.2 KiB |  00m00s
[48/88] Installing perl-SelectSaver-0:1 100% |   0.0   B/s |   2.6 KiB |  00m00s
[49/88] Installing perl-File-stat-0:1.1 100% |  12.7 MiB/s |  13.1 KiB |  00m00s
[50/88] Installing perl-Pod-Perldoc-0:3 100% |   8.3 MiB/s | 169.2 KiB |  00m00s
[51/88] Installing perl-podlators-1:6.0 100% |  16.5 MiB/s | 321.4 KiB |  00m00s
[52/88] Installing perl-Text-ParseWords 100% |  14.2 MiB/s |  14.6 KiB |  00m00s
[53/88] Installing perl-Fcntl-0:1.18-52 100% |  91.9 MiB/s |  94.1 KiB |  00m00s
[54/88] Installing perl-base-0:2.27-520 100% |   0.0   B/s |  12.9 KiB |  00m00s
[55/88] Installing perl-mro-0:1.29-520. 100% |  80.7 MiB/s |  82.7 KiB |  00m00s
[56/88] Installing perl-overloading-0:0 100% |   5.4 MiB/s |   5.5 KiB |  00m00s
[57/88] Installing perl-IO-0:1.55-520.f 100% |  95.4 MiB/s | 195.3 KiB |  00m00s
[58/88] Installing perl-Pod-Usage-4:2.0 100% |   4.8 MiB/s |  87.9 KiB |  00m00s
[59/88] Installing perl-constant-0:1.33 100% |  26.7 MiB/s |  27.4 KiB |  00m00s
[60/88] Installing perl-parent-1:0.244- 100% |  10.7 MiB/s |  11.0 KiB |  00m00s
[61/88] Installing perl-MIME-Base64-0:3 100% |  94.0 MiB/s |  96.3 KiB |  00m00s
[62/88] Installing perl-Errno-0:1.38-52 100% |   0.0   B/s |   8.7 KiB |  00m00s
[63/88] Installing perl-File-Basename-0 100% |   0.0   B/s |  14.6 KiB |  00m00s
[64/88] Installing perl-Scalar-List-Uti 100% |  76.5 MiB/s | 156.7 KiB |  00m00s
[65/88] Installing perl-vars-0:1.05-520 100% |   0.0   B/s |   4.3 KiB |  00m00s
[66/88] Installing perl-Getopt-Std-0:1. 100% |   0.0   B/s |  11.7 KiB |  00m00s
[67/88] Installing perl-overload-0:1.37 100% |  70.3 MiB/s |  71.9 KiB |  00m00s
[68/88] Installing perl-Storable-1:3.32 100% | 120.1 MiB/s | 245.9 KiB |  00m00s
[69/88] Installing perl-Getopt-Long-1:2 100% | 143.8 MiB/s | 147.2 KiB |  00m00s
[70/88] Installing perl-Exporter-0:5.78 100% |  54.3 MiB/s |  55.6 KiB |  00m00s
[71/88] Installing perl-Carp-0:1.54-512 100% |  46.6 MiB/s |  47.7 KiB |  00m00s
[72/88] Installing perl-PathTools-0:3.9 100% | 111.6 MiB/s | 228.6 KiB |  00m00s
[73/88] Installing perl-DynaLoader-0:1. 100% |  31.7 MiB/s |  32.5 KiB |  00m00s
[74/88] Installing perl-Encode-4:3.21-5 100% | 142.4 MiB/s |   4.8 MiB |  00m00s
[75/88] Installing perl-libs-4:5.40.4-5 100% | 208.8 MiB/s |  10.0 MiB |  00m00s
[76/88] Installing perl-interpreter-4:5 100% |   9.6 MiB/s | 176.1 KiB |  00m00s
[77/88] Installing perl-TermReadKey-0:2 100% |  53.8 MiB/s | 110.2 KiB |  00m00s
[78/88] Installing perl-Error-1:0.17030 100% |  78.1 MiB/s |  80.0 KiB |  00m00s
[79/88] Installing perl-lib-0:0.65-520. 100% |   0.0   B/s |   8.9 KiB |  00m00s
[80/88] Installing perl-Git-0:2.54.0-1. 100% |  63.8 MiB/s |  65.4 KiB |  00m00s
[81/88] Installing git-0:2.54.0-1.fc42. 100% |  57.6 MiB/s |  59.0 KiB |  00m00s
[82/88] Installing libb2-0:0.98.1-13.fc 100% |  12.2 MiB/s |  75.2 KiB |  00m00s
[83/88] Installing python3-libs-0:3.13. 100% | 268.3 MiB/s |  42.7 MiB |  00m00s
[84/88] Installing python3-0:3.13.13-1. 100% |   4.7 MiB/s |  86.4 KiB |  00m00s
[85/88] Installing python3-packaging-0: 100% | 138.7 MiB/s | 568.0 KiB |  00m00s
[86/88] Installing python3-rpm-generato 100% |  81.0 MiB/s |  82.9 KiB |  00m00s
[87/88] Installing python3-devel-0:3.13 100% |  59.2 MiB/s |   1.8 MiB |  00m00s
[88/88] Installing python3-setuptools-0 100% |  96.2 MiB/s |   8.6 MiB |  00m00s
Complete!
Building target platforms: aarch64
Building for target aarch64
setting SOURCE_DATE_EPOCH=1654300800
Wrote: /builddir/build/SRPMS/litex-pythondata-cpu-cva6-2025.12-20260511.0.git6b3a376b.fc42.src.rpm
Updating and loading repositories:
 Copr repository                        100% |   2.4 KiB/s |   1.5 KiB |  00m01s
 fedora                                 100% |  21.7 KiB/s |  16.3 KiB |  00m01s
 updates                                100% |  17.6 KiB/s |  12.2 KiB |  00m01s
Repositories loaded.
Package "git-2.54.0-1.fc42.aarch64" is already installed.
Package "python3-devel-3.13.13-1.fc42.aarch64" is already installed.
Package "python3-setuptools-74.1.3-7.fc42.noarch" is already installed.

Nothing to do.
Finish: build setup for litex-pythondata-cpu-cva6-2025.12-20260511.0.git6b3a376b.fc42.src.rpm
Start: rpmbuild litex-pythondata-cpu-cva6-2025.12-20260511.0.git6b3a376b.fc42.src.rpm
Building target platforms: aarch64
Building for target aarch64
setting SOURCE_DATE_EPOCH=1654300800
Executing(%mkbuilddir): /bin/sh -e /var/tmp/rpm-tmp.nwHqcQ
Executing(%prep): /bin/sh -e /var/tmp/rpm-tmp.ofCGGd
+ umask 022
+ cd /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build
+ cd /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build
+ rm -rf litex-pythondata-cpu-cva6
+ /usr/bin/mkdir -p litex-pythondata-cpu-cva6
+ cd litex-pythondata-cpu-cva6
+ /usr/bin/chmod -Rf a+rX,u+w,g-w,o-w .
+ git clone --depth 1 -n -b master https://github.com/litex-hub/pythondata-cpu-cva6.git .
Cloning into '.'...
+ git fetch --depth 1 origin 6b3a376bea43cbc58d5a42e440bf5c63d88f1e0a
From https://github.com/litex-hub/pythondata-cpu-cva6
 * branch            6b3a376bea43cbc58d5a42e440bf5c63d88f1e0a -> FETCH_HEAD
+ git reset --hard 6b3a376bea43cbc58d5a42e440bf5c63d88f1e0a
HEAD is now at 6b3a376 packaging: add PyPI publishing workflow
+ git log --format=fuller
commit 6b3a376bea43cbc58d5a42e440bf5c63d88f1e0a
Author:     Florent Kermarrec <florent@enjoy-digital.fr>
AuthorDate: Mon May 11 11:41:28 2026 +0200
Commit:     Florent Kermarrec <florent@enjoy-digital.fr>
CommitDate: Mon May 11 12:18:29 2026 +0200

    packaging: add PyPI publishing workflow
    
    Add a GitHub Actions Trusted Publishing workflow for pythondata package releases.
    
    Add pyproject.toml build-system metadata so python -m build can create release artifacts consistently.
    
    Tighten source distributions by excluding generated bytecode and cache files.
+ RPM_EC=0
++ jobs -p
+ exit 0
Executing(%build): /bin/sh -e /var/tmp/rpm-tmp.LEGnD8
+ umask 022
+ cd /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build
+ cd litex-pythondata-cpu-cva6
+ CFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Wno-complain-wrong-lang -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -mbranch-protection=standard -fasynchronous-unwind-tables -fstack-clash-protection -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer'
+ LDFLAGS='-Wl,-z,relro -Wl,--as-needed  -Wl,-z,pack-relative-relocs -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -Wl,--build-id=sha1 -specs=/usr/lib/rpm/redhat/redhat-package-notes '
+ /usr/bin/python3 setup.py build '--executable=/usr/bin/python3 -sP'
running build
running build_py
creating build
creating build/lib
creating build/lib/pythondata_cpu_cva6
copying pythondata_cpu_cva6/__init__.py -> build/lib/pythondata_cpu_cva6
running egg_info
creating pythondata_cpu_cva6.egg-info
writing pythondata_cpu_cva6.egg-info/PKG-INFO
writing dependency_links to pythondata_cpu_cva6.egg-info/dependency_links.txt
writing top-level names to pythondata_cpu_cva6.egg-info/top_level.txt
writing manifest file 'pythondata_cpu_cva6.egg-info/SOURCES.txt'
reading manifest file 'pythondata_cpu_cva6.egg-info/SOURCES.txt'
reading manifest template 'MANIFEST.in'
warning: no previously-included files matching '*.py[cod]' found anywhere in distribution
warning: no previously-included files matching '__pycache__/*' found anywhere in distribution
adding license file 'LICENSE'
writing manifest file 'pythondata_cpu_cva6.egg-info/SOURCES.txt'
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.ci' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.ci' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.ci' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.ci' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.ci' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.common.local.techlib.fpga.rtl' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.common.local.techlib.fpga.rtl' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.common.local.techlib.fpga.rtl' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.common.local.techlib.fpga.rtl' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.common.local.techlib.fpga.rtl' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.common.local.util' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.common.local.util' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.common.local.util' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.common.local.util' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.common.local.util' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.core' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.core' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.core' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.cache_subsystem' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.core.cache_subsystem' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.cache_subsystem' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.core.cache_subsystem' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.cache_subsystem' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.cvxif_example' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.core.cvxif_example' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.cvxif_example' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.core.cvxif_example' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.cvxif_example' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.cvxif_example.include' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.core.cvxif_example.include' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.cvxif_example.include' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.core.cvxif_example.include' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.cvxif_example.include' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.example_tb.verilator_results' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.core.example_tb.verilator_results' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.example_tb.verilator_results' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.core.example_tb.verilator_results' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.example_tb.verilator_results' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.frontend' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.core.frontend' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.frontend' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.core.frontend' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.frontend' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.include' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.core.include' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.include' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.core.include' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.include' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.mmu_sv32' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.core.mmu_sv32' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.mmu_sv32' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.core.mmu_sv32' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.mmu_sv32' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.mmu_sv39' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.core.mmu_sv39' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.mmu_sv39' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.core.mmu_sv39' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.mmu_sv39' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.pmp' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.core.pmp' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.pmp' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.core.pmp' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.pmp' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.pmp.include' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.core.pmp.include' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.pmp.include' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.core.pmp.include' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.pmp.include' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.pmp.src' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.core.pmp.src' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.pmp.src' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.core.pmp.src' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.pmp.src' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.pmp.tb' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.core.pmp.tb' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.pmp.tb' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.core.pmp.tb' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.pmp.tb' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.bootrom' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.bootrom' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.bootrom' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.bootrom' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.bootrom' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.clint' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.clint' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.clint' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.clint' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.clint' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.constraints' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.constraints' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.constraints' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.constraints' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.constraints' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.scripts' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.scripts' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.scripts' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.scripts' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.scripts' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom.src' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom.src' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom.src' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom.src' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom.src' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter.tcl' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter.tcl' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter.tcl' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter.tcl' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter.tcl' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter.tcl' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter.tcl' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter.tcl' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter.tcl' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter.tcl' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master.tcl' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master.tcl' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master.tcl' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master.tcl' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master.tcl' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave.tcl' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave.tcl' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave.tcl' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave.tcl' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave.tcl' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio.tcl' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio.tcl' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio.tcl' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio.tcl' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio.tcl' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi.tcl' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi.tcl' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi.tcl' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi.tcl' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi.tcl' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen.tcl' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen.tcl' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen.tcl' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen.tcl' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen.tcl' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila.tcl' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila.tcl' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila.tcl' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila.tcl' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila.tcl' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3.tcl' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3.tcl' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3.tcl' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3.tcl' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3.tcl' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker.tcl' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker.tcl' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker.tcl' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker.tcl' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker.tcl' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.include' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.include' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.include' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.include' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.include' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.baremetal' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.baremetal' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.baremetal' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.baremetal' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.baremetal' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux.src' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux.src' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux.src' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux.src' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux.src' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.common' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.common' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.common' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.common' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.common' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.dpi' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.dpi' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.dpi' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.dpi' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.dpi' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache.hdl' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache.hdl' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache.hdl' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache.hdl' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache.hdl' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv.hdl' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv.hdl' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv.hdl' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv.hdl' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv.hdl' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache.hdl' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache.hdl' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache.hdl' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache.hdl' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache.hdl' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache.hdl' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache.hdl' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache.hdl' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache.hdl' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache.hdl' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
creating build/lib/pythondata_cpu_cva6/system_verilog
copying pythondata_cpu_cva6/system_verilog/.editorconfig -> build/lib/pythondata_cpu_cva6/system_verilog
copying pythondata_cpu_cva6/system_verilog/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog
copying pythondata_cpu_cva6/system_verilog/.gitlab-ci.yml -> build/lib/pythondata_cpu_cva6/system_verilog
copying pythondata_cpu_cva6/system_verilog/.gitmodules -> build/lib/pythondata_cpu_cva6/system_verilog
copying pythondata_cpu_cva6/system_verilog/Bender.yml -> build/lib/pythondata_cpu_cva6/system_verilog
copying pythondata_cpu_cva6/system_verilog/CHANGELOG.md -> build/lib/pythondata_cpu_cva6/system_verilog
copying pythondata_cpu_cva6/system_verilog/CODEOWNERS -> build/lib/pythondata_cpu_cva6/system_verilog
copying pythondata_cpu_cva6/system_verilog/CONTRIBUTING.md -> build/lib/pythondata_cpu_cva6/system_verilog
copying pythondata_cpu_cva6/system_verilog/Flist.ariane -> build/lib/pythondata_cpu_cva6/system_verilog
copying pythondata_cpu_cva6/system_verilog/LICENSE -> build/lib/pythondata_cpu_cva6/system_verilog
copying pythondata_cpu_cva6/system_verilog/LICENSE.Berkeley -> build/lib/pythondata_cpu_cva6/system_verilog
copying pythondata_cpu_cva6/system_verilog/LICENSE.SiFive -> build/lib/pythondata_cpu_cva6/system_verilog
copying pythondata_cpu_cva6/system_verilog/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog
copying pythondata_cpu_cva6/system_verilog/README.md -> build/lib/pythondata_cpu_cva6/system_verilog
copying pythondata_cpu_cva6/system_verilog/ariane.core -> build/lib/pythondata_cpu_cva6/system_verilog
copying pythondata_cpu_cva6/system_verilog/config_pkg_generator.py -> build/lib/pythondata_cpu_cva6/system_verilog
copying pythondata_cpu_cva6/system_verilog/init_testharness.do -> build/lib/pythondata_cpu_cva6/system_verilog
copying pythondata_cpu_cva6/system_verilog/src_files.yml -> build/lib/pythondata_cpu_cva6/system_verilog
creating build/lib/pythondata_cpu_cva6/system_verilog/.github
creating build/lib/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE
copying pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE/bug.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE
copying pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE/task.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE
creating build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows
copying pythondata_cpu_cva6/system_verilog/.github/workflows/ci.yml -> build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows
creating build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci
copying pythondata_cpu_cva6/system_verilog/.gitlab-ci/core-v-verif-cva6.yml -> build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci
copying pythondata_cpu_cva6/system_verilog/.gitlab-ci/cva6.yml -> build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci
creating build/lib/pythondata_cpu_cva6/system_verilog/ci
copying pythondata_cpu_cva6/system_verilog/ci/build-riscv-gcc.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci
copying pythondata_cpu_cva6/system_verilog/ci/build-riscv-tests.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci
copying pythondata_cpu_cva6/system_verilog/ci/check-tests.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci
copying pythondata_cpu_cva6/system_verilog/ci/default.config -> build/lib/pythondata_cpu_cva6/system_verilog/ci
copying pythondata_cpu_cva6/system_verilog/ci/float.config -> build/lib/pythondata_cpu_cva6/system_verilog/ci
copying pythondata_cpu_cva6/system_verilog/ci/get-torture.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci
copying pythondata_cpu_cva6/system_verilog/ci/gitlab-ci-emul.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci
copying pythondata_cpu_cva6/system_verilog/ci/install-dtc.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci
copying pythondata_cpu_cva6/system_verilog/ci/install-fesvr.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci
copying pythondata_cpu_cva6/system_verilog/ci/install-riscvpk.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci
copying pythondata_cpu_cva6/system_verilog/ci/install-spike.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci
copying pythondata_cpu_cva6/system_verilog/ci/install-verilator.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci
copying pythondata_cpu_cva6/system_verilog/ci/make-tmp.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci
copying pythondata_cpu_cva6/system_verilog/ci/path-setup.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci
copying pythondata_cpu_cva6/system_verilog/ci/riscv-amo-tests.list -> build/lib/pythondata_cpu_cva6/system_verilog/ci
copying pythondata_cpu_cva6/system_verilog/ci/riscv-asm-tests.list -> build/lib/pythondata_cpu_cva6/system_verilog/ci
copying pythondata_cpu_cva6/system_verilog/ci/riscv-benchmarks.list -> build/lib/pythondata_cpu_cva6/system_verilog/ci
copying pythondata_cpu_cva6/system_verilog/ci/riscv-fp-tests.list -> build/lib/pythondata_cpu_cva6/system_verilog/ci
copying pythondata_cpu_cva6/system_verilog/ci/riscv-mul-tests.list -> build/lib/pythondata_cpu_cva6/system_verilog/ci
copying pythondata_cpu_cva6/system_verilog/ci/setup.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci
copying pythondata_cpu_cva6/system_verilog/ci/torture_make.patch -> build/lib/pythondata_cpu_cva6/system_verilog/ci
copying pythondata_cpu_cva6/system_verilog/ci/travis-ci-emul.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci
creating build/lib/pythondata_cpu_cva6/system_verilog/common
creating build/lib/pythondata_cpu_cva6/system_verilog/common/local
creating build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib
creating build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga
creating build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl
copying pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl/SyncDpRam.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl
copying pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl/SyncSpRam.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl
copying pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl/SyncSpRamBeNx32.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl
copying pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl/SyncSpRamBeNx64.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl
copying pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl/SyncTpRam.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl
creating build/lib/pythondata_cpu_cva6/system_verilog/common/local/util
copying pythondata_cpu_cva6/system_verilog/common/local/util/ex_trace_item.svh -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util
copying pythondata_cpu_cva6/system_verilog/common/local/util/find_first_one.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util
copying pythondata_cpu_cva6/system_verilog/common/local/util/instr_trace_item.svh -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util
copying pythondata_cpu_cva6/system_verilog/common/local/util/instr_tracer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util
copying pythondata_cpu_cva6/system_verilog/common/local/util/instr_tracer_if.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util
copying pythondata_cpu_cva6/system_verilog/common/local/util/sram.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util
copying pythondata_cpu_cva6/system_verilog/common/local/util/tc_sram_fpga_wrapper.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util
copying pythondata_cpu_cva6/system_verilog/common/local/util/tc_sram_wrapper.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util
creating build/lib/pythondata_cpu_cva6/system_verilog/core
copying pythondata_cpu_cva6/system_verilog/core/Flist.cv32a60x -> build/lib/pythondata_cpu_cva6/system_verilog/core
copying pythondata_cpu_cva6/system_verilog/core/Flist.cv32a60x_gate -> build/lib/pythondata_cpu_cva6/system_verilog/core
copying pythondata_cpu_cva6/system_verilog/core/Flist.cv32a6_imac_sv0 -> build/lib/pythondata_cpu_cva6/system_verilog/core
copying pythondata_cpu_cva6/system_verilog/core/Flist.cv32a6_imac_sv32 -> build/lib/pythondata_cpu_cva6/system_verilog/core
copying pythondata_cpu_cva6/system_verilog/core/Flist.cv32a6_imafc_sv32 -> build/lib/pythondata_cpu_cva6/system_verilog/core
copying pythondata_cpu_cva6/system_verilog/core/Flist.cv64a6_imafdc_sv39 -> build/lib/pythondata_cpu_cva6/system_verilog/core
copying pythondata_cpu_cva6/system_verilog/core/Flist.cv64a6_imafdc_sv39_gate -> build/lib/pythondata_cpu_cva6/system_verilog/core
copying pythondata_cpu_cva6/system_verilog/core/alu.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core
copying pythondata_cpu_cva6/system_verilog/core/amo_buffer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core
copying pythondata_cpu_cva6/system_verilog/core/ariane.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core
copying pythondata_cpu_cva6/system_verilog/core/ariane_regfile.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core
copying pythondata_cpu_cva6/system_verilog/core/ariane_regfile_ff.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core
copying pythondata_cpu_cva6/system_verilog/core/axi_adapter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core
copying pythondata_cpu_cva6/system_verilog/core/axi_shim.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core
copying pythondata_cpu_cva6/system_verilog/core/branch_unit.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core
copying pythondata_cpu_cva6/system_verilog/core/commit_stage.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core
copying pythondata_cpu_cva6/system_verilog/core/compressed_decoder.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core
copying pythondata_cpu_cva6/system_verilog/core/controller.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core
copying pythondata_cpu_cva6/system_verilog/core/csr_buffer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core
copying pythondata_cpu_cva6/system_verilog/core/csr_regfile.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core
copying pythondata_cpu_cva6/system_verilog/core/cva6.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core
copying pythondata_cpu_cva6/system_verilog/core/cvxif_fu.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core
copying pythondata_cpu_cva6/system_verilog/core/decoder.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core
copying pythondata_cpu_cva6/system_verilog/core/dromajo_ram.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core
copying pythondata_cpu_cva6/system_verilog/core/ex_stage.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core
copying pythondata_cpu_cva6/system_verilog/core/fpu_wrap.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core
copying pythondata_cpu_cva6/system_verilog/core/id_stage.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core
copying pythondata_cpu_cva6/system_verilog/core/instr_realign.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core
copying pythondata_cpu_cva6/system_verilog/core/issue_read_operands.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core
copying pythondata_cpu_cva6/system_verilog/core/issue_stage.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core
copying pythondata_cpu_cva6/system_verilog/core/load_store_unit.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core
copying pythondata_cpu_cva6/system_verilog/core/load_unit.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core
copying pythondata_cpu_cva6/system_verilog/core/lsu_bypass.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core
copying pythondata_cpu_cva6/system_verilog/core/mult.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core
copying pythondata_cpu_cva6/system_verilog/core/multiplier.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core
copying pythondata_cpu_cva6/system_verilog/core/perf_counters.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core
copying pythondata_cpu_cva6/system_verilog/core/re_name.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core
copying pythondata_cpu_cva6/system_verilog/core/scoreboard.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core
copying pythondata_cpu_cva6/system_verilog/core/serdiv.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core
copying pythondata_cpu_cva6/system_verilog/core/store_buffer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core
copying pythondata_cpu_cva6/system_verilog/core/store_unit.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core
creating build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem
copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/amo_alu.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem
copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cache_ctrl.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem
copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cva6_icache.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem
copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cva6_icache_axi_wrapper.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem
copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/miss_handler.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem
copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/std_cache_subsystem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem
copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/std_nbdcache.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem
copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/std_no_dcache.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem
copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/tag_cmp.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem
copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_axi_adapter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem
copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_cache_subsystem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem
copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem
copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_ctrl.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem
copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_mem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem
copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_missunit.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem
copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_wbuffer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem
copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_l15_adapter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem
creating build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example
copying pythondata_cpu_cva6/system_verilog/core/cvxif_example/cvxif_example_coprocessor.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example
copying pythondata_cpu_cva6/system_verilog/core/cvxif_example/instr_decoder.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example
creating build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example/include
copying pythondata_cpu_cva6/system_verilog/core/cvxif_example/include/cvxif_instr_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example/include
creating build/lib/pythondata_cpu_cva6/system_verilog/core/example_tb
creating build/lib/pythondata_cpu_cva6/system_verilog/core/example_tb/verilator_results
copying pythondata_cpu_cva6/system_verilog/core/example_tb/verilator_results/Vcva6_core_only_tb -> build/lib/pythondata_cpu_cva6/system_verilog/core/example_tb/verilator_results
creating build/lib/pythondata_cpu_cva6/system_verilog/core/frontend
copying pythondata_cpu_cva6/system_verilog/core/frontend/bht.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/frontend
copying pythondata_cpu_cva6/system_verilog/core/frontend/btb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/frontend
copying pythondata_cpu_cva6/system_verilog/core/frontend/frontend.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/frontend
copying pythondata_cpu_cva6/system_verilog/core/frontend/instr_queue.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/frontend
copying pythondata_cpu_cva6/system_verilog/core/frontend/instr_scan.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/frontend
copying pythondata_cpu_cva6/system_verilog/core/frontend/ras.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/frontend
creating build/lib/pythondata_cpu_cva6/system_verilog/core/include
copying pythondata_cpu_cva6/system_verilog/core/include/ariane_axi_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include
copying pythondata_cpu_cva6/system_verilog/core/include/ariane_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include
copying pythondata_cpu_cva6/system_verilog/core/include/ariane_rvfi_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include
copying pythondata_cpu_cva6/system_verilog/core/include/axi_intf.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include
copying pythondata_cpu_cva6/system_verilog/core/include/cv32a60x_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include
copying pythondata_cpu_cva6/system_verilog/core/include/cv32a6_imac_sv0_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include
copying pythondata_cpu_cva6/system_verilog/core/include/cv32a6_imac_sv32_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include
copying pythondata_cpu_cva6/system_verilog/core/include/cv32a6_imafc_sv32_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include
copying pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdc_sv39_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include
copying pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include
copying pythondata_cpu_cva6/system_verilog/core/include/cvxif_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include
copying pythondata_cpu_cva6/system_verilog/core/include/instr_tracer_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include
copying pythondata_cpu_cva6/system_verilog/core/include/riscv_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include
copying pythondata_cpu_cva6/system_verilog/core/include/std_cache_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include
copying pythondata_cpu_cva6/system_verilog/core/include/wt_cache_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include
creating build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv32
copying pythondata_cpu_cva6/system_verilog/core/mmu_sv32/cva6_mmu_sv32.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv32
copying pythondata_cpu_cva6/system_verilog/core/mmu_sv32/cva6_ptw_sv32.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv32
copying pythondata_cpu_cva6/system_verilog/core/mmu_sv32/cva6_tlb_sv32.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv32
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache.hdl' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache.hdl' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache.hdl' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache.hdl' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache.hdl' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.wave' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.wave' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.wave' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.wave' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.wave' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.docs' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.docs' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.docs' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.docs' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.docs' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.docs._static' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.docs._static' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.docs._static' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.docs._static' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.docs._static' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.docs.design_spec' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.docs.design_spec' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.docs.design_spec' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.docs.design_spec' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.docs.design_spec' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.docs.design_spec.images' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.docs.design_spec.images' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.docs.design_spec.images' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.docs.design_spec.images' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.docs.design_spec.images' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.docs.design_spec.source' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.docs.design_spec.source' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.docs.design_spec.source' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.docs.design_spec.source' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.docs.design_spec.source' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.docs.specifications' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.docs.specifications' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.docs.specifications' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.docs.specifications' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.docs.specifications' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.docs.specifications.images' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.docs.specifications.images' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.docs.specifications.images' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.docs.specifications.images' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.docs.specifications.images' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.docs.user_guide' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.docs.user_guide' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.docs.user_guide' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.docs.user_guide' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.docs.user_guide' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.pd.synth' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.pd.synth' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.pd.synth' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.pd.synth' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.pd.synth' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.pd.synth.scripts' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.pd.synth.scripts' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.pd.synth.scripts' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.pd.synth.scripts' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.pd.synth.scripts' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
/usr/lib/python3.13/site-packages/setuptools/command/build_py.py:218: _Warning: Package 'pythondata_cpu_cva6.system_verilog.scripts' is absent from the `packages` configuration.
!!

        ********************************************************************************
        ############################
        # Package would be ignored #
        ############################
        Python recognizes 'pythondata_cpu_cva6.system_verilog.scripts' as an importable package[^1],
        but it is absent from setuptools' `packages` configuration.

        This leads to an ambiguous overall configuration. If you want to distribute this
        package, please make sure that 'pythondata_cpu_cva6.system_verilog.scripts' is explicitly added
        to the `packages` configuration field.

        Alternatively, you can also rely on setuptools' discovery methods
        (for example by using `find_namespace_packages(...)`/`find_namespace:`
        instead of `find_packages(...)`/`find:`).

        You can read more about "package discovery" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html

        If you don't want 'pythondata_cpu_cva6.system_verilog.scripts' to be distributed and are
        already explicitly excluding 'pythondata_cpu_cva6.system_verilog.scripts' via
        `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`,
        you can try to use `exclude_package_data`, or `include-package-data=False` in
        combination with a more fine grained `package-data` configuration.

        You can read more about "package data files" on setuptools documentation page:

        - https://setuptools.pypa.io/en/latest/userguide/datafiles.html


        [^1]: For Python, any directory (with suitable naming) can be imported,
              even if it does not contain any `.py` files.
              On the other hand, currently there is no concept of package data
              directory, all directories are treated like packages.
        ********************************************************************************

!!
  check.warn(importable)
creating build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv39
copying pythondata_cpu_cva6/system_verilog/core/mmu_sv39/mmu.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv39
copying pythondata_cpu_cva6/system_verilog/core/mmu_sv39/ptw.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv39
copying pythondata_cpu_cva6/system_verilog/core/mmu_sv39/tlb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv39
creating build/lib/pythondata_cpu_cva6/system_verilog/core/pmp
copying pythondata_cpu_cva6/system_verilog/core/pmp/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp
copying pythondata_cpu_cva6/system_verilog/core/pmp/Bender.yml -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp
copying pythondata_cpu_cva6/system_verilog/core/pmp/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp
copying pythondata_cpu_cva6/system_verilog/core/pmp/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp
copying pythondata_cpu_cva6/system_verilog/core/pmp/formal.sby -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp
creating build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/include
copying pythondata_cpu_cva6/system_verilog/core/pmp/include/riscv.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/include
creating build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/src
copying pythondata_cpu_cva6/system_verilog/core/pmp/src/pmp.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/src
copying pythondata_cpu_cva6/system_verilog/core/pmp/src/pmp_entry.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/src
creating build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/tb
copying pythondata_cpu_cva6/system_verilog/core/pmp/tb/pmp_tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/tb
copying pythondata_cpu_cva6/system_verilog/core/pmp/tb/tb_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/tb
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom
copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom
copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom
copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/ariane.dts -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom
copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/bootrom.S -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom
copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/bootrom.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom
copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/bootrom.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom
copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/dromajo_bootrom.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom
copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/encoding.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom
copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/gen_rom.py -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom
copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/linker.ld -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/clint
copying pythondata_cpu_cva6/system_verilog/corev_apu/clint/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/clint
copying pythondata_cpu_cva6/system_verilog/corev_apu/clint/axi_lite_interface.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/clint
copying pythondata_cpu_cva6/system_verilog/corev_apu/clint/clint.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/clint
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane-multi-hart.cfg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane.cfg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane_pmod.cfg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane_pmod_tiny.cfg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/sourceme.sh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/ariane.xdc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/genesys-2.xdc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/kc705.xdc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/vc707.xdc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/vcu118.xdc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/check_fpga_boot.sh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/linux_boot.py -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/program.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/program_genesys2.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/prologue.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/write_cfgmem.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/ariane_peripherals_xilinx.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/ariane_xilinx.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/fan_ctrl.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/genesysii.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/kc705.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/vc707.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/vcu118.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/bootrom_32.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/bootrom_32.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/bootrom_64.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/bootrom_64.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/cv32a6.dts -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/cv64a6.dts -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/gen_rom.py -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/linker.lds -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/platform.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/startup.S -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/gpt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/gpt.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/main.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/sd.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/sd.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/smp.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/spi.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/spi.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/uart.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/uart.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/ariane_xlnx_ip.yml -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/common.mk -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/tcl
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/tcl
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/tcl
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/tcl
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/tcl
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/tcl
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/tcl
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/tcl
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/tcl
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/tcl
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/tcl
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/tcl
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_kc705.prj -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_vc707.prj -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/tcl
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/tcl
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/tcl
copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/tcl
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/include
copying pythondata_cpu_cva6/system_verilog/corev_apu/include/traced_instr_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/include
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton
copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/ariane_verilog_wrap.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton
copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/riscv_peripherals.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom
copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal
copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal
copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal
copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/bootrom.S -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal
copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/gen_rom.py -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal
copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/linker.ld -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux
copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux
copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux
copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux
copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/gen_rom.py -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux
copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/linker.lds -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux
copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/platform.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux
copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/startup.S -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src
copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/gpt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src
copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/gpt.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src
copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/main.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src
copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/sd.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src
copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/sd.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src
copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/smp.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src
copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/spi.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src
copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/spi.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src
copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/uart.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src
copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/uart.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_axi_soc_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_peripherals.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_soc_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_tb.cpp -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_testharness.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/rvfi_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/rvfi_tracer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/SimDTM.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/SimJTAG.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/assign.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/core_mem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/dp_ram.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/mock_uart.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/spike.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/string_buffer.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_amoport.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_dcache_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_readport.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_writeport.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/uart.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/SimDTM.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/SimJTAG.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/bootrom.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/dromajo_cosim_dpi.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/elfloader.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/msim_helper.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/msim_helper.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/remote_bitbang.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/remote_bitbang.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/sim_spike.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/sim_spike.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/spike.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/verilator.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/LICENSE -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/Makefile.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/aclocal.m4 -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/config.h.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/configure -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/configure.ac -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv-dummy_rocc.pc.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv-riscv.pc.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv-softfloat.pc.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv-spike.pc.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv-spike_main.pc.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom/debug_rom.S -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom/debug_rom.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom/link.ld -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc/dummy_rocc.ac -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc/dummy_rocc.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc/dummy_rocc.mk.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc/dummy_rocc_test.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/bootrom.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/cachesim.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/cachesim.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/clint.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/common.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/debug_defines.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/debug_module.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/debug_module.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/debug_rom_defines.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/decode.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/devices.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/devices.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/disasm.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/dts.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/dts.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/dump.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/encoding.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/execute.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/extension.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/extension.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/extensions.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/gen_icache -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insn_template.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insn_template.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/interactive.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/jtag_dtm.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/jtag_dtm.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/memtracer.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/mmu.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/mmu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/mulhi.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/opcodes.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/processor.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/processor.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/regnames.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/remote_bitbang.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/remote_bitbang.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/riscv.ac -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/riscv.mk.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/rocc.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/rocc.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/rom.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/sim.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/sim.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/simif.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/tracer.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/trap.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/trap.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/uart.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/add.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/addi.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/addiw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/addw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoadd_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoadd_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoand_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoand_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomax_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomax_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomaxu_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomaxu_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomin_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomin_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amominu_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amominu_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoor_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoor_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoswap_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoswap_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoxor_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoxor_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/and.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/andi.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/auipc.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/beq.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/bge.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/bgeu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/blt.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/bltu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/bne.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_add.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_addi.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_addi4spn.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_addw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_and.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_andi.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_beqz.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_bnez.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_ebreak.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fld.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fldsp.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_flw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_flwsp.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fsd.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fsdsp.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fsw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fswsp.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_j.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_jal.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_jalr.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_jr.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_li.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_lui.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_lw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_lwsp.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_mv.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_or.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_slli.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_srai.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_srli.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_sub.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_subw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_sw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_swsp.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_xor.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrc.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrci.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrs.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrsi.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrwi.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/div.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/divu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/divuw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/divw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/dret.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/ebreak.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/ecall.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fadd_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fadd_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fadd_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fclass_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fclass_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fclass_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_l.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_lu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_wu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_l_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_l_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_l_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_lu_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_lu_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_lu_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_l.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_lu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_wu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_l.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_lu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_wu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_w_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_w_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_w_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_wu_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_wu_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_wu_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fdiv_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fdiv_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fdiv_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fence.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fence_i.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/feq_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/feq_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/feq_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fld.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fle_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fle_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fle_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/flq.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/flt_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/flt_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/flt_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/flw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmadd_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmadd_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmadd_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmax_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmax_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmax_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmin_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmin_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmin_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmsub_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmsub_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmsub_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmul_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmul_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmul_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmv_d_x.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmv_w_x.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmv_x_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmv_x_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmadd_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmadd_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmadd_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmsub_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmsub_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmsub_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsd.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnj_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnj_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnj_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjn_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjn_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjn_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjx_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjx_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjx_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsq.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsqrt_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsqrt_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsqrt_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsub_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsub_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsub_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/jal.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/jalr.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lb.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lbu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/ld.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lh.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lhu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lr_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lr_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lui.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lwu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mret.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mul.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mulh.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mulhsu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mulhu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mulw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/or.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/ori.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/rem.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/remu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/remuw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/remw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sb.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sc_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sc_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sd.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sfence_vma.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sh.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sll.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/slli.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/slliw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sllw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/slt.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/slti.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sltiu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sltu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sra.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/srai.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sraiw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sraw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sret.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/srl.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/srli.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/srliw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/srlw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sub.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/subw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/wfi.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/xor.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/xori.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/config.guess -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/config.sub -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/install.sh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/mk-install-dirs.sh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/vcs-version.sh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_add.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_classify.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_div.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_eq.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_eq_signaling.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_isSignalingNaN.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_le.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_le_quiet.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_lt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_lt_quiet.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_mul.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_mulAdd.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_rem.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_roundToInt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_sqrt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_sub.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_f16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_f32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_f64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_i32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_i32_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_i64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_i64_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_ui32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_ui32_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_ui64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_ui64_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_add.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_div.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_eq.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_eq_signaling.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_isSignalingNaN.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_le.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_le_quiet.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_lt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_lt_quiet.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_mul.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_mulAdd.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_rem.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_roundToInt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_sqrt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_sub.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_f128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_f32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_f64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_i32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_i32_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_i64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_i64_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_ui32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_ui32_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_ui64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_ui64_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_add.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_classify.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_div.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_eq.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_eq_signaling.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_isSignalingNaN.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_le.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_le_quiet.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_lt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_lt_quiet.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_mul.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_mulAdd.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_rem.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_roundToInt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_sqrt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_sub.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_f128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_f16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_f64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_i32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_i32_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_i64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_i64_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_ui32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_ui32_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_ui64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_ui64_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_add.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_classify.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_div.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_eq.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_eq_signaling.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_isSignalingNaN.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_le.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_le_quiet.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_lt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_lt_quiet.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_mul.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_mulAdd.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_rem.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_roundToInt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_sqrt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_sub.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_f128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_f16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_f32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_i32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_i32_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_i64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_i64_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_ui32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_ui32_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_ui64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_ui64_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i32_to_f128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i32_to_f16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i32_to_f32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i32_to_f64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i64_to_f128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i64_to_f16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i64_to_f32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i64_to_f64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/internals.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/platform.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/primitiveTypes.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/primitives.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_add128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_add256M.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addCarryM.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addComplCarryM.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addM.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addMagsF128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addMagsF16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addMagsF32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addMagsF64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_approxRecip32_1.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_approxRecipSqrt32_1.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_approxRecipSqrt_1Ks.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_approxRecip_1Ks.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_commonNaNToF128UI.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_commonNaNToF16UI.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_commonNaNToF32UI.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_commonNaNToF64UI.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_compare128M.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_compare96M.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_countLeadingZeros16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_countLeadingZeros32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_countLeadingZeros64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_countLeadingZeros8.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_eq128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_f128UIToCommonNaN.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_f16UIToCommonNaN.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_f32UIToCommonNaN.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_f64UIToCommonNaN.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_le128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_lt128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul128By32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul128MTo256M.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul128To256M.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul64ByShifted32To128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul64To128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul64To128M.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mulAddF128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mulAddF16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mulAddF32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mulAddF64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_negXM.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normRoundPackToF128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normRoundPackToF16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normRoundPackToF32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normRoundPackToF64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normSubnormalF128Sig.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normSubnormalF16Sig.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normSubnormalF32Sig.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normSubnormalF64Sig.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_propagateNaNF128UI.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_propagateNaNF16UI.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_propagateNaNF32UI.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_propagateNaNF64UI.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_remStepMBy32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundMToI64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundMToUI64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackMToI64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackMToUI64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToF128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToF16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToF32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToF64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToI32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToI64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToUI32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToUI64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundToI32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundToI64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundToUI32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundToUI64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam128Extra.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam256M.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam64Extra.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftLeft128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftLeft64To96M.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRight128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightExtendM.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightJam128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightJam128Extra.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightJam64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightJam64Extra.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightM.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_sub128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_sub1XM.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_sub256M.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_subM.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_subMagsF128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_subMagsF16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_subMagsF32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_subMagsF64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat.ac -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat.mk.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat_raiseFlags.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat_state.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat_types.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/specialize.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui32_to_f128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui32_to_f16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui32_to_f32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui32_to_f64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui64_to_f128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui64_to_f16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui64_to_f32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui64_to_f64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/disasm.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/spike-dasm.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/spike.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/spike_main.ac -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/spike_main.mk.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/termios-xspike.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/xspike.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/ebreak.py -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/ebreak.s -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/tb.list -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/wave.do -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/mem_emul.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/tb_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/tlb_emul.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/tb.list -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_div.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_rem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_udiv.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_urem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/tb.list -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/wave.do -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl/tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/tb.list -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/wave.do -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/hdl
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/hdl/tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/hdl
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/tb.list -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/wave.do -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl/tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl/tb_mem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl
creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/wave
copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/wave/wave_core.do -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/wave
creating build/lib/pythondata_cpu_cva6/system_verilog/docs
copying pythondata_cpu_cva6/system_verilog/docs/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/docs
copying pythondata_cpu_cva6/system_verilog/docs/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/docs
copying pythondata_cpu_cva6/system_verilog/docs/commit_stage.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs
copying pythondata_cpu_cva6/system_verilog/docs/conf.py -> build/lib/pythondata_cpu_cva6/system_verilog/docs
copying pythondata_cpu_cva6/system_verilog/docs/cva6_soc.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs
copying pythondata_cpu_cva6/system_verilog/docs/ex_stage.md -> build/lib/pythondata_cpu_cva6/system_verilog/docs
copying pythondata_cpu_cva6/system_verilog/docs/id_stage.md -> build/lib/pythondata_cpu_cva6/system_verilog/docs
copying pythondata_cpu_cva6/system_verilog/docs/if_stage.md -> build/lib/pythondata_cpu_cva6/system_verilog/docs
copying pythondata_cpu_cva6/system_verilog/docs/index.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs
copying pythondata_cpu_cva6/system_verilog/docs/intro.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs
copying pythondata_cpu_cva6/system_verilog/docs/issue_stage.md -> build/lib/pythondata_cpu_cva6/system_verilog/docs
copying pythondata_cpu_cva6/system_verilog/docs/make.bat -> build/lib/pythondata_cpu_cva6/system_verilog/docs
copying pythondata_cpu_cva6/system_verilog/docs/pcgen_stage.md -> build/lib/pythondata_cpu_cva6/system_verilog/docs
copying pythondata_cpu_cva6/system_verilog/docs/requirements.txt -> build/lib/pythondata_cpu_cva6/system_verilog/docs
creating build/lib/pythondata_cpu_cva6/system_verilog/docs/_static
copying pythondata_cpu_cva6/system_verilog/docs/_static/ariane_overview.pdf -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static
copying pythondata_cpu_cva6/system_verilog/docs/_static/ariane_overview.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static
copying pythondata_cpu_cva6/system_verilog/docs/_static/bg.jpg -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static
copying pythondata_cpu_cva6/system_verilog/docs/_static/branch_prediction.pdf -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static
copying pythondata_cpu_cva6/system_verilog/docs/_static/branch_prediction.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static
copying pythondata_cpu_cva6/system_verilog/docs/_static/fpga_bd.pdf -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static
copying pythondata_cpu_cva6/system_verilog/docs/_static/fpga_bd.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static
copying pythondata_cpu_cva6/system_verilog/docs/_static/instr_realign.pdf -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static
copying pythondata_cpu_cva6/system_verilog/docs/_static/instr_realign.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static
copying pythondata_cpu_cva6/system_verilog/docs/_static/jekyll-dark.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static
copying pythondata_cpu_cva6/system_verilog/docs/_static/jekyll.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static
copying pythondata_cpu_cva6/system_verilog/docs/_static/ld_pipeline_diagram.svg -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static
copying pythondata_cpu_cva6/system_verilog/docs/_static/logonav.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static
copying pythondata_cpu_cva6/system_verilog/docs/_static/lsu_blockdiagram.pdf -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static
copying pythondata_cpu_cva6/system_verilog/docs/_static/lsu_blockdiagram.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static
copying pythondata_cpu_cva6/system_verilog/docs/_static/mmu_blockdiagramm.pdf -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static
copying pythondata_cpu_cva6/system_verilog/docs/_static/mmu_blockdiagramm.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static
copying pythondata_cpu_cva6/system_verilog/docs/_static/openhw-landscape.svg -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static
copying pythondata_cpu_cva6/system_verilog/docs/_static/scoreboard.pdf -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static
copying pythondata_cpu_cva6/system_verilog/docs/_static/scoreboard.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static
copying pythondata_cpu_cva6/system_verilog/docs/_static/uvm_fu_tb.ai -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static
copying pythondata_cpu_cva6/system_verilog/docs/_static/uvm_fu_tb.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static
creating build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec
copying pythondata_cpu_cva6/system_verilog/docs/design_spec/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec
copying pythondata_cpu_cva6/system_verilog/docs/design_spec/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec
copying pythondata_cpu_cva6/system_verilog/docs/design_spec/make.bat -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec
copying pythondata_cpu_cva6/system_verilog/docs/design_spec/requirements.txt -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec
creating build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images
copying pythondata_cpu_cva6/system_verilog/docs/design_spec/images/CVA6_subsystems.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images
copying pythondata_cpu_cva6/system_verilog/docs/design_spec/images/ariane_overview.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images
copying pythondata_cpu_cva6/system_verilog/docs/design_spec/images/bht.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images
copying pythondata_cpu_cva6/system_verilog/docs/design_spec/images/frontend_modules.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images
copying pythondata_cpu_cva6/system_verilog/docs/design_spec/images/jade_design_automation_logo.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images
copying pythondata_cpu_cva6/system_verilog/docs/design_spec/images/openhw-landscape.svg -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images
copying pythondata_cpu_cva6/system_verilog/docs/design_spec/images/subsystems.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images
creating build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source
copying pythondata_cpu_cva6/system_verilog/docs/design_spec/source/CV32A6_CSR.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source
copying pythondata_cpu_cva6/system_verilog/docs/design_spec/source/CV32A6_CSR.xml -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source
copying pythondata_cpu_cva6/system_verilog/docs/design_spec/source/conf.py -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source
copying pythondata_cpu_cva6/system_verilog/docs/design_spec/source/cva6_frontend.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source
copying pythondata_cpu_cva6/system_verilog/docs/design_spec/source/cva6_glossary.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source
copying pythondata_cpu_cva6/system_verilog/docs/design_spec/source/cva6_intro.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source
copying pythondata_cpu_cva6/system_verilog/docs/design_spec/source/cva6_system.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source
copying pythondata_cpu_cva6/system_verilog/docs/design_spec/source/index.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source
creating build/lib/pythondata_cpu_cva6/system_verilog/docs/specifications
copying pythondata_cpu_cva6/system_verilog/docs/specifications/cva6_requirement_specification.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/specifications
creating build/lib/pythondata_cpu_cva6/system_verilog/docs/specifications/images
copying pythondata_cpu_cva6/system_verilog/docs/specifications/images/cva6_scope.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/specifications/images
creating build/lib/pythondata_cpu_cva6/system_verilog/docs/user_guide
copying pythondata_cpu_cva6/system_verilog/docs/user_guide/cva6_ug_csr.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/user_guide
creating build/lib/pythondata_cpu_cva6/system_verilog/pd
creating build/lib/pythondata_cpu_cva6/system_verilog/pd/synth
copying pythondata_cpu_cva6/system_verilog/pd/synth/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth
copying pythondata_cpu_cva6/system_verilog/pd/synth/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth
copying pythondata_cpu_cva6/system_verilog/pd/synth/cva6_read.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth
copying pythondata_cpu_cva6/system_verilog/pd/synth/cva6_synth.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth
copying pythondata_cpu_cva6/system_verilog/pd/synth/tc_sram_wrapper_256_64_00000008_00000001_00000001_none_0.sv -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth
creating build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/scripts
copying pythondata_cpu_cva6/system_verilog/pd/synth/scripts/dc_setup.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/scripts
copying pythondata_cpu_cva6/system_verilog/pd/synth/scripts/dc_setup_filenames.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/scripts
copying pythondata_cpu_cva6/system_verilog/pd/synth/scripts/gate_analysis.py -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/scripts
creating build/lib/pythondata_cpu_cva6/system_verilog/scripts
copying pythondata_cpu_cva6/system_verilog/scripts/parse_ila_trace.py -> build/lib/pythondata_cpu_cva6/system_verilog/scripts
+ RPM_EC=0
++ jobs -p
+ exit 0
Executing(%install): /bin/sh -e /var/tmp/rpm-tmp.rl1TOq
+ umask 022
+ cd /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build
+ '[' /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT '!=' / ']'
+ rm -rf /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT
++ dirname /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT
+ mkdir -p /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build
+ mkdir /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT
+ cd litex-pythondata-cpu-cva6
+ CFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Wno-complain-wrong-lang -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -mbranch-protection=standard -fasynchronous-unwind-tables -fstack-clash-protection -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer'
+ LDFLAGS='-Wl,-z,relro -Wl,--as-needed  -Wl,-z,pack-relative-relocs -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -Wl,--build-id=sha1 -specs=/usr/lib/rpm/redhat/redhat-package-notes '
+ /usr/bin/python3 setup.py install -O1 --skip-build --root /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT --prefix /usr
running install
/usr/lib/python3.13/site-packages/setuptools/_distutils/cmd.py:66: SetuptoolsDeprecationWarning: setup.py install is deprecated.
!!

        ********************************************************************************
        Please avoid running ``setup.py`` directly.
        Instead, use pypa/build, pypa/installer or other
        standards-based tools.

        Follow the current Python packaging guidelines when building
        Python RPM packages.

        See https://blog.ganssle.io/articles/2021/10/setup-py-deprecated.html
        and https://docs.fedoraproject.org/en-US/packaging-guidelines/Python/ for details.
        ********************************************************************************

!!
  self.initialize_options()
running install_lib
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/scripts
copying build/lib/pythondata_cpu_cva6/system_verilog/scripts/parse_ila_trace.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/scripts
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/pd
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth/scripts
copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/scripts/gate_analysis.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth/scripts
copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/scripts/dc_setup_filenames.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth/scripts
copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/scripts/dc_setup.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth/scripts
copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/tc_sram_wrapper_256_64_00000008_00000001_00000001_none_0.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth
copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/cva6_synth.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth
copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/cva6_read.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth
copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth
copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/user_guide
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/user_guide/cva6_ug_csr.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/user_guide
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/specifications
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/specifications/images
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/specifications/images/cva6_scope.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/specifications/images
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/specifications/cva6_requirement_specification.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/specifications
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/index.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/cva6_system.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/cva6_intro.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/cva6_glossary.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/cva6_frontend.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/conf.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/CV32A6_CSR.xml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/CV32A6_CSR.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/images
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images/subsystems.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/images
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images/openhw-landscape.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/images
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images/jade_design_automation_logo.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/images
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images/frontend_modules.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/images
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images/bht.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/images
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images/ariane_overview.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/images
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images/CVA6_subsystems.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/images
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/requirements.txt -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/make.bat -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/uvm_fu_tb.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/uvm_fu_tb.ai -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/scoreboard.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/scoreboard.pdf -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/openhw-landscape.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/mmu_blockdiagramm.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/mmu_blockdiagramm.pdf -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/lsu_blockdiagram.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/lsu_blockdiagram.pdf -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/logonav.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/ld_pipeline_diagram.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/jekyll.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/jekyll-dark.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/instr_realign.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/instr_realign.pdf -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/fpga_bd.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/fpga_bd.pdf -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/branch_prediction.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/branch_prediction.pdf -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/bg.jpg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/ariane_overview.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/ariane_overview.pdf -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/requirements.txt -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/pcgen_stage.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/make.bat -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/issue_stage.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/intro.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/index.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/if_stage.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/id_stage.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/ex_stage.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/cva6_soc.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/conf.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/commit_stage.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs
copying build/lib/pythondata_cpu_cva6/system_verilog/docs/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/wave
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/wave/wave_core.do -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/wave
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl/tb_mem.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl/tb.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/wave.do -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/tb.list -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/hdl
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/hdl/tb.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/hdl
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/wave.do -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/tb.list -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl/tb.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/wave.do -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/tb.list -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_urem.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_udiv.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_rem.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_div.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/tb.list -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/tlb_emul.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/tb_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/tb.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/mem_emul.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/wave.do -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/tb.list -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/ebreak.s -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/ebreak.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/xspike.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/termios-xspike.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/spike_main.mk.in -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/spike_main.ac -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/spike.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/spike-dasm.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/disasm.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui64_to_f64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui64_to_f32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui64_to_f16.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui64_to_f128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui32_to_f64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui32_to_f32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui32_to_f16.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui32_to_f128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/specialize.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat_types.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat_state.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat_raiseFlags.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat.mk.in -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat.ac -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_subMagsF64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_subMagsF32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_subMagsF16.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_subMagsF128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_subM.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_sub256M.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_sub1XM.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_sub128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightM.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightJam64Extra.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightJam64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightJam128Extra.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightJam128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightExtendM.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRight128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftLeft64To96M.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftLeft128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam64Extra.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam256M.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam128Extra.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundToUI64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundToUI32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundToI64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundToI32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToUI64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToUI32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToI64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToI32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToF64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToF32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToF16.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToF128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackMToUI64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackMToI64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundMToUI64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundMToI64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_remStepMBy32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_propagateNaNF64UI.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_propagateNaNF32UI.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_propagateNaNF16UI.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_propagateNaNF128UI.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normSubnormalF64Sig.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normSubnormalF32Sig.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normSubnormalF16Sig.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normSubnormalF128Sig.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normRoundPackToF64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normRoundPackToF32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normRoundPackToF16.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normRoundPackToF128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_negXM.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mulAddF64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mulAddF32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mulAddF16.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mulAddF128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul64To128M.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul64To128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul64ByShifted32To128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul128To256M.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul128MTo256M.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul128By32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_lt128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_le128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_f64UIToCommonNaN.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_f32UIToCommonNaN.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_f16UIToCommonNaN.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_f128UIToCommonNaN.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_eq128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_countLeadingZeros8.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_countLeadingZeros64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_countLeadingZeros32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_countLeadingZeros16.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_compare96M.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_compare128M.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_commonNaNToF64UI.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_commonNaNToF32UI.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_commonNaNToF16UI.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_commonNaNToF128UI.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_approxRecip_1Ks.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_approxRecipSqrt_1Ks.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_approxRecipSqrt32_1.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_approxRecip32_1.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addMagsF64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addMagsF32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addMagsF16.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addMagsF128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addM.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addComplCarryM.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addCarryM.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_add256M.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_add128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/primitives.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/primitiveTypes.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/platform.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/internals.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i64_to_f64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i64_to_f32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i64_to_f16.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i64_to_f128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i32_to_f64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i32_to_f32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i32_to_f16.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i32_to_f128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_ui64_r_minMag.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_ui64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_ui32_r_minMag.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_ui32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_i64_r_minMag.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_i64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_i32_r_minMag.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_i32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_f32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_f16.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_f128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_sub.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_sqrt.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_roundToInt.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_rem.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_mulAdd.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_mul.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_lt_quiet.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_lt.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_le_quiet.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_le.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_isSignalingNaN.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_eq_signaling.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_eq.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_div.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_classify.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_add.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_ui64_r_minMag.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_ui64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_ui32_r_minMag.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_ui32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_i64_r_minMag.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_i64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_i32_r_minMag.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_i32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_f64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_f16.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_f128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_sub.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_sqrt.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_roundToInt.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_rem.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_mulAdd.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_mul.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_lt_quiet.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_lt.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_le_quiet.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_le.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_isSignalingNaN.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_eq_signaling.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_eq.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_div.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_classify.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_add.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_ui64_r_minMag.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_ui64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_ui32_r_minMag.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_ui32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_i64_r_minMag.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_i64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_i32_r_minMag.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_i32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_f64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_f32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_f128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_sub.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_sqrt.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_roundToInt.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_rem.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_mulAdd.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_mul.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_lt_quiet.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_lt.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_le_quiet.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_le.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_isSignalingNaN.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_eq_signaling.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_eq.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_div.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_add.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_ui64_r_minMag.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_ui64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_ui32_r_minMag.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_ui32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_i64_r_minMag.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_i64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_i32_r_minMag.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_i32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_f64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_f32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_f16.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_sub.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_sqrt.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_roundToInt.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_rem.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_mulAdd.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_mul.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_lt_quiet.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_lt.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_le_quiet.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_le.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_isSignalingNaN.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_eq_signaling.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_eq.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_div.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_classify.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_add.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/vcs-version.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/mk-install-dirs.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/install.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/config.sub -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/config.guess -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/xori.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/xor.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/wfi.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/subw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sub.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/srlw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/srliw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/srli.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/srl.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sret.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sraw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sraiw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/srai.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sra.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sltu.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sltiu.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/slti.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/slt.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sllw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/slliw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/slli.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sll.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sh.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sfence_vma.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sd.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sc_w.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sc_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sb.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/remw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/remuw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/remu.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/rem.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/ori.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/or.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mulw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mulhu.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mulhsu.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mulh.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mul.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mret.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lwu.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lui.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lr_w.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lr_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lhu.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lh.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/ld.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lbu.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lb.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/jalr.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/jal.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsub_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsub_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsub_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsqrt_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsqrt_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsqrt_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsq.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjx_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjx_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjx_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjn_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjn_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjn_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnj_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnj_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnj_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsd.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmsub_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmsub_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmsub_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmadd_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmadd_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmadd_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmv_x_w.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmv_x_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmv_w_x.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmv_d_x.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmul_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmul_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmul_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmsub_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmsub_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmsub_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmin_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmin_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmin_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmax_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmax_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmax_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmadd_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmadd_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmadd_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/flw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/flt_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/flt_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/flt_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/flq.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fle_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fle_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fle_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fld.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/feq_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/feq_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/feq_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fence_i.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fence.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fdiv_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fdiv_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fdiv_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_wu_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_wu_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_wu_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_w_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_w_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_w_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_wu.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_w.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_lu.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_l.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_wu.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_w.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_lu.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_l.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_lu_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_lu_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_lu_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_l_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_l_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_l_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_wu.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_w.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_lu.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_l.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fclass_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fclass_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fclass_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fadd_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fadd_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fadd_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/ecall.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/ebreak.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/dret.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/divw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/divuw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/divu.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/div.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrwi.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrsi.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrs.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrci.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrc.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_xor.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_swsp.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_sw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_subw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_sub.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_srli.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_srai.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_slli.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_or.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_mv.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_lwsp.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_lw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_lui.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_li.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_jr.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_jalr.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_jal.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_j.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fswsp.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fsw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fsdsp.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fsd.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_flwsp.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_flw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fldsp.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fld.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_ebreak.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_bnez.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_beqz.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_andi.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_and.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_addw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_addi4spn.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_addi.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_add.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/bne.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/bltu.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/blt.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/bgeu.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/bge.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/beq.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/auipc.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/andi.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/and.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoxor_w.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoxor_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoswap_w.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoswap_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoor_w.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoor_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amominu_w.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amominu_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomin_w.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomin_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomaxu_w.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomaxu_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomax_w.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomax_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoand_w.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoand_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoadd_w.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoadd_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/addw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/addiw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/addi.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/add.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/uart.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/trap.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/trap.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/tracer.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/simif.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/sim.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/sim.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/rom.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/rocc.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/rocc.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/riscv.mk.in -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/riscv.ac -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/remote_bitbang.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/remote_bitbang.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/regnames.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/processor.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/processor.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/opcodes.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/mulhi.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/mmu.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/mmu.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/memtracer.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/jtag_dtm.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/jtag_dtm.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/interactive.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insn_template.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insn_template.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/gen_icache -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/extensions.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/extension.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/extension.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/execute.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/encoding.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/dump.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/dts.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/dts.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/disasm.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/devices.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/devices.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/decode.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/debug_rom_defines.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/debug_module.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/debug_module.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/debug_defines.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/common.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/clint.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/cachesim.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/cachesim.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/bootrom.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc/dummy_rocc_test.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc/dummy_rocc.mk.in -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc/dummy_rocc.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc/dummy_rocc.ac -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom/link.ld -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom/debug_rom.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom/debug_rom.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv-spike_main.pc.in -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv-spike.pc.in -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv-softfloat.pc.in -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv-riscv.pc.in -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv-dummy_rocc.pc.in -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/configure.ac -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/configure -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/config.h.in -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/aclocal.m4 -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/Makefile.in -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/LICENSE -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/verilator.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/spike.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/sim_spike.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/sim_spike.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/remote_bitbang.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/remote_bitbang.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/msim_helper.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/msim_helper.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/elfloader.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/dromajo_cosim_dpi.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/bootrom.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/SimJTAG.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/SimDTM.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/uart.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_writeport.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_readport.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_dcache_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_amoport.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb.svh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/string_buffer.svh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/spike.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/mock_uart.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/dp_ram.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/core_mem.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/assign.svh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/SimJTAG.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/SimDTM.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/rvfi_tracer.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/rvfi_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_testharness.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_tb.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_tb.cpp -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_soc_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_peripherals.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_axi_soc_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/uart.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/uart.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/spi.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/spi.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/smp.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/sd.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/sd.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/main.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/gpt.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/gpt.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/startup.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/platform.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/linker.lds -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/gen_rom.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/linker.ld -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/gen_rom.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/bootrom.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/riscv_peripherals.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/ariane_verilog_wrap.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/include
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/include/traced_instr_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/include
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/tcl
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/tcl/run.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/tcl
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/tcl
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/tcl/run.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/tcl
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_vc707.prj -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_kc705.prj -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/tcl
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/tcl/run.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/tcl
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/tcl
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/tcl/run.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/tcl
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/tcl
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/tcl/run.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/tcl
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/tcl
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/tcl/run.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/tcl
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl/run.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl/run.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/tcl
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/tcl/run.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/tcl
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/tcl
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/tcl/run.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/tcl
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/common.mk -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/ariane_xlnx_ip.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/uart.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/uart.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/spi.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/spi.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/smp.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/sd.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/sd.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/main.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/gpt.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/gpt.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/startup.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/platform.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/linker.lds -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/gen_rom.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/cv64a6.dts -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/cv32a6.dts -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/bootrom_64.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/bootrom_64.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/bootrom_32.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/bootrom_32.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/vcu118.svh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/vc707.svh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/kc705.svh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/genesysii.svh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/fan_ctrl.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/ariane_xilinx.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/ariane_peripherals_xilinx.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/write_cfgmem.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/run.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/prologue.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/program_genesys2.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/program.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/linux_boot.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/check_fpga_boot.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/vcu118.xdc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/vc707.xdc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/kc705.xdc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/genesys-2.xdc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/ariane.xdc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/sourceme.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane_pmod_tiny.cfg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane_pmod.cfg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane.cfg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane-multi-hart.cfg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/clint
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/clint/clint.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/clint
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/clint/axi_lite_interface.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/clint
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/clint/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/clint
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/linker.ld -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/gen_rom.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/encoding.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/dromajo_bootrom.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/bootrom.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/bootrom.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/bootrom.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/ariane.dts -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom
copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/tb
copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/tb/tb_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/tb
copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/tb/pmp_tb.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/tb
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/src
copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/src/pmp_entry.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/src
copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/src/pmp.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/src
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/include
copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/include/riscv.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/include
copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/formal.sby -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp
copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp
copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp
copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/Bender.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp
copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/mmu_sv39
copying build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv39/tlb.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/mmu_sv39
copying build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv39/ptw.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/mmu_sv39
copying build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv39/mmu.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/mmu_sv39
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/mmu_sv32
copying build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv32/cva6_tlb_sv32.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/mmu_sv32
copying build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv32/cva6_ptw_sv32.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/mmu_sv32
copying build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv32/cva6_mmu_sv32.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/mmu_sv32
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/include
copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/wt_cache_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/include
copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/std_cache_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/include
copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/riscv_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/include
copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/instr_tracer_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/include
copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cvxif_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/include
copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/include
copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdc_sv39_config_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/include
copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv32a6_imafc_sv32_config_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/include
copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv32a6_imac_sv32_config_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/include
copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv32a6_imac_sv0_config_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/include
copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv32a60x_config_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/include
copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/axi_intf.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/include
copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/ariane_rvfi_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/include
copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/ariane_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/include
copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/ariane_axi_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/include
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/frontend
copying build/lib/pythondata_cpu_cva6/system_verilog/core/frontend/ras.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/frontend
copying build/lib/pythondata_cpu_cva6/system_verilog/core/frontend/instr_scan.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/frontend
copying build/lib/pythondata_cpu_cva6/system_verilog/core/frontend/instr_queue.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/frontend
copying build/lib/pythondata_cpu_cva6/system_verilog/core/frontend/frontend.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/frontend
copying build/lib/pythondata_cpu_cva6/system_verilog/core/frontend/btb.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/frontend
copying build/lib/pythondata_cpu_cva6/system_verilog/core/frontend/bht.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/frontend
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/example_tb
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/example_tb/verilator_results
copying build/lib/pythondata_cpu_cva6/system_verilog/core/example_tb/verilator_results/Vcva6_core_only_tb -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/example_tb/verilator_results
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/cvxif_example
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/cvxif_example/include
copying build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example/include/cvxif_instr_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/cvxif_example/include
copying build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example/instr_decoder.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/cvxif_example
copying build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example/cvxif_example_coprocessor.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/cvxif_example
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem
copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_l15_adapter.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem
copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_wbuffer.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem
copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_missunit.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem
copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_mem.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem
copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_ctrl.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem
copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem
copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_cache_subsystem.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem
copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_axi_adapter.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem
copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/tag_cmp.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem
copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/std_no_dcache.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem
copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/std_nbdcache.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem
copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/std_cache_subsystem.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem
copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/miss_handler.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem
copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cva6_icache_axi_wrapper.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem
copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cva6_icache.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem
copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cache_ctrl.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem
copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/amo_alu.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem
copying build/lib/pythondata_cpu_cva6/system_verilog/core/store_unit.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core
copying build/lib/pythondata_cpu_cva6/system_verilog/core/store_buffer.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core
copying build/lib/pythondata_cpu_cva6/system_verilog/core/serdiv.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core
copying build/lib/pythondata_cpu_cva6/system_verilog/core/scoreboard.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core
copying build/lib/pythondata_cpu_cva6/system_verilog/core/re_name.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core
copying build/lib/pythondata_cpu_cva6/system_verilog/core/perf_counters.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core
copying build/lib/pythondata_cpu_cva6/system_verilog/core/multiplier.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core
copying build/lib/pythondata_cpu_cva6/system_verilog/core/mult.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core
copying build/lib/pythondata_cpu_cva6/system_verilog/core/lsu_bypass.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core
copying build/lib/pythondata_cpu_cva6/system_verilog/core/load_unit.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core
copying build/lib/pythondata_cpu_cva6/system_verilog/core/load_store_unit.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core
copying build/lib/pythondata_cpu_cva6/system_verilog/core/issue_stage.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core
copying build/lib/pythondata_cpu_cva6/system_verilog/core/issue_read_operands.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core
copying build/lib/pythondata_cpu_cva6/system_verilog/core/instr_realign.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core
copying build/lib/pythondata_cpu_cva6/system_verilog/core/id_stage.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core
copying build/lib/pythondata_cpu_cva6/system_verilog/core/fpu_wrap.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core
copying build/lib/pythondata_cpu_cva6/system_verilog/core/ex_stage.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core
copying build/lib/pythondata_cpu_cva6/system_verilog/core/dromajo_ram.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core
copying build/lib/pythondata_cpu_cva6/system_verilog/core/decoder.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core
copying build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_fu.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core
copying build/lib/pythondata_cpu_cva6/system_verilog/core/cva6.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core
copying build/lib/pythondata_cpu_cva6/system_verilog/core/csr_regfile.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core
copying build/lib/pythondata_cpu_cva6/system_verilog/core/csr_buffer.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core
copying build/lib/pythondata_cpu_cva6/system_verilog/core/controller.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core
copying build/lib/pythondata_cpu_cva6/system_verilog/core/compressed_decoder.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core
copying build/lib/pythondata_cpu_cva6/system_verilog/core/commit_stage.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core
copying build/lib/pythondata_cpu_cva6/system_verilog/core/branch_unit.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core
copying build/lib/pythondata_cpu_cva6/system_verilog/core/axi_shim.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core
copying build/lib/pythondata_cpu_cva6/system_verilog/core/axi_adapter.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core
copying build/lib/pythondata_cpu_cva6/system_verilog/core/ariane_regfile_ff.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core
copying build/lib/pythondata_cpu_cva6/system_verilog/core/ariane_regfile.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core
copying build/lib/pythondata_cpu_cva6/system_verilog/core/ariane.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core
copying build/lib/pythondata_cpu_cva6/system_verilog/core/amo_buffer.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core
copying build/lib/pythondata_cpu_cva6/system_verilog/core/alu.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core
copying build/lib/pythondata_cpu_cva6/system_verilog/core/Flist.cv64a6_imafdc_sv39_gate -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core
copying build/lib/pythondata_cpu_cva6/system_verilog/core/Flist.cv64a6_imafdc_sv39 -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core
copying build/lib/pythondata_cpu_cva6/system_verilog/core/Flist.cv32a6_imafc_sv32 -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core
copying build/lib/pythondata_cpu_cva6/system_verilog/core/Flist.cv32a6_imac_sv32 -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core
copying build/lib/pythondata_cpu_cva6/system_verilog/core/Flist.cv32a6_imac_sv0 -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core
copying build/lib/pythondata_cpu_cva6/system_verilog/core/Flist.cv32a60x_gate -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core
copying build/lib/pythondata_cpu_cva6/system_verilog/core/Flist.cv32a60x -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/core
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/common
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/common/local
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util
copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/tc_sram_wrapper.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util
copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/tc_sram_fpga_wrapper.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util
copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/sram.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util
copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/instr_tracer_if.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util
copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/instr_tracer.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util
copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/instr_trace_item.svh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util
copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/find_first_one.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util
copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/ex_trace_item.svh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/common/local/techlib
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl
copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl/SyncTpRam.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl
copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl/SyncSpRamBeNx64.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl
copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl/SyncSpRamBeNx32.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl
copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl/SyncSpRam.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl
copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl/SyncDpRam.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/ci
copying build/lib/pythondata_cpu_cva6/system_verilog/ci/travis-ci-emul.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/ci
copying build/lib/pythondata_cpu_cva6/system_verilog/ci/torture_make.patch -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/ci
copying build/lib/pythondata_cpu_cva6/system_verilog/ci/setup.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/ci
copying build/lib/pythondata_cpu_cva6/system_verilog/ci/riscv-mul-tests.list -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/ci
copying build/lib/pythondata_cpu_cva6/system_verilog/ci/riscv-fp-tests.list -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/ci
copying build/lib/pythondata_cpu_cva6/system_verilog/ci/riscv-benchmarks.list -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/ci
copying build/lib/pythondata_cpu_cva6/system_verilog/ci/riscv-asm-tests.list -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/ci
copying build/lib/pythondata_cpu_cva6/system_verilog/ci/riscv-amo-tests.list -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/ci
copying build/lib/pythondata_cpu_cva6/system_verilog/ci/path-setup.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/ci
copying build/lib/pythondata_cpu_cva6/system_verilog/ci/make-tmp.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/ci
copying build/lib/pythondata_cpu_cva6/system_verilog/ci/install-verilator.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/ci
copying build/lib/pythondata_cpu_cva6/system_verilog/ci/install-spike.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/ci
copying build/lib/pythondata_cpu_cva6/system_verilog/ci/install-riscvpk.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/ci
copying build/lib/pythondata_cpu_cva6/system_verilog/ci/install-fesvr.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/ci
copying build/lib/pythondata_cpu_cva6/system_verilog/ci/install-dtc.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/ci
copying build/lib/pythondata_cpu_cva6/system_verilog/ci/gitlab-ci-emul.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/ci
copying build/lib/pythondata_cpu_cva6/system_verilog/ci/get-torture.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/ci
copying build/lib/pythondata_cpu_cva6/system_verilog/ci/float.config -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/ci
copying build/lib/pythondata_cpu_cva6/system_verilog/ci/default.config -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/ci
copying build/lib/pythondata_cpu_cva6/system_verilog/ci/check-tests.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/ci
copying build/lib/pythondata_cpu_cva6/system_verilog/ci/build-riscv-tests.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/ci
copying build/lib/pythondata_cpu_cva6/system_verilog/ci/build-riscv-gcc.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/ci
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci
copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/cva6.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci
copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/core-v-verif-cva6.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/.github
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/.github/workflows
copying build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows/ci.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/.github/workflows
creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE
copying build/lib/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE/task.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE
copying build/lib/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE/bug.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE
copying build/lib/pythondata_cpu_cva6/system_verilog/src_files.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog
copying build/lib/pythondata_cpu_cva6/system_verilog/init_testharness.do -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog
copying build/lib/pythondata_cpu_cva6/system_verilog/config_pkg_generator.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog
copying build/lib/pythondata_cpu_cva6/system_verilog/ariane.core -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog
copying build/lib/pythondata_cpu_cva6/system_verilog/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog
copying build/lib/pythondata_cpu_cva6/system_verilog/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog
copying build/lib/pythondata_cpu_cva6/system_verilog/LICENSE.SiFive -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog
copying build/lib/pythondata_cpu_cva6/system_verilog/LICENSE.Berkeley -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog
copying build/lib/pythondata_cpu_cva6/system_verilog/LICENSE -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog
copying build/lib/pythondata_cpu_cva6/system_verilog/Flist.ariane -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog
copying build/lib/pythondata_cpu_cva6/system_verilog/CONTRIBUTING.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog
copying build/lib/pythondata_cpu_cva6/system_verilog/CODEOWNERS -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog
copying build/lib/pythondata_cpu_cva6/system_verilog/CHANGELOG.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog
copying build/lib/pythondata_cpu_cva6/system_verilog/Bender.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog
copying build/lib/pythondata_cpu_cva6/system_verilog/.gitmodules -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog
copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog
copying build/lib/pythondata_cpu_cva6/system_verilog/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog
copying build/lib/pythondata_cpu_cva6/system_verilog/.editorconfig -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog
copying build/lib/pythondata_cpu_cva6/__init__.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6
byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/scripts/parse_ila_trace.py to parse_ila_trace.cpython-313.pyc
byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth/scripts/gate_analysis.py to gate_analysis.cpython-313.pyc
byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/conf.py to conf.cpython-313.pyc
byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/conf.py to conf.cpython-313.pyc
byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py to testlib.cpython-313.pyc
byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/ebreak.py to ebreak.cpython-313.pyc
byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/gen_rom.py to gen_rom.cpython-313.pyc
/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:86: SyntaxWarning: invalid escape sequence '\('
/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:91: SyntaxWarning: invalid escape sequence '\('
/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:103: SyntaxWarning: invalid escape sequence '\('
/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/config_pkg_generator.py:97: SyntaxWarning: invalid escape sequence '\g'
/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/config_pkg_generator.py:111: SyntaxWarning: invalid escape sequence '\g'
byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/gen_rom.py to gen_rom.cpython-313.pyc
byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/gen_rom.py to gen_rom.cpython-313.pyc
byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/linux_boot.py to linux_boot.cpython-313.pyc
byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/gen_rom.py to gen_rom.cpython-313.pyc
byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/config_pkg_generator.py to config_pkg_generator.cpython-313.pyc
byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/__init__.py to __init__.cpython-313.pyc
writing byte-compilation script '/tmp/tmp07_rslgu.py'
/usr/bin/python3 /tmp/tmp07_rslgu.py
/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:86: SyntaxWarning: invalid escape sequence '\('
/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:91: SyntaxWarning: invalid escape sequence '\('
/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:103: SyntaxWarning: invalid escape sequence '\('
/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/config_pkg_generator.py:97: SyntaxWarning: invalid escape sequence '\g'
/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/config_pkg_generator.py:111: SyntaxWarning: invalid escape sequence '\g'
removing /tmp/tmp07_rslgu.py
running install_egg_info
running egg_info
writing pythondata_cpu_cva6.egg-info/PKG-INFO
writing dependency_links to pythondata_cpu_cva6.egg-info/dependency_links.txt
writing top-level names to pythondata_cpu_cva6.egg-info/top_level.txt
reading manifest file 'pythondata_cpu_cva6.egg-info/SOURCES.txt'
reading manifest template 'MANIFEST.in'
warning: no previously-included files matching '*.py[cod]' found anywhere in distribution
warning: no previously-included files matching '__pycache__/*' found anywhere in distribution
adding license file 'LICENSE'
writing manifest file 'pythondata_cpu_cva6.egg-info/SOURCES.txt'
Copying pythondata_cpu_cva6.egg-info to /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6-4.2.0.post435-py3.13.egg-info
running install_scripts
+ rm -rfv /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/bin/__pycache__
+ sed -i /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/ebreak.py -e 's|#!/usr/bin/python|#!/usr/bin/python3|'
+ /usr/lib/rpm/check-buildroot
+ /usr/lib/rpm/redhat/brp-ldconfig
+ /usr/lib/rpm/brp-compress
+ /usr/lib/rpm/brp-strip /bin/true
+ /usr/lib/rpm/brp-strip-comment-note /bin/true /usr/bin/objdump
+ /usr/lib/rpm/redhat/brp-strip-lto /bin/true
+ /usr/lib/rpm/brp-strip-static-archive /bin/true
+ /usr/lib/rpm/check-rpaths
+ /usr/lib/rpm/redhat/brp-mangle-shebangs
mangling shebang in /usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/ci/build-riscv-gcc.sh from /bin/bash to #!/usr/bin/bash
mangling shebang in /usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/ci/build-riscv-tests.sh from /bin/bash to #!/usr/bin/bash
mangling shebang in /usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/ci/check-tests.sh from /bin/bash to #!/usr/bin/bash
mangling shebang in /usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/ci/get-torture.sh from /bin/bash to #!/usr/bin/bash
mangling shebang in /usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/ci/gitlab-ci-emul.sh from /bin/bash to #!/usr/bin/bash
mangling shebang in /usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/ci/install-dtc.sh from /bin/bash to #!/usr/bin/bash
mangling shebang in /usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/ci/install-fesvr.sh from /bin/bash to #!/usr/bin/bash
mangling shebang in /usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/ci/install-riscvpk.sh from /bin/bash to #!/usr/bin/bash
mangling shebang in /usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/ci/install-spike.sh from /bin/bash to #!/usr/bin/bash
mangling shebang in /usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/ci/install-verilator.sh from /bin/bash to #!/usr/bin/bash
mangling shebang in /usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/ci/make-tmp.sh from /bin/bash to #!/usr/bin/bash
mangling shebang in /usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/ci/setup.sh from /bin/bash to #!/usr/bin/bash
mangling shebang in /usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/gen_rom.py from /usr/bin/env python3 to #!/usr/bin/python3
mangling shebang in /usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/gen_rom.py from /usr/bin/env python3 to #!/usr/bin/python3
*** WARNING: ./usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj is executable but has no shebang, removing executable bit
mangling shebang in /usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/gen_rom.py from /usr/bin/env python3 to #!/usr/bin/python3
mangling shebang in /usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/gen_rom.py from /usr/bin/env python3 to #!/usr/bin/python3
mangling shebang in /usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/configure from /bin/sh to #!/usr/bin/sh
*** WARNING: ./usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom/debug_rom.S is executable but has no shebang, removing executable bit
mangling shebang in /usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/gen_icache from /bin/sh to #!/usr/bin/sh
mangling shebang in /usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/config.guess from /bin/sh to #!/usr/bin/sh
mangling shebang in /usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/config.sub from /bin/sh to #!/usr/bin/sh
mangling shebang in /usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/install.sh from /bin/sh to #!/usr/bin/sh
mangling shebang in /usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/mk-install-dirs.sh from /bin/sh to #!/usr/bin/sh
mangling shebang in /usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/vcs-version.sh from /bin/bash to #!/usr/bin/bash
*** WARNING: ./usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_classify.c is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_classify.c is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_classify.c is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/Makefile is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/Makefile is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/Makefile is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/Makefile is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/Makefile is executable but has no shebang, removing executable bit
*** WARNING: ./usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/scripts/parse_ila_trace.py is executable but has no shebang, removing executable bit
+ /usr/lib/rpm/brp-remove-la-files
+ env /usr/lib/rpm/redhat/brp-python-bytecompile '' 1 0 -j4
Bytecompiling .py files below /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13 using python3.13
/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/config_pkg_generator.py:97: SyntaxWarning: invalid escape sequence '\g'
/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/config_pkg_generator.py:111: SyntaxWarning: invalid escape sequence '\g'
/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/config_pkg_generator.py:97: SyntaxWarning: invalid escape sequence '\g'
/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/config_pkg_generator.py:111: SyntaxWarning: invalid escape sequence '\g'
/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:86: SyntaxWarning: invalid escape sequence '\('
/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:91: SyntaxWarning: invalid escape sequence '\('
/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:103: SyntaxWarning: invalid escape sequence '\('
/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:86: SyntaxWarning: invalid escape sequence '\('
/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:91: SyntaxWarning: invalid escape sequence '\('
/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:103: SyntaxWarning: invalid escape sequence '\('
+ /usr/lib/rpm/redhat/brp-python-hardlink
+ /usr/bin/add-determinism --brp -j4 /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT
/builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/__pycache__/__init__.cpython-313.opt-1.pyc: rewriting with normalized contents
/builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/__pycache__/config_pkg_generator.cpython-313.opt-1.pyc: rewriting with normalized contents
/builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/__pycache__/linux_boot.cpython-313.opt-1.pyc: rewriting with normalized contents
/builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/__pycache__/gen_rom.cpython-313.opt-1.pyc: rewriting with normalized contents
/builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/__pycache__/gen_rom.cpython-313.opt-1.pyc: rewriting with normalized contents
/builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/__pycache__/gen_rom.cpython-313.opt-1.pyc: rewriting with normalized contents
/builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/__pycache__/gen_rom.cpython-313.opt-1.pyc: rewriting with normalized contents
/builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/__pycache__/ebreak.cpython-313.opt-1.pyc: rewriting with normalized contents
/builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/__pycache__/conf.cpython-313.opt-1.pyc: rewriting with normalized contents
/builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/__pycache__/conf.cpython-313.opt-1.pyc: rewriting with normalized contents
/builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth/scripts/__pycache__/gate_analysis.cpython-313.opt-1.pyc: rewriting with normalized contents
/builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/scripts/__pycache__/parse_ila_trace.cpython-313.opt-1.pyc: rewriting with normalized contents
/builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/__pycache__/testlib.cpython-313.pyc: replacing with normalized version
/builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/lib/python3.13/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/__pycache__/testlib.cpython-313.opt-1.pyc: replacing with normalized version
Scanned 116 directories and 979 files,
               processed 14 inodes,
               14 modified (2 replaced + 12 rewritten),
               0 unsupported format, 0 errors
Processing files: litex-pythondata-cpu-cva6-python3-2025.12-20260511.0.git6b3a376b.fc42.noarch
Executing(%doc): /bin/sh -e /var/tmp/rpm-tmp.U1mqBL
+ umask 022
+ cd /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build
+ cd litex-pythondata-cpu-cva6
+ DOCDIR=/builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/share/doc/litex-pythondata-cpu-cva6-python3
+ export LC_ALL=C.UTF-8
+ LC_ALL=C.UTF-8
+ export DOCDIR
+ /usr/bin/mkdir -p /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/share/doc/litex-pythondata-cpu-cva6-python3
+ cp -pr /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/litex-pythondata-cpu-cva6/README.md /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/share/doc/litex-pythondata-cpu-cva6-python3
+ RPM_EC=0
++ jobs -p
+ exit 0
Executing(%license): /bin/sh -e /var/tmp/rpm-tmp.drKY0T
+ umask 022
+ cd /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build
+ cd litex-pythondata-cpu-cva6
+ LICENSEDIR=/builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/share/licenses/litex-pythondata-cpu-cva6-python3
+ export LC_ALL=C.UTF-8
+ LC_ALL=C.UTF-8
+ export LICENSEDIR
+ /usr/bin/mkdir -p /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/share/licenses/litex-pythondata-cpu-cva6-python3
+ cp -pr /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/litex-pythondata-cpu-cva6/LICENSE /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT/usr/share/licenses/litex-pythondata-cpu-cva6-python3
+ RPM_EC=0
++ jobs -p
+ exit 0
Provides: litex-pythondata-cpu-cva6-python3 = 2025.12-20260511.0.git6b3a376b.fc42 pythondata-cpu-cva6
Requires(rpmlib): rpmlib(CompressedFileNames) <= 3.0.4-1 rpmlib(FileDigests) <= 4.6.0-1 rpmlib(PartialHardlinkSets) <= 4.0.4-1 rpmlib(PayloadFilesHavePrefix) <= 4.0-1
warning: Arch dependent binaries in noarch package
Checking for unpackaged file(s): /usr/lib/rpm/check-files /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build/BUILDROOT
Wrote: /builddir/build/RPMS/litex-pythondata-cpu-cva6-python3-2025.12-20260511.0.git6b3a376b.fc42.noarch.rpm
Executing(rmbuild): /bin/sh -e /var/tmp/rpm-tmp.FAAchQ
+ umask 022
+ cd /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build
+ test -d /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build
+ /usr/bin/chmod -Rf a+rX,u+w,g-w,o-w /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build
+ rm -rf /builddir/build/BUILD/litex-pythondata-cpu-cva6-2025.12-build
+ RPM_EC=0
++ jobs -p
+ exit 0

RPM build warnings:
    Arch dependent binaries in noarch package
Finish: rpmbuild litex-pythondata-cpu-cva6-2025.12-20260511.0.git6b3a376b.fc42.src.rpm
Finish: build phase for litex-pythondata-cpu-cva6-2025.12-20260511.0.git6b3a376b.fc42.src.rpm
INFO: chroot_scan: 1 files copied to /var/lib/copr-rpmbuild/results/chroot_scan
INFO: /var/lib/mock/fedora-42-aarch64-1778795171.515428/root/var/log/dnf5.log
INFO: chroot_scan: creating tarball /var/lib/copr-rpmbuild/results/chroot_scan.tar.gz
/bin/tar: Removing leading `/' from member names
INFO: Done(/var/lib/copr-rpmbuild/results/litex-pythondata-cpu-cva6-2025.12-20260511.0.git6b3a376b.fc42.src.rpm) Config(child) 0 minutes 32 seconds
INFO: Results and/or logs in: /var/lib/copr-rpmbuild/results
INFO: Cleaning up build root ('cleanup_on_success=True')
Start: clean chroot
INFO: unmounting tmpfs.
Finish: clean chroot
Finish: run
Running RPMResults tool
Package info:
{
    "packages": [
        {
            "name": "litex-pythondata-cpu-cva6-python3",
            "epoch": null,
            "version": "2025.12",
            "release": "20260511.0.git6b3a376b.fc42",
            "arch": "noarch"
        },
        {
            "name": "litex-pythondata-cpu-cva6",
            "epoch": null,
            "version": "2025.12",
            "release": "20260511.0.git6b3a376b.fc42",
            "arch": "src"
        }
    ]
}
RPMResults finished