Warning: Permanently added '34.201.73.117' (ED25519) to the list of known hosts. Running (timeout=172800): unbuffer mock --spec /var/lib/copr-rpmbuild/workspace/workdir-80xpc3wc/litex-pythondata-cpu-cva6/litex-pythondata-cpu-cva6.spec --sources /var/lib/copr-rpmbuild/workspace/workdir-80xpc3wc/litex-pythondata-cpu-cva6 --resultdir /var/lib/copr-rpmbuild/results --uniqueext 1779852097.193724 -r /var/lib/copr-rpmbuild/results/configs/child.cfg INFO: mock.py version 6.7 starting (python version = 3.14.2, NVR = mock-6.7-1.fc43), args: /usr/libexec/mock/mock --spec /var/lib/copr-rpmbuild/workspace/workdir-80xpc3wc/litex-pythondata-cpu-cva6/litex-pythondata-cpu-cva6.spec --sources /var/lib/copr-rpmbuild/workspace/workdir-80xpc3wc/litex-pythondata-cpu-cva6 --resultdir /var/lib/copr-rpmbuild/results --uniqueext 1779852097.193724 -r /var/lib/copr-rpmbuild/results/configs/child.cfg Start(bootstrap): init plugins INFO: tmpfs initialized INFO: selinux enabled INFO: chroot_scan: initialized INFO: compress_logs: initialized Finish(bootstrap): init plugins Start: init plugins INFO: tmpfs initialized INFO: selinux enabled INFO: chroot_scan: initialized INFO: compress_logs: initialized Finish: init plugins INFO: Signal handler active Start: run INFO: Start(/var/lib/copr-rpmbuild/workspace/workdir-80xpc3wc/litex-pythondata-cpu-cva6/litex-pythondata-cpu-cva6.spec) Config(fedora-43-aarch64) Start: clean chroot Finish: clean chroot Mock Version: 6.7 INFO: Mock Version: 6.7 Start(bootstrap): chroot init INFO: mounting tmpfs at /var/lib/mock/fedora-43-aarch64-bootstrap-1779852097.193724/root. INFO: calling preinit hooks INFO: enabled root cache INFO: enabled package manager cache Start(bootstrap): cleaning package manager metadata Finish(bootstrap): cleaning package manager metadata INFO: Guessed host environment type: unknown INFO: Using container image: registry.fedoraproject.org/fedora:43 INFO: Pulling image: registry.fedoraproject.org/fedora:43 INFO: Tagging container image as mock-bootstrap-bfedd95a-1e50-4e78-b44e-452bdeb35863 INFO: Checking that ceae511cef048a631bd155d1ddbb93802e798fe4c5c43c6036b65b6ce5ceefba image matches host's architecture INFO: Copy content of container ceae511cef048a631bd155d1ddbb93802e798fe4c5c43c6036b65b6ce5ceefba to /var/lib/mock/fedora-43-aarch64-bootstrap-1779852097.193724/root INFO: mounting ceae511cef048a631bd155d1ddbb93802e798fe4c5c43c6036b65b6ce5ceefba with podman image mount INFO: image ceae511cef048a631bd155d1ddbb93802e798fe4c5c43c6036b65b6ce5ceefba as /var/lib/containers/storage/overlay/31c8550f4326ca0c7168d76dfcc041d18258375467faa027380a41001c4088a6/merged INFO: umounting image ceae511cef048a631bd155d1ddbb93802e798fe4c5c43c6036b65b6ce5ceefba (/var/lib/containers/storage/overlay/31c8550f4326ca0c7168d76dfcc041d18258375467faa027380a41001c4088a6/merged) with podman image umount INFO: Removing image mock-bootstrap-bfedd95a-1e50-4e78-b44e-452bdeb35863 INFO: Package manager dnf5 detected and used (fallback) INFO: Not updating bootstrap chroot, bootstrap_image_ready=True Start(bootstrap): creating root cache Finish(bootstrap): creating root cache Finish(bootstrap): chroot init Start: chroot init INFO: mounting tmpfs at /var/lib/mock/fedora-43-aarch64-1779852097.193724/root. INFO: calling preinit hooks INFO: enabled root cache INFO: enabled package manager cache Start: cleaning package manager metadata Finish: cleaning package manager metadata INFO: enabled HW Info plugin INFO: Package manager dnf5 detected and used (direct choice) INFO: Buildroot is handled by package management downloaded with a bootstrap image: rpm-6.0.1-1.fc43.aarch64 rpm-sequoia-1.10.2-1.fc43.aarch64 dnf5-5.2.18.0-3.fc43.aarch64 dnf5-plugins-5.2.18.0-3.fc43.aarch64 Start: installing minimal buildroot with dnf5 Updating and loading repositories: Copr repository 100% | 49.3 KiB/s | 1.5 KiB | 00m00s updates 100% | 55.0 KiB/s | 9.5 KiB | 00m00s fedora 100% | 145.5 KiB/s | 16.3 KiB | 00m00s Repositories loaded. Package Arch Version Repository Size Installing group/module packages: bash aarch64 5.3.0-2.fc43 fedora 8.4 MiB bzip2 aarch64 1.0.8-21.fc43 fedora 171.3 KiB coreutils aarch64 9.7-8.fc43 updates 8.2 MiB cpio aarch64 2.15-6.fc43 fedora 1.1 MiB diffutils aarch64 3.12-3.fc43 fedora 1.6 MiB fedora-release-common noarch 43-27 updates 20.6 KiB findutils aarch64 1:4.10.0-6.fc43 fedora 1.9 MiB gawk aarch64 5.3.2-2.fc43 fedora 2.6 MiB glibc-minimal-langpack aarch64 2.42-13.fc43 updates 0.0 B grep aarch64 3.12-2.fc43 fedora 1.0 MiB gzip aarch64 1.13-4.fc43 fedora 424.7 KiB info aarch64 7.2-7.fc43 updates 421.6 KiB patch aarch64 2.8-2.fc43 fedora 262.5 KiB redhat-rpm-config noarch 343-12.fc43 updates 182.9 KiB rpm-build aarch64 6.0.1-1.fc43 updates 599.0 KiB sed aarch64 4.9-5.fc43 fedora 873.2 KiB shadow-utils aarch64 2:4.18.0-3.fc43 fedora 4.4 MiB tar aarch64 2:1.35-6.fc43 fedora 3.0 MiB unzip aarch64 6.0-67.fc43 fedora 470.2 KiB util-linux aarch64 2.41.4-7.fc43 updates 6.8 MiB which aarch64 2.23-3.fc43 fedora 123.4 KiB xz aarch64 1:5.8.1-4.fc43 updates 1.4 MiB Installing dependencies: add-determinism aarch64 0.6.0-3.fc43 updates 2.0 MiB alternatives aarch64 1.33-3.fc43 updates 90.2 KiB ansible-srpm-macros noarch 1-18.1.fc43 fedora 35.7 KiB audit-libs aarch64 4.1.4-1.fc43 updates 486.9 KiB binutils aarch64 2.45.1-4.fc43 updates 31.0 MiB build-reproducibility-srpm-macros noarch 0.6.0-3.fc43 updates 735.0 B bzip2-libs aarch64 1.0.8-21.fc43 fedora 72.6 KiB ca-certificates noarch 2025.2.80_v9.0.304-1.2.fc43 updates 2.7 MiB coreutils-common aarch64 9.7-8.fc43 updates 11.3 MiB crypto-policies noarch 20251125-1.git63291f8.fc43 updates 147.1 KiB curl aarch64 8.15.0-7.fc43 updates 457.5 KiB cyrus-sasl-lib aarch64 2.1.28-33.fc43 fedora 2.4 MiB debugedit aarch64 5.2-3.fc43 fedora 317.9 KiB dwz aarch64 0.16-2.fc43 fedora 322.6 KiB ed aarch64 1.22.2-1.fc43 fedora 156.0 KiB efi-srpm-macros noarch 6-4.fc43 fedora 40.1 KiB elfutils aarch64 0.195-1.fc43 updates 3.6 MiB elfutils-debuginfod-client aarch64 0.195-1.fc43 updates 144.1 KiB elfutils-default-yama-scope noarch 0.195-1.fc43 updates 1.8 KiB elfutils-libelf aarch64 0.195-1.fc43 updates 1.2 MiB elfutils-libs aarch64 0.195-1.fc43 updates 746.7 KiB fedora-gpg-keys noarch 43-1 fedora 131.2 KiB fedora-release noarch 43-27 updates 0.0 B fedora-release-identity-basic noarch 43-27 updates 631.0 B fedora-repos noarch 43-1 fedora 4.9 KiB file aarch64 5.46-9.fc43 updates 140.2 KiB file-libs aarch64 5.46-9.fc43 updates 11.9 MiB filesystem aarch64 3.18-50.fc43 fedora 112.0 B filesystem-srpm-macros noarch 3.18-50.fc43 fedora 38.2 KiB fonts-srpm-macros noarch 1:2.0.5-23.fc43 fedora 55.8 KiB forge-srpm-macros noarch 0.4.0-3.fc43 fedora 38.9 KiB fpc-srpm-macros noarch 1.3-15.fc43 fedora 144.0 B gap-srpm-macros noarch 2-1.fc43 fedora 2.1 KiB gdb-minimal aarch64 17.1-4.fc43 updates 13.4 MiB gdbm-libs aarch64 1:1.23-10.fc43 fedora 233.9 KiB ghc-srpm-macros noarch 1.9.2-3.fc43 fedora 779.0 B glibc aarch64 2.42-13.fc43 updates 6.3 MiB glibc-common aarch64 2.42-13.fc43 updates 1.3 MiB glibc-gconv-extra aarch64 2.42-13.fc43 updates 18.5 MiB gmp aarch64 1:6.3.0-4.fc43 fedora 657.9 KiB gnat-srpm-macros noarch 7-1.fc43 updates 1.0 KiB gnulib-l10n noarch 20241231-1.fc43 fedora 655.0 KiB gnupg2 aarch64 2.4.9-5.fc43 updates 6.5 MiB gnupg2-dirmngr aarch64 2.4.9-5.fc43 updates 646.4 KiB gnupg2-gpg-agent aarch64 2.4.9-5.fc43 updates 847.3 KiB gnupg2-gpgconf aarch64 2.4.9-5.fc43 updates 321.9 KiB gnupg2-keyboxd aarch64 2.4.9-5.fc43 updates 233.3 KiB gnupg2-verify aarch64 2.4.9-5.fc43 updates 364.4 KiB gnutls aarch64 3.8.13-1.fc43 updates 3.7 MiB go-srpm-macros noarch 3.8.0-1.fc43 fedora 61.9 KiB gpgverify noarch 2.2-3.fc43 fedora 8.7 KiB ima-evm-utils-libs aarch64 1.6.2-6.fc43 fedora 92.7 KiB jansson aarch64 2.14-3.fc43 fedora 93.1 KiB java-srpm-macros noarch 1-7.fc43 fedora 870.0 B json-c aarch64 0.18-7.fc43 fedora 138.7 KiB kernel-srpm-macros noarch 1.0-27.fc43 fedora 1.9 KiB keyutils-libs aarch64 1.6.3-6.fc43 fedora 98.3 KiB krb5-libs aarch64 1.22.2-4.fc43 updates 2.5 MiB libacl aarch64 2.3.2-4.fc43 fedora 68.0 KiB libarchive aarch64 3.8.4-1.fc43 updates 975.3 KiB libassuan aarch64 2.5.7-4.fc43 fedora 215.8 KiB libattr aarch64 2.5.2-6.fc43 fedora 68.5 KiB libblkid aarch64 2.41.4-7.fc43 updates 290.5 KiB libbrotli aarch64 1.2.0-1.fc43 updates 909.5 KiB libcap aarch64 2.76-4.fc43 updates 508.8 KiB libcap-ng aarch64 0.9.3-1.fc43 updates 161.1 KiB libcom_err aarch64 1.47.3-2.fc43 fedora 111.2 KiB libcurl aarch64 8.15.0-7.fc43 updates 915.1 KiB libeconf aarch64 0.7.9-2.fc43 fedora 81.0 KiB libevent aarch64 2.1.12-16.fc43 fedora 1.1 MiB libfdisk aarch64 2.41.4-7.fc43 updates 418.9 KiB libffi aarch64 3.5.2-1.fc43 updates 155.9 KiB libfsverity aarch64 1.6-3.fc43 fedora 68.5 KiB libgcc aarch64 15.2.1-7.fc43 updates 222.2 KiB libgcrypt aarch64 1.11.1-4.fc43 updates 1.2 MiB libgomp aarch64 15.2.1-7.fc43 updates 517.0 KiB libgpg-error aarch64 1.55-2.fc43 fedora 971.3 KiB libidn2 aarch64 2.3.8-2.fc43 fedora 560.6 KiB libksba aarch64 1.6.7-4.fc43 fedora 398.4 KiB liblastlog2 aarch64 2.41.4-7.fc43 updates 138.0 KiB libmount aarch64 2.41.4-7.fc43 updates 420.2 KiB libnghttp2 aarch64 1.66.0-2.fc43 fedora 197.9 KiB libpkgconf aarch64 2.3.0-3.fc43 fedora 134.0 KiB libpsl aarch64 0.21.5-6.fc43 fedora 132.5 KiB libselinux aarch64 3.9-5.fc43 fedora 201.1 KiB libsemanage aarch64 3.9-4.fc43 fedora 360.2 KiB libsepol aarch64 3.9-2.fc43 fedora 809.8 KiB libsmartcols aarch64 2.41.4-7.fc43 updates 224.6 KiB libssh aarch64 0.11.4-1.fc43 updates 587.7 KiB libssh-config noarch 0.11.4-1.fc43 updates 277.0 B libstdc++ aarch64 15.2.1-7.fc43 updates 2.8 MiB libtasn1 aarch64 4.21.0-1.fc43 updates 220.8 KiB libtool-ltdl aarch64 2.5.4-8.fc43 updates 94.0 KiB libunistring aarch64 1.1-10.fc43 fedora 1.7 MiB libusb1 aarch64 1.0.29-4.fc43 fedora 178.9 KiB libuuid aarch64 2.41.4-7.fc43 updates 69.4 KiB libverto aarch64 0.3.2-11.fc43 fedora 69.4 KiB libxcrypt aarch64 4.5.2-1.fc43 updates 273.4 KiB libxml2 aarch64 2.12.10-5.fc43 fedora 1.9 MiB libzstd aarch64 1.5.7-2.fc43 fedora 667.7 KiB lua-libs aarch64 5.4.8-4.fc43 updates 329.9 KiB lua-srpm-macros noarch 1-16.fc43 fedora 1.3 KiB lz4-libs aarch64 1.10.0-3.fc43 fedora 197.4 KiB mpfr aarch64 4.2.2-2.fc43 fedora 755.5 KiB ncurses-base noarch 6.5-7.20250614.fc43 fedora 328.1 KiB ncurses-libs aarch64 6.5-7.20250614.fc43 fedora 1.2 MiB nettle aarch64 3.10.1-2.fc43 fedora 765.3 KiB npth aarch64 1.8-3.fc43 fedora 93.5 KiB ocaml-srpm-macros noarch 11-2.fc43 fedora 1.9 KiB openblas-srpm-macros noarch 2-20.fc43 fedora 112.0 B openldap aarch64 2.6.13-1.fc43 updates 764.2 KiB openssl-libs aarch64 1:3.5.4-3.fc43 updates 7.4 MiB p11-kit aarch64 0.26.2-1.fc43 updates 2.7 MiB p11-kit-trust aarch64 0.26.2-1.fc43 updates 530.3 KiB package-notes-srpm-macros noarch 0.5-15.fc43 updates 1.6 KiB pam-libs aarch64 1.7.1-4.fc43 updates 223.0 KiB pcre2 aarch64 10.47-1.fc43 updates 714.5 KiB pcre2-syntax noarch 10.47-1.fc43 updates 281.9 KiB perl-srpm-macros noarch 1-60.fc43 fedora 861.0 B pkgconf aarch64 2.3.0-3.fc43 fedora 112.4 KiB pkgconf-m4 noarch 2.3.0-3.fc43 fedora 14.4 KiB pkgconf-pkg-config aarch64 2.3.0-3.fc43 fedora 990.0 B popt aarch64 1.19-9.fc43 fedora 144.8 KiB publicsuffix-list-dafsa noarch 20260116-1.fc43 updates 70.4 KiB pyproject-srpm-macros noarch 1.22.1-1.fc43 updates 3.2 KiB python-srpm-macros noarch 3.14-5.fc43 fedora 51.5 KiB qt5-srpm-macros noarch 5.15.18-1.fc43 updates 500.0 B qt6-srpm-macros noarch 6.10.3-1.fc43 updates 472.0 B readline aarch64 8.3-2.fc43 fedora 563.8 KiB rpm aarch64 6.0.1-1.fc43 updates 3.4 MiB rpm-build-libs aarch64 6.0.1-1.fc43 updates 264.1 KiB rpm-libs aarch64 6.0.1-1.fc43 updates 995.5 KiB rpm-sequoia aarch64 1.10.2-2.fc43 updates 2.2 MiB rpm-sign-libs aarch64 6.0.1-1.fc43 updates 67.8 KiB rust-srpm-macros noarch 28.4-1.fc43 updates 5.5 KiB setup noarch 2.15.0-26.fc43 fedora 725.0 KiB sqlite-libs aarch64 3.50.2-2.fc43 fedora 1.5 MiB systemd-libs aarch64 258.7-1.fc43 updates 2.4 MiB systemd-standalone-sysusers aarch64 258.7-1.fc43 updates 329.6 KiB tpm2-tss aarch64 4.1.3-8.fc43 fedora 2.1 MiB tree-sitter-srpm-macros noarch 0.4.2-1.fc43 fedora 8.3 KiB util-linux-core aarch64 2.41.4-7.fc43 updates 2.4 MiB xxhash-libs aarch64 0.8.3-3.fc43 fedora 86.0 KiB xz-libs aarch64 1:5.8.1-4.fc43 updates 201.6 KiB zig-srpm-macros noarch 1-5.fc43 fedora 1.1 KiB zip aarch64 3.0-44.fc43 fedora 762.5 KiB zlib-ng-compat aarch64 2.3.3-2.fc43 updates 133.5 KiB zstd aarch64 1.5.7-2.fc43 fedora 1.5 MiB Installing groups: Buildsystem building group Transaction Summary: Installing: 170 packages Total size of inbound packages is 58 MiB. Need to download 0 B. After this operation, 227 MiB extra will be used (install 227 MiB, remove 0 B). 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B | 00m00s >>> Already downloaded [170/170] libbrotli-0:1.2.0-1.fc43.aarc 100% | 0.0 B/s | 0.0 B | 00m00s >>> Already downloaded -------------------------------------------------------------------------------- [170/170] Total 100% | 0.0 B/s | 0.0 B | 00m00s Running transaction Importing OpenPGP key 0x31645531: UserID : "Fedora (43) " Fingerprint: C6E7F081CF80E13146676E88829B606631645531 From : file:///usr/share/distribution-gpg-keys/fedora/RPM-GPG-KEY-fedora-43-primary The key was successfully imported. [ 1/172] Verify package files 100% | 805.0 B/s | 170.0 B | 00m00s [ 2/172] Prepare transaction 100% | 2.6 KiB/s | 170.0 B | 00m00s [ 3/172] Installing libgcc-0:15.2.1-7. 100% | 109.3 MiB/s | 223.9 KiB | 00m00s [ 4/172] Installing publicsuffix-list- 100% | 69.4 MiB/s | 71.1 KiB | 00m00s [ 5/172] Installing libssh-config-0:0. 100% | 0.0 B/s | 816.0 B | 00m00s [ 6/172] Installing fedora-release-ide 100% | 867.2 KiB/s | 888.0 B | 00m00s [ 7/172] Installing fedora-gpg-keys-0: 100% | 29.1 MiB/s | 179.0 KiB | 00m00s [ 8/172] Installing fedora-repos-0:43- 100% | 0.0 B/s | 5.7 KiB | 00m00s [ 9/172] Installing fedora-release-com 100% | 24.3 MiB/s | 24.8 KiB | 00m00s [ 10/172] Installing fedora-release-0:4 100% | 15.1 KiB/s | 124.0 B | 00m00s >>> Running sysusers scriptlet: setup-0:2.15.0-26.fc43.noarch >>> Finished sysusers scriptlet: setup-0:2.15.0-26.fc43.noarch >>> Scriptlet output: >>> Creating group 'adm' with GID 4. >>> Creating group 'audio' with GID 63. >>> Creating group 'cdrom' with GID 11. >>> Creating group 'clock' with GID 103. >>> Creating group 'dialout' with GID 18. >>> Creating group 'disk' with GID 6. >>> Creating group 'floppy' with GID 19. >>> Creating group 'ftp' with GID 50. >>> Creating group 'games' with GID 20. >>> Creating group 'input' with GID 104. >>> Creating group 'kmem' with GID 9. >>> Creating group 'kvm' with GID 36. >>> Creating group 'lock' with GID 54. >>> Creating group 'lp' with GID 7. >>> Creating group 'mail' with GID 12. >>> Creating group 'man' with GID 15. >>> Creating group 'mem' with GID 8. >>> Creating group 'nobody' with GID 65534. >>> Creating group 'render' with GID 105. >>> Creating group 'root' with GID 0. >>> Creating group 'sgx' with GID 106. >>> Creating group 'sys' with GID 3. >>> Creating group 'tape' with GID 33. >>> Creating group 'tty' with GID 5. >>> Creating group 'users' with GID 100. >>> Creating group 'utmp' with GID 22. >>> Creating group 'video' with GID 39. >>> Creating group 'wheel' with GID 10. >>> Creating user 'adm' (adm) with UID 3 and GID 4. >>> Creating group 'bin' with GID 1. >>> Creating user 'bin' (bin) with UID 1 and GID 1. >>> Creating group 'daemon' with GID 2. >>> Creating user 'daemon' (daemon) with UID 2 and GID 2. >>> Creating user 'ftp' (FTP User) with UID 14 and GID 50. >>> Creating user 'games' (games) with UID 12 and GID 100. >>> Creating user 'halt' (halt) with UID 7 and GID 0. >>> Creating user 'lp' (lp) with UID 4 and GID 7. >>> Creating user 'mail' (mail) with UID 8 and GID 12. >>> Creating user 'nobody' (Kernel Overflow User) with UID 65534 and GID 65534. >>> Creating user 'operator' (operator) with UID 11 and GID 0. >>> Creating user 'root' (Super User) with UID 0 and GID 0. >>> Creating user 'shutdown' (shutdown) with UID 6 and GID 0. >>> Creating user 'sync' (sync) with UID 5 and GID 0. >>> [ 11/172] Installing setup-0:2.15.0-26. 100% | 37.6 MiB/s | 730.6 KiB | 00m00s [ 12/172] Installing filesystem-0:3.18- 100% | 1.9 MiB/s | 212.8 KiB | 00m00s [ 13/172] Installing rust-srpm-macros-0 100% | 6.2 MiB/s | 6.4 KiB | 00m00s [ 14/172] Installing qt6-srpm-macros-0: 100% | 0.0 B/s | 748.0 B | 00m00s [ 15/172] Installing qt5-srpm-macros-0: 100% | 0.0 B/s | 776.0 B | 00m00s [ 16/172] Installing package-notes-srpm 100% | 0.0 B/s | 2.0 KiB | 00m00s [ 17/172] Installing gnat-srpm-macros-0 100% | 0.0 B/s | 1.3 KiB | 00m00s [ 18/172] Installing pcre2-syntax-0:10. 100% | 138.8 MiB/s | 284.3 KiB | 00m00s [ 19/172] Installing gnulib-l10n-0:2024 100% | 129.3 MiB/s | 661.9 KiB | 00m00s [ 20/172] Installing coreutils-common-0 100% | 305.2 MiB/s | 11.3 MiB | 00m00s [ 21/172] Installing pkgconf-m4-0:2.3.0 100% | 14.5 MiB/s | 14.8 KiB | 00m00s [ 22/172] Installing ncurses-base-0:6.5 100% | 49.3 MiB/s | 353.5 KiB | 00m00s [ 23/172] Installing bash-0:5.3.0-2.fc4 100% | 205.6 MiB/s | 8.4 MiB | 00m00s [ 24/172] Installing glibc-common-0:2.4 100% | 60.2 MiB/s | 1.3 MiB | 00m00s [ 25/172] Installing glibc-gconv-extra- 100% | 388.0 MiB/s | 18.6 MiB | 00m00s [ 26/172] Installing glibc-0:2.42-13.fc 100% | 149.5 MiB/s | 6.3 MiB | 00m00s [ 27/172] Installing ncurses-libs-0:6.5 100% | 249.5 MiB/s | 1.2 MiB | 00m00s [ 28/172] Installing glibc-minimal-lang 100% | 0.0 B/s | 124.0 B | 00m00s [ 29/172] Installing zlib-ng-compat-0:2 100% | 131.2 MiB/s | 134.4 KiB | 00m00s [ 30/172] Installing bzip2-libs-0:1.0.8 100% | 72.0 MiB/s | 73.8 KiB | 00m00s [ 31/172] Installing libgpg-error-0:1.5 100% | 47.7 MiB/s | 977.1 KiB | 00m00s [ 32/172] Installing libstdc++-0:15.2.1 100% | 315.1 MiB/s | 2.8 MiB | 00m00s [ 33/172] Installing xz-libs-1:5.8.1-4. 100% | 197.9 MiB/s | 202.7 KiB | 00m00s [ 34/172] Installing libassuan-0:2.5.7- 100% | 212.6 MiB/s | 217.7 KiB | 00m00s [ 35/172] Installing libgcrypt-0:1.11.1 100% | 238.9 MiB/s | 1.2 MiB | 00m00s [ 36/172] Installing readline-0:8.3-2.f 100% | 276.3 MiB/s | 565.9 KiB | 00m00s [ 37/172] Installing gmp-1:6.3.0-4.fc43 100% | 214.9 MiB/s | 660.1 KiB | 00m00s [ 38/172] Installing libuuid-0:2.41.4-7 100% | 68.9 MiB/s | 70.6 KiB | 00m00s [ 39/172] Installing popt-0:1.19-9.fc43 100% | 49.3 MiB/s | 151.4 KiB | 00m00s [ 40/172] Installing npth-0:1.8-3.fc43. 100% | 92.4 MiB/s | 94.6 KiB | 00m00s [ 41/172] Installing libblkid-0:2.41.4- 100% | 284.7 MiB/s | 291.5 KiB | 00m00s [ 42/172] Installing sqlite-libs-0:3.50 100% | 250.2 MiB/s | 1.5 MiB | 00m00s [ 43/172] Installing libzstd-0:1.5.7-2. 100% | 217.8 MiB/s | 669.0 KiB | 00m00s [ 44/172] Installing elfutils-libelf-0: 100% | 294.4 MiB/s | 1.2 MiB | 00m00s [ 45/172] Installing libxcrypt-0:4.5.2- 100% | 134.8 MiB/s | 276.1 KiB | 00m00s [ 46/172] Installing gnupg2-gpgconf-0:2 100% | 18.6 MiB/s | 324.0 KiB | 00m00s [ 47/172] Installing libattr-0:2.5.2-6. 100% | 67.8 MiB/s | 69.4 KiB | 00m00s [ 48/172] Installing libacl-0:2.3.2-4.f 100% | 67.2 MiB/s | 68.8 KiB | 00m00s [ 49/172] Installing libunistring-0:1.1 100% | 291.0 MiB/s | 1.7 MiB | 00m00s [ 50/172] Installing libidn2-0:2.3.8-2. 100% | 138.4 MiB/s | 566.7 KiB | 00m00s [ 51/172] Installing libtasn1-0:4.21.0- 100% | 27.2 MiB/s | 222.6 KiB | 00m00s [ 52/172] Installing crypto-policies-0: 100% | 21.0 MiB/s | 172.2 KiB | 00m00s [ 53/172] Installing dwz-0:0.16-2.fc43. 100% | 16.7 MiB/s | 324.0 KiB | 00m00s [ 54/172] Installing gnupg2-verify-0:2. 100% | 21.0 MiB/s | 365.8 KiB | 00m00s [ 55/172] Installing mpfr-0:4.2.2-2.fc4 100% | 184.9 MiB/s | 757.2 KiB | 00m00s [ 56/172] Installing gawk-0:5.3.2-2.fc4 100% | 103.3 MiB/s | 2.6 MiB | 00m00s [ 57/172] Installing libksba-0:1.6.7-4. 100% | 195.8 MiB/s | 401.0 KiB | 00m00s [ 58/172] Installing unzip-0:6.0-67.fc4 100% | 25.7 MiB/s | 473.7 KiB | 00m00s [ 59/172] Installing file-libs-0:5.46-9 100% | 565.9 MiB/s | 11.9 MiB | 00m00s [ 60/172] Installing file-0:5.46-9.fc43 100% | 8.1 MiB/s | 141.7 KiB | 00m00s [ 61/172] Installing libeconf-0:0.7.9-2 100% | 80.7 MiB/s | 82.6 KiB | 00m00s [ 62/172] Installing libsmartcols-0:2.4 100% | 220.3 MiB/s | 225.6 KiB | 00m00s [ 63/172] Installing libsepol-0:3.9-2.f 100% | 263.9 MiB/s | 810.8 KiB | 00m00s [ 64/172] Installing lz4-libs-0:1.10.0- 100% | 193.9 MiB/s | 198.5 KiB | 00m00s [ 65/172] Installing json-c-0:0.18-7.fc 100% | 136.7 MiB/s | 139.9 KiB | 00m00s [ 66/172] Installing pcre2-0:10.47-1.fc 100% | 233.0 MiB/s | 715.9 KiB | 00m00s [ 67/172] Installing libselinux-0:3.9-5 100% | 197.6 MiB/s | 202.4 KiB | 00m00s [ 68/172] Installing grep-0:3.12-2.fc43 100% | 47.2 MiB/s | 1.0 MiB | 00m00s [ 69/172] Installing sed-0:4.9-5.fc43.a 100% | 41.0 MiB/s | 881.4 KiB | 00m00s [ 70/172] Installing findutils-1:4.10.0 100% | 80.0 MiB/s | 1.9 MiB | 00m00s [ 71/172] Installing xz-1:5.8.1-4.fc43. 100% | 58.9 MiB/s | 1.4 MiB | 00m00s [ 72/172] Installing libmount-0:2.41.4- 100% | 205.7 MiB/s | 421.3 KiB | 00m00s [ 73/172] Installing libcap-ng-0:0.9.3- 100% | 159.1 MiB/s | 162.9 KiB | 00m00s [ 74/172] Installing audit-libs-0:4.1.4 100% | 239.0 MiB/s | 489.5 KiB | 00m00s [ 75/172] Installing pam-libs-0:1.7.1-4 100% | 220.0 MiB/s | 225.3 KiB | 00m00s [ 76/172] Installing libcap-0:2.76-4.fc 100% | 27.9 MiB/s | 513.9 KiB | 00m00s [ 77/172] Installing systemd-libs-0:258 100% | 300.1 MiB/s | 2.4 MiB | 00m00s [ 78/172] Installing lua-libs-0:5.4.8-4 100% | 161.8 MiB/s | 331.4 KiB | 00m00s [ 79/172] Installing libffi-0:3.5.2-1.f 100% | 153.6 MiB/s | 157.3 KiB | 00m00s [ 80/172] Installing p11-kit-0:0.26.2-1 100% | 98.7 MiB/s | 2.8 MiB | 00m00s [ 81/172] Installing alternatives-0:1.3 100% | 5.6 MiB/s | 91.8 KiB | 00m00s [ 82/172] Installing p11-kit-trust-0:0. 100% | 20.0 MiB/s | 532.0 KiB | 00m00s [ 83/172] Installing openssl-libs-1:3.5 100% | 296.9 MiB/s | 7.4 MiB | 00m00s [ 84/172] Installing coreutils-0:9.7-8. 100% | 175.0 MiB/s | 8.2 MiB | 00m00s [ 85/172] Installing ca-certificates-0: 100% | 1.4 MiB/s | 2.5 MiB | 00m02s [ 86/172] Installing gzip-0:1.13-4.fc43 100% | 22.1 MiB/s | 430.2 KiB | 00m00s [ 87/172] Installing libfsverity-0:1.6- 100% | 67.8 MiB/s | 69.4 KiB | 00m00s [ 88/172] Installing rpm-sequoia-0:1.10 100% | 278.4 MiB/s | 2.2 MiB | 00m00s [ 89/172] Installing libevent-0:2.1.12- 100% | 271.3 MiB/s | 1.1 MiB | 00m00s [ 90/172] Installing util-linux-core-0: 100% | 94.9 MiB/s | 2.5 MiB | 00m00s [ 91/172] Installing libusb1-0:1.0.29-4 100% | 17.6 MiB/s | 180.6 KiB | 00m00s >>> Running sysusers scriptlet: tpm2-tss-0:4.1.3-8.fc43.aarch64 >>> Finished sysusers scriptlet: tpm2-tss-0:4.1.3-8.fc43.aarch64 >>> Scriptlet output: >>> Creating group 'tss' with GID 59. >>> Creating user 'tss' (Account used for TPM access) with UID 59 and GID 59. >>> [ 92/172] Installing tpm2-tss-0:4.1.3-8 100% | 239.9 MiB/s | 2.2 MiB | 00m00s [ 93/172] Installing ima-evm-utils-libs 100% | 91.8 MiB/s | 94.0 KiB | 00m00s [ 94/172] Installing gnupg2-gpg-agent-0 100% | 29.7 MiB/s | 851.3 KiB | 00m00s [ 95/172] Installing systemd-standalone 100% | 17.9 MiB/s | 330.2 KiB | 00m00s [ 96/172] Installing rpm-libs-0:6.0.1-1 100% | 243.4 MiB/s | 997.1 KiB | 00m00s [ 97/172] Installing libsemanage-0:3.9- 100% | 176.7 MiB/s | 361.9 KiB | 00m00s [ 98/172] Installing tar-2:1.35-6.fc43. 100% | 111.3 MiB/s | 3.0 MiB | 00m00s [ 99/172] Installing zstd-0:1.5.7-2.fc4 100% | 71.7 MiB/s | 1.5 MiB | 00m00s [100/172] Installing zip-0:3.0-44.fc43. 100% | 39.4 MiB/s | 766.4 KiB | 00m00s [101/172] Installing gnupg2-keyboxd-0:2 100% | 32.7 MiB/s | 234.6 KiB | 00m00s [102/172] Installing libpsl-0:0.21.5-6. 100% | 130.5 MiB/s | 133.6 KiB | 00m00s [103/172] Installing liblastlog2-0:2.41 100% | 19.5 MiB/s | 140.1 KiB | 00m00s [104/172] Installing libfdisk-0:2.41.4- 100% | 205.1 MiB/s | 420.0 KiB | 00m00s [105/172] Installing nettle-0:3.10.1-2. 100% | 187.6 MiB/s | 768.4 KiB | 00m00s [106/172] Installing gnutls-0:3.8.13-1. 100% | 285.4 MiB/s | 3.7 MiB | 00m00s [107/172] Installing libxml2-0:2.12.10- 100% | 78.8 MiB/s | 1.9 MiB | 00m00s [108/172] Installing libarchive-0:3.8.4 100% | 238.6 MiB/s | 977.2 KiB | 00m00s [109/172] Installing bzip2-0:1.0.8-21.f 100% | 10.1 MiB/s | 175.8 KiB | 00m00s [110/172] Installing add-determinism-0: 100% | 92.4 MiB/s | 2.0 MiB | 00m00s [111/172] Installing build-reproducibil 100% | 1.0 MiB/s | 1.0 KiB | 00m00s [112/172] Installing cpio-0:2.15-6.fc43 100% | 52.2 MiB/s | 1.1 MiB | 00m00s [113/172] Installing diffutils-0:3.12-3 100% | 70.6 MiB/s | 1.6 MiB | 00m00s [114/172] Installing ed-0:1.22.2-1.fc43 100% | 9.1 MiB/s | 158.3 KiB | 00m00s [115/172] Installing patch-0:2.8-2.fc43 100% | 15.2 MiB/s | 264.1 KiB | 00m00s [116/172] Installing libpkgconf-0:2.3.0 100% | 132.0 MiB/s | 135.1 KiB | 00m00s [117/172] Installing pkgconf-0:2.3.0-3. 100% | 6.6 MiB/s | 114.9 KiB | 00m00s [118/172] Installing pkgconf-pkg-config 100% | 110.8 KiB/s | 1.8 KiB | 00m00s [119/172] Installing jansson-0:2.14-3.f 100% | 92.3 MiB/s | 94.5 KiB | 00m00s [120/172] Installing libgomp-0:15.2.1-7 100% | 253.1 MiB/s | 518.4 KiB | 00m00s [121/172] Installing gdbm-libs-1:1.23-1 100% | 230.1 MiB/s | 235.6 KiB | 00m00s [122/172] Installing cyrus-sasl-lib-0:2 100% | 100.7 MiB/s | 2.4 MiB | 00m00s [123/172] Installing libtool-ltdl-0:2.5 100% | 92.9 MiB/s | 95.1 KiB | 00m00s [124/172] Installing openldap-0:2.6.13- 100% | 187.5 MiB/s | 768.0 KiB | 00m00s [125/172] Installing gnupg2-dirmngr-0:2 100% | 24.4 MiB/s | 649.1 KiB | 00m00s [126/172] Installing gnupg2-0:2.4.9-5.f 100% | 167.7 MiB/s | 6.5 MiB | 00m00s [127/172] Installing rpm-sign-libs-0:6. 100% | 67.0 MiB/s | 68.6 KiB | 00m00s [128/172] Installing gpgverify-0:2.2-3. 100% | 9.2 MiB/s | 9.4 KiB | 00m00s [129/172] Installing xxhash-libs-0:0.8. 100% | 85.3 MiB/s | 87.4 KiB | 00m00s [130/172] Installing libnghttp2-0:1.66. 100% | 194.4 MiB/s | 199.1 KiB | 00m00s [131/172] Installing keyutils-libs-0:1. 100% | 97.4 MiB/s | 99.8 KiB | 00m00s [132/172] Installing libcom_err-0:1.47. 100% | 109.5 MiB/s | 112.2 KiB | 00m00s [133/172] Installing libverto-0:0.3.2-1 100% | 69.5 MiB/s | 71.2 KiB | 00m00s [134/172] Installing krb5-libs-0:1.22.2 100% | 253.3 MiB/s | 2.5 MiB | 00m00s [135/172] Installing libssh-0:0.11.4-1. 100% | 192.0 MiB/s | 589.8 KiB | 00m00s [136/172] Installing libbrotli-0:1.2.0- 100% | 222.6 MiB/s | 911.8 KiB | 00m00s [137/172] Installing libcurl-0:8.15.0-7 100% | 223.7 MiB/s | 916.2 KiB | 00m00s [138/172] Installing curl-0:8.15.0-7.fc 100% | 16.0 MiB/s | 460.0 KiB | 00m00s [139/172] Installing rpm-0:6.0.1-1.fc43 100% | 58.7 MiB/s | 2.8 MiB | 00m00s [140/172] Installing efi-srpm-macros-0: 100% | 40.2 MiB/s | 41.1 KiB | 00m00s [141/172] Installing java-srpm-macros-0 100% | 0.0 B/s | 1.1 KiB | 00m00s [142/172] Installing lua-srpm-macros-0: 100% | 0.0 B/s | 1.9 KiB | 00m00s [143/172] Installing tree-sitter-srpm-m 100% | 9.1 MiB/s | 9.3 KiB | 00m00s [144/172] Installing zig-srpm-macros-0: 100% | 0.0 B/s | 1.7 KiB | 00m00s [145/172] Installing filesystem-srpm-ma 100% | 38.0 MiB/s | 38.9 KiB | 00m00s [146/172] Installing elfutils-default-y 100% | 340.5 KiB/s | 2.0 KiB | 00m00s [147/172] Installing elfutils-libs-0:0. 100% | 182.8 MiB/s | 748.6 KiB | 00m00s [148/172] Installing elfutils-debuginfo 100% | 7.5 MiB/s | 146.4 KiB | 00m00s [149/172] Installing elfutils-0:0.195-1 100% | 128.1 MiB/s | 3.6 MiB | 00m00s [150/172] Installing binutils-0:2.45.1- 100% | 289.9 MiB/s | 31.0 MiB | 00m00s [151/172] Installing gdb-minimal-0:17.1 100% | 230.2 MiB/s | 13.4 MiB | 00m00s [152/172] Installing debugedit-0:5.2-3. 100% | 17.4 MiB/s | 321.2 KiB | 00m00s [153/172] Installing rpm-build-libs-0:6 100% | 129.4 MiB/s | 265.0 KiB | 00m00s [154/172] Installing perl-srpm-macros-0 100% | 0.0 B/s | 1.1 KiB | 00m00s [155/172] Installing openblas-srpm-macr 100% | 0.0 B/s | 392.0 B | 00m00s [156/172] Installing ocaml-srpm-macros- 100% | 0.0 B/s | 2.1 KiB | 00m00s [157/172] Installing kernel-srpm-macros 100% | 0.0 B/s | 2.3 KiB | 00m00s [158/172] Installing ghc-srpm-macros-0: 100% | 0.0 B/s | 1.0 KiB | 00m00s [159/172] Installing gap-srpm-macros-0: 100% | 0.0 B/s | 2.7 KiB | 00m00s [160/172] Installing fpc-srpm-macros-0: 100% | 0.0 B/s | 420.0 B | 00m00s [161/172] Installing ansible-srpm-macro 100% | 35.4 MiB/s | 36.2 KiB | 00m00s [162/172] Installing rpm-build-0:6.0.1- 100% | 29.7 MiB/s | 608.1 KiB | 00m00s [163/172] Installing pyproject-srpm-mac 100% | 3.7 MiB/s | 3.8 KiB | 00m00s [164/172] Installing redhat-rpm-config- 100% | 61.6 MiB/s | 189.1 KiB | 00m00s [165/172] Installing forge-srpm-macros- 100% | 39.3 MiB/s | 40.3 KiB | 00m00s [166/172] Installing fonts-srpm-macros- 100% | 55.7 MiB/s | 57.0 KiB | 00m00s [167/172] Installing go-srpm-macros-0:3 100% | 61.6 MiB/s | 63.0 KiB | 00m00s [168/172] Installing python-srpm-macros 100% | 25.8 MiB/s | 52.8 KiB | 00m00s [169/172] Installing util-linux-0:2.41. 100% | 129.5 MiB/s | 6.9 MiB | 00m00s [170/172] Installing shadow-utils-2:4.1 100% | 102.1 MiB/s | 4.5 MiB | 00m00s [171/172] Installing which-0:2.23-3.fc4 100% | 7.2 MiB/s | 125.6 KiB | 00m00s [172/172] Installing info-0:7.2-7.fc43. 100% | 185.2 KiB/s | 422.0 KiB | 00m02s Complete! Finish: installing minimal buildroot with dnf5 Start: creating root cache Finish: creating root cache Finish: chroot init INFO: Installed packages: INFO: add-determinism-0.6.0-3.fc43.aarch64 alternatives-1.33-3.fc43.aarch64 ansible-srpm-macros-1-18.1.fc43.noarch audit-libs-4.1.4-1.fc43.aarch64 bash-5.3.0-2.fc43.aarch64 binutils-2.45.1-4.fc43.aarch64 build-reproducibility-srpm-macros-0.6.0-3.fc43.noarch bzip2-1.0.8-21.fc43.aarch64 bzip2-libs-1.0.8-21.fc43.aarch64 ca-certificates-2025.2.80_v9.0.304-1.2.fc43.noarch coreutils-9.7-8.fc43.aarch64 coreutils-common-9.7-8.fc43.aarch64 cpio-2.15-6.fc43.aarch64 crypto-policies-20251125-1.git63291f8.fc43.noarch curl-8.15.0-7.fc43.aarch64 cyrus-sasl-lib-2.1.28-33.fc43.aarch64 debugedit-5.2-3.fc43.aarch64 diffutils-3.12-3.fc43.aarch64 dwz-0.16-2.fc43.aarch64 ed-1.22.2-1.fc43.aarch64 efi-srpm-macros-6-4.fc43.noarch elfutils-0.195-1.fc43.aarch64 elfutils-debuginfod-client-0.195-1.fc43.aarch64 elfutils-default-yama-scope-0.195-1.fc43.noarch elfutils-libelf-0.195-1.fc43.aarch64 elfutils-libs-0.195-1.fc43.aarch64 fedora-gpg-keys-43-1.noarch fedora-release-43-27.noarch fedora-release-common-43-27.noarch fedora-release-identity-basic-43-27.noarch fedora-repos-43-1.noarch file-5.46-9.fc43.aarch64 file-libs-5.46-9.fc43.aarch64 filesystem-3.18-50.fc43.aarch64 filesystem-srpm-macros-3.18-50.fc43.noarch findutils-4.10.0-6.fc43.aarch64 fonts-srpm-macros-2.0.5-23.fc43.noarch forge-srpm-macros-0.4.0-3.fc43.noarch fpc-srpm-macros-1.3-15.fc43.noarch gap-srpm-macros-2-1.fc43.noarch gawk-5.3.2-2.fc43.aarch64 gdb-minimal-17.1-4.fc43.aarch64 gdbm-libs-1.23-10.fc43.aarch64 ghc-srpm-macros-1.9.2-3.fc43.noarch glibc-2.42-13.fc43.aarch64 glibc-common-2.42-13.fc43.aarch64 glibc-gconv-extra-2.42-13.fc43.aarch64 glibc-minimal-langpack-2.42-13.fc43.aarch64 gmp-6.3.0-4.fc43.aarch64 gnat-srpm-macros-7-1.fc43.noarch gnulib-l10n-20241231-1.fc43.noarch gnupg2-2.4.9-5.fc43.aarch64 gnupg2-dirmngr-2.4.9-5.fc43.aarch64 gnupg2-gpg-agent-2.4.9-5.fc43.aarch64 gnupg2-gpgconf-2.4.9-5.fc43.aarch64 gnupg2-keyboxd-2.4.9-5.fc43.aarch64 gnupg2-verify-2.4.9-5.fc43.aarch64 gnutls-3.8.13-1.fc43.aarch64 go-srpm-macros-3.8.0-1.fc43.noarch gpg-pubkey-c6e7f081cf80e13146676e88829b606631645531-66b6dccf gpgverify-2.2-3.fc43.noarch grep-3.12-2.fc43.aarch64 gzip-1.13-4.fc43.aarch64 ima-evm-utils-libs-1.6.2-6.fc43.aarch64 info-7.2-7.fc43.aarch64 jansson-2.14-3.fc43.aarch64 java-srpm-macros-1-7.fc43.noarch json-c-0.18-7.fc43.aarch64 kernel-srpm-macros-1.0-27.fc43.noarch keyutils-libs-1.6.3-6.fc43.aarch64 krb5-libs-1.22.2-4.fc43.aarch64 libacl-2.3.2-4.fc43.aarch64 libarchive-3.8.4-1.fc43.aarch64 libassuan-2.5.7-4.fc43.aarch64 libattr-2.5.2-6.fc43.aarch64 libblkid-2.41.4-7.fc43.aarch64 libbrotli-1.2.0-1.fc43.aarch64 libcap-2.76-4.fc43.aarch64 libcap-ng-0.9.3-1.fc43.aarch64 libcom_err-1.47.3-2.fc43.aarch64 libcurl-8.15.0-7.fc43.aarch64 libeconf-0.7.9-2.fc43.aarch64 libevent-2.1.12-16.fc43.aarch64 libfdisk-2.41.4-7.fc43.aarch64 libffi-3.5.2-1.fc43.aarch64 libfsverity-1.6-3.fc43.aarch64 libgcc-15.2.1-7.fc43.aarch64 libgcrypt-1.11.1-4.fc43.aarch64 libgomp-15.2.1-7.fc43.aarch64 libgpg-error-1.55-2.fc43.aarch64 libidn2-2.3.8-2.fc43.aarch64 libksba-1.6.7-4.fc43.aarch64 liblastlog2-2.41.4-7.fc43.aarch64 libmount-2.41.4-7.fc43.aarch64 libnghttp2-1.66.0-2.fc43.aarch64 libpkgconf-2.3.0-3.fc43.aarch64 libpsl-0.21.5-6.fc43.aarch64 libselinux-3.9-5.fc43.aarch64 libsemanage-3.9-4.fc43.aarch64 libsepol-3.9-2.fc43.aarch64 libsmartcols-2.41.4-7.fc43.aarch64 libssh-0.11.4-1.fc43.aarch64 libssh-config-0.11.4-1.fc43.noarch libstdc++-15.2.1-7.fc43.aarch64 libtasn1-4.21.0-1.fc43.aarch64 libtool-ltdl-2.5.4-8.fc43.aarch64 libunistring-1.1-10.fc43.aarch64 libusb1-1.0.29-4.fc43.aarch64 libuuid-2.41.4-7.fc43.aarch64 libverto-0.3.2-11.fc43.aarch64 libxcrypt-4.5.2-1.fc43.aarch64 libxml2-2.12.10-5.fc43.aarch64 libzstd-1.5.7-2.fc43.aarch64 lua-libs-5.4.8-4.fc43.aarch64 lua-srpm-macros-1-16.fc43.noarch lz4-libs-1.10.0-3.fc43.aarch64 mpfr-4.2.2-2.fc43.aarch64 ncurses-base-6.5-7.20250614.fc43.noarch ncurses-libs-6.5-7.20250614.fc43.aarch64 nettle-3.10.1-2.fc43.aarch64 npth-1.8-3.fc43.aarch64 ocaml-srpm-macros-11-2.fc43.noarch openblas-srpm-macros-2-20.fc43.noarch openldap-2.6.13-1.fc43.aarch64 openssl-libs-3.5.4-3.fc43.aarch64 p11-kit-0.26.2-1.fc43.aarch64 p11-kit-trust-0.26.2-1.fc43.aarch64 package-notes-srpm-macros-0.5-15.fc43.noarch pam-libs-1.7.1-4.fc43.aarch64 patch-2.8-2.fc43.aarch64 pcre2-10.47-1.fc43.aarch64 pcre2-syntax-10.47-1.fc43.noarch perl-srpm-macros-1-60.fc43.noarch pkgconf-2.3.0-3.fc43.aarch64 pkgconf-m4-2.3.0-3.fc43.noarch pkgconf-pkg-config-2.3.0-3.fc43.aarch64 popt-1.19-9.fc43.aarch64 publicsuffix-list-dafsa-20260116-1.fc43.noarch pyproject-srpm-macros-1.22.1-1.fc43.noarch python-srpm-macros-3.14-5.fc43.noarch qt5-srpm-macros-5.15.18-1.fc43.noarch qt6-srpm-macros-6.10.3-1.fc43.noarch readline-8.3-2.fc43.aarch64 redhat-rpm-config-343-12.fc43.noarch rpm-6.0.1-1.fc43.aarch64 rpm-build-6.0.1-1.fc43.aarch64 rpm-build-libs-6.0.1-1.fc43.aarch64 rpm-libs-6.0.1-1.fc43.aarch64 rpm-sequoia-1.10.2-2.fc43.aarch64 rpm-sign-libs-6.0.1-1.fc43.aarch64 rust-srpm-macros-28.4-1.fc43.noarch sed-4.9-5.fc43.aarch64 setup-2.15.0-26.fc43.noarch shadow-utils-4.18.0-3.fc43.aarch64 sqlite-libs-3.50.2-2.fc43.aarch64 systemd-libs-258.7-1.fc43.aarch64 systemd-standalone-sysusers-258.7-1.fc43.aarch64 tar-1.35-6.fc43.aarch64 tpm2-tss-4.1.3-8.fc43.aarch64 tree-sitter-srpm-macros-0.4.2-1.fc43.noarch unzip-6.0-67.fc43.aarch64 util-linux-2.41.4-7.fc43.aarch64 util-linux-core-2.41.4-7.fc43.aarch64 which-2.23-3.fc43.aarch64 xxhash-libs-0.8.3-3.fc43.aarch64 xz-5.8.1-4.fc43.aarch64 xz-libs-5.8.1-4.fc43.aarch64 zig-srpm-macros-1-5.fc43.noarch zip-3.0-44.fc43.aarch64 zlib-ng-compat-2.3.3-2.fc43.aarch64 zstd-1.5.7-2.fc43.aarch64 Start: buildsrpm Start: rpmbuild -bs Building target platforms: aarch64 Building for target aarch64 setting SOURCE_DATE_EPOCH=1654300800 Wrote: /builddir/build/SRPMS/litex-pythondata-cpu-cva6-2026.04-20260526.0.gitda8c19c8.fc43.src.rpm Finish: rpmbuild -bs INFO: chroot_scan: 1 files copied to /var/lib/copr-rpmbuild/results/chroot_scan INFO: /var/lib/mock/fedora-43-aarch64-1779852097.193724/root/var/log/dnf5.log INFO: chroot_scan: creating tarball /var/lib/copr-rpmbuild/results/chroot_scan.tar.gz /bin/tar: Removing leading `/' from member names Finish: buildsrpm INFO: Done(/var/lib/copr-rpmbuild/workspace/workdir-80xpc3wc/litex-pythondata-cpu-cva6/litex-pythondata-cpu-cva6.spec) Config(child) 0 minutes 12 seconds INFO: Results and/or logs in: /var/lib/copr-rpmbuild/results INFO: Cleaning up build root ('cleanup_on_success=True') Start: clean chroot INFO: unmounting tmpfs. Finish: clean chroot INFO: Start(/var/lib/copr-rpmbuild/results/litex-pythondata-cpu-cva6-2026.04-20260526.0.gitda8c19c8.fc43.src.rpm) Config(fedora-43-aarch64) Start(bootstrap): chroot init INFO: mounting tmpfs at /var/lib/mock/fedora-43-aarch64-bootstrap-1779852097.193724/root. INFO: reusing tmpfs at /var/lib/mock/fedora-43-aarch64-bootstrap-1779852097.193724/root. INFO: calling preinit hooks INFO: enabled root cache INFO: enabled package manager cache Start(bootstrap): cleaning package manager metadata Finish(bootstrap): cleaning package manager metadata Finish(bootstrap): chroot init Start: chroot init INFO: mounting tmpfs at /var/lib/mock/fedora-43-aarch64-1779852097.193724/root. INFO: calling preinit hooks INFO: enabled root cache Start: unpacking root cache Finish: unpacking root cache INFO: enabled package manager cache Start: cleaning package manager metadata Finish: cleaning package manager metadata INFO: enabled HW Info plugin INFO: Buildroot is handled by package management downloaded with a bootstrap image: rpm-6.0.1-1.fc43.aarch64 rpm-sequoia-1.10.2-1.fc43.aarch64 dnf5-5.2.18.0-3.fc43.aarch64 dnf5-plugins-5.2.18.0-3.fc43.aarch64 Finish: chroot init Start: build phase for litex-pythondata-cpu-cva6-2026.04-20260526.0.gitda8c19c8.fc43.src.rpm Start: build setup for litex-pythondata-cpu-cva6-2026.04-20260526.0.gitda8c19c8.fc43.src.rpm Building target platforms: aarch64 Building for target aarch64 setting SOURCE_DATE_EPOCH=1654300800 Wrote: /builddir/build/SRPMS/litex-pythondata-cpu-cva6-2026.04-20260526.0.gitda8c19c8.fc43.src.rpm Updating and loading repositories: Copr repository 100% | 47.8 KiB/s | 1.5 KiB | 00m00s fedora 100% | 29.7 KiB/s | 16.3 KiB | 00m01s updates 100% | 113.3 KiB/s | 9.5 KiB | 00m00s Repositories loaded. Package Arch Version Repository Size Installing: git aarch64 2.54.0-1.fc43 updates 57.7 KiB python3-devel aarch64 3.14.4-2.fc43 updates 2.0 MiB python3-setuptools noarch 78.1.1-15.fc43 fedora 9.0 MiB Installing dependencies: expat aarch64 2.8.1-1.fc43 updates 371.4 KiB git-core aarch64 2.54.0-1.fc43 updates 24.3 MiB git-core-doc noarch 2.54.0-1.fc43 updates 18.7 MiB groff-base aarch64 1.23.0-11.fc43 updates 4.2 MiB less aarch64 692-6.fc43 updates 599.1 KiB libcbor aarch64 0.12.0-6.fc43 fedora 137.9 KiB libedit aarch64 3.1-57.20251016cvs.fc43 updates 280.2 KiB libfido2 aarch64 1.16.0-3.fc43 fedora 278.7 KiB mpdecimal aarch64 4.0.1-2.fc43 fedora 281.2 KiB ncurses aarch64 6.5-7.20250614.fc43 fedora 893.6 KiB openssh aarch64 10.0p1-9.fc43 updates 1.4 MiB openssh-clients aarch64 10.0p1-9.fc43 updates 2.7 MiB perl-AutoLoader noarch 5.74-523.fc43 updates 20.6 KiB perl-B aarch64 1.89-523.fc43 updates 545.4 KiB perl-Carp noarch 1.54-520.fc43 fedora 46.6 KiB perl-Class-Struct noarch 0.68-523.fc43 updates 25.4 KiB perl-Data-Dumper aarch64 2.191-521.fc43 fedora 135.7 KiB perl-Digest noarch 1.20-520.fc43 fedora 35.3 KiB perl-Digest-MD5 aarch64 2.59-520.fc43 fedora 103.7 KiB perl-DynaLoader aarch64 1.57-523.fc43 updates 32.1 KiB perl-Encode aarch64 4:3.21-520.fc43 fedora 4.8 MiB perl-Errno aarch64 1.38-523.fc43 updates 8.4 KiB perl-Error noarch 1:0.17030-2.fc43 fedora 76.7 KiB perl-Exporter noarch 5.79-520.fc43 fedora 54.3 KiB perl-Fcntl aarch64 1.20-523.fc43 updates 92.8 KiB perl-File-Basename noarch 2.86-523.fc43 updates 14.0 KiB perl-File-Path noarch 2.18-520.fc43 fedora 63.5 KiB perl-File-Temp noarch 1:0.231.100-520.fc43 fedora 162.3 KiB perl-File-stat noarch 1.14-523.fc43 updates 12.5 KiB perl-FileHandle noarch 2.05-523.fc43 updates 9.4 KiB perl-Getopt-Long noarch 1:2.58-520.fc43 fedora 144.5 KiB perl-Getopt-Std noarch 1.14-523.fc43 updates 11.2 KiB perl-Git noarch 2.54.0-1.fc43 updates 64.4 KiB perl-HTTP-Tiny noarch 0.090-521.fc43 fedora 154.4 KiB perl-IO aarch64 1.55-523.fc43 updates 191.4 KiB perl-IO-Socket-IP noarch 0.43-521.fc43 fedora 100.3 KiB perl-IO-Socket-SSL noarch 2.095-2.fc43 fedora 714.5 KiB perl-IPC-Open3 noarch 1.24-523.fc43 updates 27.7 KiB perl-MIME-Base32 noarch 1.303-24.fc43 fedora 30.7 KiB perl-MIME-Base64 aarch64 3.16-520.fc43 fedora 94.1 KiB perl-Net-SSLeay aarch64 1.94-11.fc43 fedora 1.4 MiB perl-POSIX aarch64 2.23-523.fc43 updates 261.6 KiB perl-PathTools aarch64 3.94-520.fc43 fedora 224.0 KiB perl-Pod-Escapes noarch 1:1.07-520.fc43 fedora 24.9 KiB perl-Pod-Perldoc noarch 3.28.01-521.fc43 fedora 163.7 KiB perl-Pod-Simple noarch 1:3.47-3.fc43 fedora 565.3 KiB perl-Pod-Usage noarch 4:2.05-520.fc43 fedora 86.3 KiB perl-Scalar-List-Utils aarch64 5:1.70-1.fc43 fedora 152.9 KiB perl-SelectSaver noarch 1.02-523.fc43 updates 2.2 KiB perl-Socket aarch64 4:2.040-2.fc43 fedora 144.3 KiB perl-Storable aarch64 1:3.37-521.fc43 fedora 243.2 KiB perl-Symbol noarch 1.09-523.fc43 updates 6.8 KiB perl-Term-ANSIColor noarch 5.01-521.fc43 fedora 97.5 KiB perl-Term-Cap noarch 1.18-520.fc43 fedora 29.3 KiB perl-TermReadKey aarch64 2.38-26.fc43 fedora 108.0 KiB perl-Text-ParseWords noarch 3.31-520.fc43 fedora 13.6 KiB perl-Text-Tabs+Wrap noarch 2024.001-520.fc43 fedora 22.6 KiB perl-Time-Local noarch 2:1.350-520.fc43 fedora 69.0 KiB perl-URI noarch 5.34-2.fc43 updates 268.0 KiB perl-base noarch 2.27-523.fc43 updates 12.6 KiB perl-constant noarch 1.33-521.fc43 fedora 26.2 KiB perl-if noarch 0.61.000-523.fc43 updates 5.8 KiB perl-interpreter aarch64 4:5.42.2-523.fc43 updates 174.8 KiB perl-lib aarch64 0.65-523.fc43 updates 8.5 KiB perl-libnet noarch 3.15-521.fc43 fedora 289.4 KiB perl-libs aarch64 4:5.42.2-523.fc43 updates 11.6 MiB perl-locale noarch 1.13-523.fc43 updates 6.1 KiB perl-mro aarch64 1.29-523.fc43 updates 81.6 KiB perl-overload noarch 1.40-523.fc43 updates 71.6 KiB perl-overloading noarch 0.02-523.fc43 updates 4.9 KiB perl-parent noarch 1:0.244-520.fc43 fedora 10.3 KiB perl-podlators noarch 1:6.0.2-520.fc43 fedora 317.5 KiB perl-vars noarch 1.05-523.fc43 updates 3.9 KiB pyproject-rpm-macros noarch 1.22.1-1.fc43 updates 147.5 KiB python-pip-wheel noarch 25.1.1-18.fc43 fedora 1.2 MiB python-rpm-macros noarch 3.14-5.fc43 fedora 23.2 KiB python3 aarch64 3.14.4-2.fc43 updates 84.8 KiB python3-libs aarch64 3.14.4-2.fc43 updates 45.2 MiB python3-packaging noarch 25.0-7.fc43 fedora 607.4 KiB python3-rpm-generators noarch 14-13.fc43 fedora 81.7 KiB python3-rpm-macros noarch 3.14-5.fc43 fedora 6.5 KiB tzdata noarch 2026a-1.fc43 updates 1.6 MiB Transaction Summary: Installing: 85 packages Total size of inbound packages is 33 MiB. Need to download 0 B. After this operation, 138 MiB extra will be used (install 138 MiB, remove 0 B). [ 1/85] python3-setuptools-0:78.1.1-15. 100% | 0.0 B/s | 0.0 B | 00m00s >>> Already downloaded [ 2/85] git-0:2.54.0-1.fc43.aarch64 100% | 0.0 B/s | 0.0 B | 00m00s >>> Already downloaded [ 3/85] python3-devel-0:3.14.4-2.fc43.a 100% | 0.0 B/s | 0.0 B | 00m00s >>> Already downloaded [ 4/85] perl-Getopt-Long-1:2.58-520.fc4 100% | 0.0 B/s | 0.0 B | 00m00s >>> Already downloaded [ 5/85] perl-PathTools-0:3.94-520.fc43. 100% | 0.0 B/s | 0.0 B | 00m00s >>> Already downloaded [ 6/85] perl-TermReadKey-0:2.38-26.fc43 100% | 0.0 B/s | 0.0 B | 00m00s >>> Already downloaded [ 7/85] git-core-0:2.54.0-1.fc43.aarch6 100% | 0.0 B/s | 0.0 B | 00m00s >>> Already downloaded [ 8/85] git-core-doc-0:2.54.0-1.fc43.no 100% | 0.0 B/s | 0.0 B | 00m00s >>> Already downloaded [ 9/85] perl-Git-0:2.54.0-1.fc43.noarch 100% | 0.0 B/s | 0.0 B | 00m00s >>> Already downloaded [10/85] python3-0:3.14.4-2.fc43.aarch64 100% | 0.0 B/s | 0.0 B | 00m00s >>> Already downloaded [11/85] python3-libs-0:3.14.4-2.fc43.aa 100% | 0.0 B/s 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Building target platforms: aarch64 Building for target aarch64 warning: The %py3_build macro is deprecated and will likely stop working in Fedora 44. See the current Python packaging guidelines: https://docs.fedoraproject.org/en-US/packaging-guidelines/Python/ warning: The %py3_install macro is deprecated and will likely stop working in Fedora 44. See the current Python packaging guidelines: https://docs.fedoraproject.org/en-US/packaging-guidelines/Python/ setting SOURCE_DATE_EPOCH=1654300800 Wrote: /builddir/build/SRPMS/litex-pythondata-cpu-cva6-2026.04-20260526.0.gitda8c19c8.fc43.src.rpm RPM build warnings: The %py3_build macro is deprecated and will likely stop working in Fedora 44. See the current Python packaging guidelines: https://docs.fedoraproject.org/en-US/packaging-guidelines/Python/ The %py3_install macro is deprecated and will likely stop working in Fedora 44. See the current Python packaging guidelines: https://docs.fedoraproject.org/en-US/packaging-guidelines/Python/ Updating and loading repositories: Copr repository 100% | 1.3 KiB/s | 1.5 KiB | 00m01s fedora 100% | 11.6 KiB/s | 16.3 KiB | 00m01s updates 100% | 7.4 KiB/s | 9.5 KiB | 00m01s Repositories loaded. Package "git-2.54.0-1.fc43.aarch64" is already installed. Package "python3-devel-3.14.4-2.fc43.aarch64" is already installed. Package "python3-setuptools-78.1.1-15.fc43.noarch" is already installed. Nothing to do. Finish: build setup for litex-pythondata-cpu-cva6-2026.04-20260526.0.gitda8c19c8.fc43.src.rpm Start: rpmbuild litex-pythondata-cpu-cva6-2026.04-20260526.0.gitda8c19c8.fc43.src.rpm Building target platforms: aarch64 Building for target aarch64 warning: The %py3_build macro is deprecated and will likely stop working in Fedora 44. See the current Python packaging guidelines: https://docs.fedoraproject.org/en-US/packaging-guidelines/Python/ warning: The %py3_install macro is deprecated and will likely stop working in Fedora 44. See the current Python packaging guidelines: https://docs.fedoraproject.org/en-US/packaging-guidelines/Python/ setting SOURCE_DATE_EPOCH=1654300800 Executing(%mkbuilddir): /bin/sh -e /var/tmp/rpm-tmp.uH5jkK Executing(%prep): /bin/sh -e /var/tmp/rpm-tmp.M8UpO5 + umask 022 + cd /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build + cd /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build + rm -rf litex-pythondata-cpu-cva6 + /usr/bin/mkdir -p litex-pythondata-cpu-cva6 + cd litex-pythondata-cpu-cva6 + /usr/bin/chmod -Rf a+rX,u+w,g-w,o-w . + git clone --depth 1 -n -b master https://github.com/litex-hub/pythondata-cpu-cva6.git . Cloning into '.'... + git fetch --depth 1 origin da8c19c8142eee4053b714fc2b748d746e17f175 From https://github.com/litex-hub/pythondata-cpu-cva6 * branch da8c19c8142eee4053b714fc2b748d746e17f175 -> FETCH_HEAD + git reset --hard da8c19c8142eee4053b714fc2b748d746e17f175 HEAD is now at da8c19c packaging: fix release installs + git log --format=fuller commit da8c19c8142eee4053b714fc2b748d746e17f175 Author: Florent Kermarrec AuthorDate: Tue May 26 16:49:34 2026 +0200 Commit: Florent Kermarrec CommitDate: Tue May 26 16:49:34 2026 +0200 packaging: fix release installs + RPM_EC=0 ++ jobs -p + exit 0 Executing(%build): /bin/sh -e /var/tmp/rpm-tmp.JOy2Kx + umask 022 + cd /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build + cd litex-pythondata-cpu-cva6 + CFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Wno-complain-wrong-lang -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -mbranch-protection=standard -fasynchronous-unwind-tables -fstack-clash-protection -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer' + LDFLAGS='-Wl,-z,relro -Wl,--as-needed -Wl,-z,pack-relative-relocs -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-hardened-ld-errors -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -Wl,--build-id=sha1 -specs=/usr/lib/rpm/redhat/redhat-package-notes ' + /usr/bin/python3 setup.py build '--executable=/usr/bin/python3 -sP' /usr/lib/python3.14/site-packages/setuptools/dist.py:759: SetuptoolsDeprecationWarning: License classifiers are deprecated. !! ******************************************************************************** Please consider removing the following classifiers in favor of a SPDX license expression: License :: OSI Approved :: Apache Software License See https://packaging.python.org/en/latest/guides/writing-pyproject-toml/#license for details. ******************************************************************************** !! self._finalize_license_expression() running build running build_py creating build/lib/pythondata_cpu_cva6 copying pythondata_cpu_cva6/__init__.py -> build/lib/pythondata_cpu_cva6 running egg_info creating pythondata_cpu_cva6.egg-info writing pythondata_cpu_cva6.egg-info/PKG-INFO writing dependency_links to pythondata_cpu_cva6.egg-info/dependency_links.txt writing top-level names to pythondata_cpu_cva6.egg-info/top_level.txt writing manifest file 'pythondata_cpu_cva6.egg-info/SOURCES.txt' reading manifest file 'pythondata_cpu_cva6.egg-info/SOURCES.txt' reading manifest template 'MANIFEST.in' warning: no previously-included files matching '*.py[cod]' found anywhere in distribution warning: no previously-included files matching '__pycache__/*' found anywhere in distribution adding license file 'LICENSE' writing manifest file 'pythondata_cpu_cva6.egg-info/SOURCES.txt' /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.ci' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.ci' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.ci' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.ci' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.ci' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.common.local.techlib.fpga.rtl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.common.local.techlib.fpga.rtl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.common.local.techlib.fpga.rtl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.common.local.techlib.fpga.rtl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.common.local.techlib.fpga.rtl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.common.local.util' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.common.local.util' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.common.local.util' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.common.local.util' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.common.local.util' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.cache_subsystem' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.cache_subsystem' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.cache_subsystem' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.cache_subsystem' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.cache_subsystem' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.cvxif_example' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.cvxif_example' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.cvxif_example' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.cvxif_example' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.cvxif_example' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.cvxif_example.include' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.cvxif_example.include' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.cvxif_example.include' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.cvxif_example.include' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.cvxif_example.include' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.example_tb.verilator_results' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.example_tb.verilator_results' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.example_tb.verilator_results' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.example_tb.verilator_results' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.example_tb.verilator_results' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.frontend' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.frontend' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.frontend' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.frontend' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.frontend' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.include' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.include' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.include' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.include' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.include' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.mmu_sv32' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.mmu_sv32' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.mmu_sv32' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.mmu_sv32' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.mmu_sv32' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.mmu_sv39' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.mmu_sv39' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.mmu_sv39' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.mmu_sv39' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.mmu_sv39' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.pmp' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.pmp' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.pmp' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.pmp' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.pmp' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.pmp.include' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.pmp.include' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.pmp.include' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.pmp.include' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.pmp.include' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.pmp.src' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.pmp.src' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.pmp.src' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.pmp.src' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.pmp.src' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.pmp.tb' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.pmp.tb' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.pmp.tb' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.pmp.tb' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.pmp.tb' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.bootrom' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.bootrom' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.bootrom' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.bootrom' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.bootrom' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.clint' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.clint' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.clint' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.clint' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.clint' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.constraints' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.constraints' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.constraints' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.constraints' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.constraints' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.scripts' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.scripts' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.scripts' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.scripts' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.scripts' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom.src' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom.src' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom.src' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom.src' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom.src' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.include' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.include' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.include' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.include' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.include' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.baremetal' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.baremetal' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.baremetal' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.baremetal' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.baremetal' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux.src' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux.src' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux.src' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux.src' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux.src' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.common' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.common' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.common' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.common' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.common' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.dpi' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.dpi' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.dpi' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.dpi' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.dpi' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache.hdl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache.hdl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache.hdl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache.hdl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache.hdl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv.hdl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv.hdl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv.hdl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv.hdl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv.hdl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache.hdl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache.hdl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache.hdl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache.hdl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache.hdl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache.hdl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache.hdl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache.hdl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache.hdl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache.hdl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache.hdl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache.hdl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache.hdl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache.hdl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache.hdl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.wave' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.wave' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.wave' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.wave' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.wave' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.docs' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.docs' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.docs' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.docs' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.docs' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.docs._static' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.docs._static' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.docs._static' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.docs._static' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.docs._static' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) creating build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/.editorconfig -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/.gitlab-ci.yml -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/.gitmodules -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/Bender.yml -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/CHANGELOG.md -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/CODEOWNERS -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/CONTRIBUTING.md -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/Flist.ariane -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/LICENSE -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/LICENSE.Berkeley -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/LICENSE.SiFive -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/README.md -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/ariane.core -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/config_pkg_generator.py -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/init_testharness.do -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/src_files.yml -> build/lib/pythondata_cpu_cva6/system_verilog creating build/lib/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE copying pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE/bug.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE copying pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE/task.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE creating build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows copying pythondata_cpu_cva6/system_verilog/.github/workflows/ci.yml -> build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows creating build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci copying pythondata_cpu_cva6/system_verilog/.gitlab-ci/core-v-verif-cva6.yml -> build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci copying pythondata_cpu_cva6/system_verilog/.gitlab-ci/cva6.yml -> build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci creating build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/build-riscv-gcc.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/build-riscv-tests.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/check-tests.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/default.config -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/float.config -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/get-torture.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/gitlab-ci-emul.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/install-dtc.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/install-fesvr.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/install-riscvpk.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/install-spike.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/install-verilator.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/make-tmp.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.docs.design_spec' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.docs.design_spec' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.docs.design_spec' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.docs.design_spec' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.docs.design_spec' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.docs.design_spec.images' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.docs.design_spec.images' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.docs.design_spec.images' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.docs.design_spec.images' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.docs.design_spec.images' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.docs.design_spec.source' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.docs.design_spec.source' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.docs.design_spec.source' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.docs.design_spec.source' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.docs.design_spec.source' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.docs.specifications' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.docs.specifications' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.docs.specifications' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.docs.specifications' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.docs.specifications' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.docs.specifications.images' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.docs.specifications.images' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.docs.specifications.images' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.docs.specifications.images' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.docs.specifications.images' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.docs.user_guide' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.docs.user_guide' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.docs.user_guide' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.docs.user_guide' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.docs.user_guide' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.pd.synth' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.pd.synth' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.pd.synth' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.pd.synth' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.pd.synth' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.pd.synth.scripts' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.pd.synth.scripts' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.pd.synth.scripts' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.pd.synth.scripts' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.pd.synth.scripts' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.14/site-packages/setuptools/command/build_py.py:212: _Warning: Package 'pythondata_cpu_cva6.system_verilog.scripts' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.scripts' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.scripts' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.scripts' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.scripts' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) copying pythondata_cpu_cva6/system_verilog/ci/path-setup.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/riscv-amo-tests.list -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/riscv-asm-tests.list -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/riscv-benchmarks.list -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/riscv-fp-tests.list -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/riscv-mul-tests.list -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/setup.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/torture_make.patch -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/travis-ci-emul.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci creating build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl copying pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl/SyncDpRam.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl copying pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl/SyncSpRam.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl copying pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl/SyncSpRamBeNx32.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl copying pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl/SyncSpRamBeNx64.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl copying pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl/SyncTpRam.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl creating build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/ex_trace_item.svh -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/find_first_one.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/instr_trace_item.svh -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/instr_tracer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/instr_tracer_if.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/sram.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/tc_sram_fpga_wrapper.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/tc_sram_wrapper.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util creating build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/Flist.cv32a60x -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/Flist.cv32a60x_gate -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/Flist.cv32a6_imac_sv0 -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/Flist.cv32a6_imac_sv32 -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/Flist.cv32a6_imafc_sv32 -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/Flist.cv64a6_imafdc_sv39 -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/Flist.cv64a6_imafdc_sv39_gate -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/alu.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/amo_buffer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/ariane.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/ariane_regfile.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/ariane_regfile_ff.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/axi_adapter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/axi_shim.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/branch_unit.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/commit_stage.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/compressed_decoder.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/controller.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/csr_buffer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/csr_regfile.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/cva6.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/cvxif_fu.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/decoder.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/dromajo_ram.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/ex_stage.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/fpu_wrap.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/id_stage.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/instr_realign.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/issue_read_operands.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/issue_stage.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/load_store_unit.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/load_unit.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/lsu_bypass.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/mult.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/multiplier.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/perf_counters.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/re_name.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/scoreboard.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/serdiv.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/store_buffer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/store_unit.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core creating build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/amo_alu.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cache_ctrl.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cva6_icache.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cva6_icache_axi_wrapper.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/miss_handler.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/std_cache_subsystem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/std_nbdcache.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/std_no_dcache.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/tag_cmp.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_axi_adapter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_cache_subsystem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_ctrl.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_mem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_missunit.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_wbuffer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_l15_adapter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem creating build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example copying pythondata_cpu_cva6/system_verilog/core/cvxif_example/cvxif_example_coprocessor.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example copying pythondata_cpu_cva6/system_verilog/core/cvxif_example/instr_decoder.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example creating build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example/include copying pythondata_cpu_cva6/system_verilog/core/cvxif_example/include/cvxif_instr_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example/include creating build/lib/pythondata_cpu_cva6/system_verilog/core/example_tb/verilator_results copying pythondata_cpu_cva6/system_verilog/core/example_tb/verilator_results/Vcva6_core_only_tb -> build/lib/pythondata_cpu_cva6/system_verilog/core/example_tb/verilator_results creating build/lib/pythondata_cpu_cva6/system_verilog/core/frontend copying pythondata_cpu_cva6/system_verilog/core/frontend/bht.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/frontend copying pythondata_cpu_cva6/system_verilog/core/frontend/btb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/frontend copying pythondata_cpu_cva6/system_verilog/core/frontend/frontend.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/frontend copying pythondata_cpu_cva6/system_verilog/core/frontend/instr_queue.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/frontend copying pythondata_cpu_cva6/system_verilog/core/frontend/instr_scan.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/frontend copying pythondata_cpu_cva6/system_verilog/core/frontend/ras.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/frontend creating build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/ariane_axi_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/ariane_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/ariane_rvfi_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/axi_intf.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv32a60x_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv32a6_imac_sv0_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv32a6_imac_sv32_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv32a6_imafc_sv32_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdc_sv39_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cvxif_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/instr_tracer_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/riscv_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/std_cache_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/wt_cache_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include creating build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv32 copying pythondata_cpu_cva6/system_verilog/core/mmu_sv32/cva6_mmu_sv32.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv32 copying pythondata_cpu_cva6/system_verilog/core/mmu_sv32/cva6_ptw_sv32.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv32 copying pythondata_cpu_cva6/system_verilog/core/mmu_sv32/cva6_tlb_sv32.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv32 creating build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv39 copying pythondata_cpu_cva6/system_verilog/core/mmu_sv39/mmu.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv39 copying pythondata_cpu_cva6/system_verilog/core/mmu_sv39/ptw.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv39 copying pythondata_cpu_cva6/system_verilog/core/mmu_sv39/tlb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv39 creating build/lib/pythondata_cpu_cva6/system_verilog/core/pmp copying pythondata_cpu_cva6/system_verilog/core/pmp/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp copying pythondata_cpu_cva6/system_verilog/core/pmp/Bender.yml -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp copying pythondata_cpu_cva6/system_verilog/core/pmp/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp copying pythondata_cpu_cva6/system_verilog/core/pmp/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp copying pythondata_cpu_cva6/system_verilog/core/pmp/formal.sby -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp creating build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/include copying pythondata_cpu_cva6/system_verilog/core/pmp/include/riscv.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/include creating build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/src copying pythondata_cpu_cva6/system_verilog/core/pmp/src/pmp.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/src copying pythondata_cpu_cva6/system_verilog/core/pmp/src/pmp_entry.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/src creating build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/tb copying pythondata_cpu_cva6/system_verilog/core/pmp/tb/pmp_tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/tb copying pythondata_cpu_cva6/system_verilog/core/pmp/tb/tb_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/tb creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/ariane.dts -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/bootrom.S -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/bootrom.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/bootrom.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/dromajo_bootrom.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/encoding.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/gen_rom.py -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/linker.ld -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/clint copying pythondata_cpu_cva6/system_verilog/corev_apu/clint/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/clint copying pythondata_cpu_cva6/system_verilog/corev_apu/clint/axi_lite_interface.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/clint copying pythondata_cpu_cva6/system_verilog/corev_apu/clint/clint.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/clint creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane-multi-hart.cfg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane.cfg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane_pmod.cfg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane_pmod_tiny.cfg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/sourceme.sh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/ariane.xdc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/genesys-2.xdc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/kc705.xdc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/vc707.xdc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/vcu118.xdc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/check_fpga_boot.sh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/linux_boot.py -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/program.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/program_genesys2.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/prologue.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/write_cfgmem.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/ariane_peripherals_xilinx.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/ariane_xilinx.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/fan_ctrl.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/genesysii.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/kc705.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/vc707.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/vcu118.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/bootrom_32.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/bootrom_32.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/bootrom_64.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/bootrom_64.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/cv32a6.dts -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/cv64a6.dts -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/gen_rom.py -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/linker.lds -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/platform.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/startup.S -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/gpt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/gpt.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/main.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/sd.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/sd.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/smp.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/spi.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/spi.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/uart.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/uart.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/ariane_xlnx_ip.yml -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/common.mk -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_kc705.prj -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_vc707.prj -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/include copying pythondata_cpu_cva6/system_verilog/corev_apu/include/traced_instr_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/include creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/ariane_verilog_wrap.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/riscv_peripherals.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/bootrom.S -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/gen_rom.py -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/linker.ld -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/gen_rom.py -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/linker.lds -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/platform.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/startup.S -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/gpt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/gpt.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/main.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/sd.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/sd.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/smp.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/spi.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/spi.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/uart.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/uart.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_axi_soc_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_peripherals.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_soc_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_tb.cpp -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_testharness.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/rvfi_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/rvfi_tracer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/SimDTM.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/SimJTAG.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/assign.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/core_mem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/dp_ram.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/mock_uart.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/spike.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/string_buffer.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_amoport.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_dcache_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_readport.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_writeport.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/uart.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/SimDTM.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/SimJTAG.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/bootrom.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/dromajo_cosim_dpi.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/elfloader.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/msim_helper.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/msim_helper.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/remote_bitbang.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/remote_bitbang.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/sim_spike.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/sim_spike.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/spike.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/verilator.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/LICENSE -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/Makefile.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/aclocal.m4 -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/config.h.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/configure -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/configure.ac -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv-dummy_rocc.pc.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv-riscv.pc.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv-softfloat.pc.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv-spike.pc.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv-spike_main.pc.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom/debug_rom.S -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom/debug_rom.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom/link.ld -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc/dummy_rocc.ac -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc/dummy_rocc.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc/dummy_rocc.mk.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc/dummy_rocc_test.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/bootrom.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/cachesim.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/cachesim.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/clint.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/common.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/debug_defines.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/debug_module.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/debug_module.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/debug_rom_defines.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/decode.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/devices.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/devices.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/disasm.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/dts.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/dts.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/dump.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/encoding.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/execute.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/extension.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/extension.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/extensions.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/gen_icache -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insn_template.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insn_template.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/interactive.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/jtag_dtm.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/jtag_dtm.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/memtracer.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/mmu.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/mmu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/mulhi.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/opcodes.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/processor.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/processor.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/regnames.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/remote_bitbang.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/remote_bitbang.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/riscv.ac -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/riscv.mk.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/rocc.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/rocc.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/rom.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/sim.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/sim.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/simif.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/tracer.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/trap.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/trap.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/uart.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/add.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/addi.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/addiw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/addw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoadd_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoadd_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoand_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoand_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomax_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomax_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomaxu_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomaxu_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomin_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomin_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amominu_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amominu_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoor_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoor_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoswap_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoswap_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoxor_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoxor_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/and.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/andi.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/auipc.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/beq.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/bge.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/bgeu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/blt.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/bltu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/bne.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_add.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_addi.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_addi4spn.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_addw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_and.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_andi.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_beqz.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_bnez.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_ebreak.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fld.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fldsp.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_flw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_flwsp.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fsd.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fsdsp.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fsw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fswsp.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_j.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_jal.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_jalr.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_jr.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_li.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_lui.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_lw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_lwsp.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_mv.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_or.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_slli.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_srai.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_srli.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_sub.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_subw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_sw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_swsp.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_xor.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrc.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrci.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrs.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrsi.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrwi.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/div.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/divu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/divuw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/divw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/dret.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/ebreak.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/ecall.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fadd_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fadd_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fadd_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fclass_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fclass_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fclass_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_l.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_lu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_wu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_l_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_l_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_l_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_lu_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_lu_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_lu_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_l.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_lu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_wu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_l.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_lu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_wu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_w_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_w_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_w_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_wu_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_wu_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_wu_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fdiv_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fdiv_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fdiv_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fence.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fence_i.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/feq_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/feq_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/feq_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fld.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fle_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fle_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fle_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/flq.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/flt_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/flt_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/flt_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/flw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmadd_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmadd_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmadd_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmax_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmax_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmax_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmin_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmin_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmin_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmsub_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmsub_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmsub_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmul_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmul_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmul_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmv_d_x.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmv_w_x.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmv_x_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmv_x_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmadd_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmadd_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmadd_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmsub_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmsub_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmsub_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsd.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnj_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnj_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnj_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjn_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjn_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjn_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjx_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjx_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjx_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsq.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsqrt_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsqrt_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsqrt_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsub_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsub_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsub_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/jal.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/jalr.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lb.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lbu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/ld.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lh.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lhu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lr_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lr_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lui.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lwu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mret.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mul.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mulh.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mulhsu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mulhu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mulw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/or.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/ori.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/rem.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/remu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/remuw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/remw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sb.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sc_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sc_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sd.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sfence_vma.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sh.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sll.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/slli.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/slliw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sllw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/slt.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/slti.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sltiu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sltu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sra.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/srai.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sraiw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sraw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sret.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/srl.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/srli.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/srliw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/srlw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sub.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/subw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/wfi.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/xor.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/xori.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/config.guess -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/config.sub -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/install.sh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/mk-install-dirs.sh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/vcs-version.sh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_add.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_classify.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_div.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_eq.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_eq_signaling.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_isSignalingNaN.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_le.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_le_quiet.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_lt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_lt_quiet.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_mul.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_mulAdd.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_rem.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_roundToInt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_sqrt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_sub.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_f16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_f32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_f64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_i32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_i32_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_i64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_i64_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_ui32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_ui32_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_ui64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_ui64_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_add.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_div.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_eq.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_eq_signaling.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_isSignalingNaN.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_le.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_le_quiet.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_lt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_lt_quiet.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_mul.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_mulAdd.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_rem.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_roundToInt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_sqrt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_sub.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_f128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_f32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_f64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_i32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_i32_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_i64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_i64_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_ui32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_ui32_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_ui64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_ui64_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_add.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_classify.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_div.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_eq.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_eq_signaling.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_isSignalingNaN.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_le.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_le_quiet.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_lt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_lt_quiet.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_mul.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_mulAdd.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_rem.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_roundToInt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_sqrt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_sub.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_f128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_f16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_f64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_i32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_i32_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_i64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_i64_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_ui32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_ui32_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_ui64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_ui64_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_add.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_classify.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_div.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_eq.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_eq_signaling.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_isSignalingNaN.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_le.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_le_quiet.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_lt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_lt_quiet.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_mul.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_mulAdd.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_rem.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_roundToInt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_sqrt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_sub.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_f128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_f16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_f32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_i32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_i32_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_i64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_i64_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_ui32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_ui32_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_ui64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_ui64_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i32_to_f128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i32_to_f16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i32_to_f32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i32_to_f64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i64_to_f128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i64_to_f16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i64_to_f32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i64_to_f64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/internals.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/platform.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/primitiveTypes.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/primitives.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_add128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_add256M.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addCarryM.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addComplCarryM.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addM.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addMagsF128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addMagsF16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addMagsF32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addMagsF64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_approxRecip32_1.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_approxRecipSqrt32_1.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_approxRecipSqrt_1Ks.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_approxRecip_1Ks.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_commonNaNToF128UI.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_commonNaNToF16UI.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_commonNaNToF32UI.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_commonNaNToF64UI.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_compare128M.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_compare96M.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_countLeadingZeros16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_countLeadingZeros32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_countLeadingZeros64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_countLeadingZeros8.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_eq128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_f128UIToCommonNaN.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_f16UIToCommonNaN.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_f32UIToCommonNaN.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_f64UIToCommonNaN.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_le128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_lt128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul128By32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul128MTo256M.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul128To256M.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul64ByShifted32To128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul64To128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul64To128M.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mulAddF128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mulAddF16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mulAddF32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mulAddF64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_negXM.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normRoundPackToF128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normRoundPackToF16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normRoundPackToF32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normRoundPackToF64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normSubnormalF128Sig.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normSubnormalF16Sig.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normSubnormalF32Sig.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normSubnormalF64Sig.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_propagateNaNF128UI.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_propagateNaNF16UI.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_propagateNaNF32UI.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_propagateNaNF64UI.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_remStepMBy32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundMToI64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundMToUI64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackMToI64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackMToUI64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToF128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToF16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToF32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToF64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToI32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToI64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToUI32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToUI64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundToI32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundToI64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundToUI32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundToUI64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam128Extra.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam256M.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam64Extra.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftLeft128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftLeft64To96M.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRight128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightExtendM.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightJam128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightJam128Extra.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightJam64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightJam64Extra.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightM.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_sub128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_sub1XM.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_sub256M.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_subM.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_subMagsF128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_subMagsF16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_subMagsF32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_subMagsF64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat.ac -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat.mk.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat_raiseFlags.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat_state.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat_types.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/specialize.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui32_to_f128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui32_to_f16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui32_to_f32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui32_to_f64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui64_to_f128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui64_to_f16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui64_to_f32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui64_to_f64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/disasm.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/spike-dasm.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/spike.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/spike_main.ac -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/spike_main.mk.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/termios-xspike.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/xspike.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/ebreak.py -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/ebreak.s -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/tb.list -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/wave.do -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/mem_emul.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/tb_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/tlb_emul.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/tb.list -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_div.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_rem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_udiv.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_urem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/tb.list -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/wave.do -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl/tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/tb.list -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/wave.do -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/hdl/tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/hdl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/tb.list -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/wave.do -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl/tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl/tb_mem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/wave copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/wave/wave_core.do -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/wave creating build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/commit_stage.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/conf.py -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/cva6_soc.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/ex_stage.md -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/id_stage.md -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/if_stage.md -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/index.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/intro.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/issue_stage.md -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/make.bat -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/pcgen_stage.md -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/requirements.txt -> build/lib/pythondata_cpu_cva6/system_verilog/docs creating build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/ariane_overview.pdf -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/ariane_overview.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/bg.jpg -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/branch_prediction.pdf -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/branch_prediction.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/fpga_bd.pdf -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/fpga_bd.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/instr_realign.pdf -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/instr_realign.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/jekyll-dark.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/jekyll.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/ld_pipeline_diagram.svg -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/logonav.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/lsu_blockdiagram.pdf -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/lsu_blockdiagram.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/mmu_blockdiagramm.pdf -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/mmu_blockdiagramm.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/openhw-landscape.svg -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/scoreboard.pdf -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/scoreboard.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/uvm_fu_tb.ai -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/uvm_fu_tb.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static creating build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec copying pythondata_cpu_cva6/system_verilog/docs/design_spec/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec copying pythondata_cpu_cva6/system_verilog/docs/design_spec/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec copying pythondata_cpu_cva6/system_verilog/docs/design_spec/make.bat -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec copying pythondata_cpu_cva6/system_verilog/docs/design_spec/requirements.txt -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec creating build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying pythondata_cpu_cva6/system_verilog/docs/design_spec/images/CVA6_subsystems.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying pythondata_cpu_cva6/system_verilog/docs/design_spec/images/ariane_overview.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying pythondata_cpu_cva6/system_verilog/docs/design_spec/images/bht.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying pythondata_cpu_cva6/system_verilog/docs/design_spec/images/frontend_modules.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying pythondata_cpu_cva6/system_verilog/docs/design_spec/images/jade_design_automation_logo.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying pythondata_cpu_cva6/system_verilog/docs/design_spec/images/openhw-landscape.svg -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying pythondata_cpu_cva6/system_verilog/docs/design_spec/images/subsystems.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images creating build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying pythondata_cpu_cva6/system_verilog/docs/design_spec/source/CV32A6_CSR.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying pythondata_cpu_cva6/system_verilog/docs/design_spec/source/CV32A6_CSR.xml -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying pythondata_cpu_cva6/system_verilog/docs/design_spec/source/conf.py -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying pythondata_cpu_cva6/system_verilog/docs/design_spec/source/cva6_frontend.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying pythondata_cpu_cva6/system_verilog/docs/design_spec/source/cva6_glossary.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying pythondata_cpu_cva6/system_verilog/docs/design_spec/source/cva6_intro.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying pythondata_cpu_cva6/system_verilog/docs/design_spec/source/cva6_system.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying pythondata_cpu_cva6/system_verilog/docs/design_spec/source/index.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source creating build/lib/pythondata_cpu_cva6/system_verilog/docs/specifications copying pythondata_cpu_cva6/system_verilog/docs/specifications/cva6_requirement_specification.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/specifications creating build/lib/pythondata_cpu_cva6/system_verilog/docs/specifications/images copying pythondata_cpu_cva6/system_verilog/docs/specifications/images/cva6_scope.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/specifications/images creating build/lib/pythondata_cpu_cva6/system_verilog/docs/user_guide copying pythondata_cpu_cva6/system_verilog/docs/user_guide/cva6_ug_csr.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/user_guide creating build/lib/pythondata_cpu_cva6/system_verilog/pd/synth copying pythondata_cpu_cva6/system_verilog/pd/synth/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth copying pythondata_cpu_cva6/system_verilog/pd/synth/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth copying pythondata_cpu_cva6/system_verilog/pd/synth/cva6_read.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth copying pythondata_cpu_cva6/system_verilog/pd/synth/cva6_synth.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth copying pythondata_cpu_cva6/system_verilog/pd/synth/tc_sram_wrapper_256_64_00000008_00000001_00000001_none_0.sv -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth creating build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/scripts copying pythondata_cpu_cva6/system_verilog/pd/synth/scripts/dc_setup.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/scripts copying pythondata_cpu_cva6/system_verilog/pd/synth/scripts/dc_setup_filenames.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/scripts copying pythondata_cpu_cva6/system_verilog/pd/synth/scripts/gate_analysis.py -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/scripts creating build/lib/pythondata_cpu_cva6/system_verilog/scripts copying pythondata_cpu_cva6/system_verilog/scripts/parse_ila_trace.py -> build/lib/pythondata_cpu_cva6/system_verilog/scripts + RPM_EC=0 ++ jobs -p + exit 0 Executing(%install): /bin/sh -e /var/tmp/rpm-tmp.scbJ8B + umask 022 + cd /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build + '[' /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT '!=' / ']' + rm -rf /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT ++ dirname /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT + mkdir -p /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build + mkdir /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT + cd litex-pythondata-cpu-cva6 + CFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Wno-complain-wrong-lang -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -mbranch-protection=standard -fasynchronous-unwind-tables -fstack-clash-protection -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer' + LDFLAGS='-Wl,-z,relro -Wl,--as-needed -Wl,-z,pack-relative-relocs -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-hardened-ld-errors -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -Wl,--build-id=sha1 -specs=/usr/lib/rpm/redhat/redhat-package-notes ' + /usr/bin/python3 setup.py install -O1 --skip-build --root /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT --prefix /usr /usr/lib/python3.14/site-packages/setuptools/dist.py:759: SetuptoolsDeprecationWarning: License classifiers are deprecated. !! ******************************************************************************** Please consider removing the following classifiers in favor of a SPDX license expression: License :: OSI Approved :: Apache Software License See https://packaging.python.org/en/latest/guides/writing-pyproject-toml/#license for details. ******************************************************************************** !! self._finalize_license_expression() running install /usr/lib/python3.14/site-packages/setuptools/_distutils/cmd.py:90: SetuptoolsDeprecationWarning: setup.py install is deprecated. !! ******************************************************************************** Please avoid running ``setup.py`` directly. Instead, use pypa/build, pypa/installer or other standards-based tools. Follow the current Python packaging guidelines when building Python RPM packages. See https://blog.ganssle.io/articles/2021/10/setup-py-deprecated.html and https://docs.fedoraproject.org/en-US/packaging-guidelines/Python/ for details. ******************************************************************************** !! self.initialize_options() running install_lib creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6 creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/scripts/parse_ila_trace.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/scripts creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/pd creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/scripts/gate_analysis.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/scripts/dc_setup_filenames.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/scripts/dc_setup.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/tc_sram_wrapper_256_64_00000008_00000001_00000001_none_0.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/cva6_synth.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/cva6_read.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/user_guide copying build/lib/pythondata_cpu_cva6/system_verilog/docs/user_guide/cva6_ug_csr.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/user_guide creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/specifications creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/specifications/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/specifications/images/cva6_scope.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/specifications/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/specifications/cva6_requirement_specification.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/specifications creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/index.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/cva6_system.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/cva6_intro.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/cva6_glossary.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/cva6_frontend.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/conf.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/CV32A6_CSR.xml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/CV32A6_CSR.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images/subsystems.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images/openhw-landscape.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images/jade_design_automation_logo.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images/frontend_modules.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images/bht.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images/ariane_overview.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images/CVA6_subsystems.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/requirements.txt -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/make.bat -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/uvm_fu_tb.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/uvm_fu_tb.ai -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/scoreboard.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/scoreboard.pdf -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/openhw-landscape.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/mmu_blockdiagramm.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/mmu_blockdiagramm.pdf -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/lsu_blockdiagram.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/lsu_blockdiagram.pdf -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/logonav.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/ld_pipeline_diagram.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/jekyll.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/jekyll-dark.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/instr_realign.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/instr_realign.pdf -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/fpga_bd.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/fpga_bd.pdf -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/branch_prediction.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/branch_prediction.pdf -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/bg.jpg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/ariane_overview.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/ariane_overview.pdf -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/requirements.txt -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/pcgen_stage.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/make.bat -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/issue_stage.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/intro.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/index.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/if_stage.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/id_stage.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/ex_stage.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/cva6_soc.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/conf.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/commit_stage.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/wave copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/wave/wave_core.do -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/wave creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl/tb_mem.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl/tb.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/wave.do -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/tb.list -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/hdl/tb.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/wave.do -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/tb.list -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl/tb.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/wave.do -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/tb.list -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_urem.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_udiv.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_rem.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_div.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/tb.list -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/tlb_emul.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/tb_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/tb.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/mem_emul.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/wave.do -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/tb.list -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/ebreak.s -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/ebreak.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/xspike.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/termios-xspike.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/spike_main.mk.in -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/spike_main.ac -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/spike.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/spike-dasm.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/disasm.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui64_to_f64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui64_to_f32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui64_to_f16.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui64_to_f128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui32_to_f64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui32_to_f32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui32_to_f16.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui32_to_f128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/specialize.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat_types.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat_state.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat_raiseFlags.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat.mk.in -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat.ac -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_subMagsF64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_subMagsF32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_subMagsF16.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_subMagsF128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_subM.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_sub256M.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_sub1XM.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_sub128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightM.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightJam64Extra.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightJam64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightJam128Extra.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightJam128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightExtendM.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRight128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftLeft64To96M.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftLeft128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam64Extra.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam256M.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam128Extra.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundToUI64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundToUI32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundToI64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundToI32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToUI64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToUI32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToI64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToI32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToF64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToF32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToF16.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToF128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackMToUI64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackMToI64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundMToUI64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundMToI64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_remStepMBy32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_propagateNaNF64UI.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_propagateNaNF32UI.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_propagateNaNF16UI.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_propagateNaNF128UI.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normSubnormalF64Sig.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normSubnormalF32Sig.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normSubnormalF16Sig.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normSubnormalF128Sig.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normRoundPackToF64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normRoundPackToF32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normRoundPackToF16.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normRoundPackToF128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_negXM.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mulAddF64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mulAddF32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mulAddF16.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mulAddF128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul64To128M.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul64To128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul64ByShifted32To128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul128To256M.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul128MTo256M.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul128By32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_lt128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_le128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_f64UIToCommonNaN.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_f32UIToCommonNaN.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_f16UIToCommonNaN.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_f128UIToCommonNaN.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_eq128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_countLeadingZeros8.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_countLeadingZeros64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_countLeadingZeros32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_countLeadingZeros16.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_compare96M.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_compare128M.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_commonNaNToF64UI.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_commonNaNToF32UI.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_commonNaNToF16UI.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_commonNaNToF128UI.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_approxRecip_1Ks.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_approxRecipSqrt_1Ks.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_approxRecipSqrt32_1.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_approxRecip32_1.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addMagsF64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addMagsF32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addMagsF16.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addMagsF128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addM.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addComplCarryM.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addCarryM.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_add256M.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_add128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/primitives.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/primitiveTypes.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/platform.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/internals.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i64_to_f64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i64_to_f32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i64_to_f16.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i64_to_f128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i32_to_f64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i32_to_f32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i32_to_f16.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i32_to_f128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_ui64_r_minMag.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_ui64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_ui32_r_minMag.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_ui32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_i64_r_minMag.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_i64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_i32_r_minMag.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_i32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_f32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_f16.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_f128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_sub.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_sqrt.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_roundToInt.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_rem.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_mulAdd.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_mul.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_lt_quiet.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_lt.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_le_quiet.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_le.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_isSignalingNaN.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_eq_signaling.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_eq.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_div.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_classify.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_add.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_ui64_r_minMag.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_ui64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_ui32_r_minMag.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_ui32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_i64_r_minMag.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_i64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_i32_r_minMag.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_i32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_f64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_f16.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_f128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_sub.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_sqrt.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_roundToInt.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_rem.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_mulAdd.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_mul.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_lt_quiet.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_lt.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_le_quiet.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_le.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_isSignalingNaN.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_eq_signaling.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_eq.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_div.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_classify.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_add.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_ui64_r_minMag.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_ui64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_ui32_r_minMag.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_ui32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_i64_r_minMag.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_i64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_i32_r_minMag.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_i32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_f64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_f32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_f128.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_sub.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_sqrt.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_roundToInt.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_rem.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_mulAdd.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_mul.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_lt_quiet.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_lt.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_le_quiet.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_le.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_isSignalingNaN.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_eq_signaling.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_eq.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_div.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_add.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_ui64_r_minMag.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_ui64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_ui32_r_minMag.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_ui32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_i64_r_minMag.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_i64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_i32_r_minMag.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_i32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_f64.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_f32.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_f16.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_sub.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_sqrt.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_roundToInt.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_rem.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_mulAdd.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_mul.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_lt_quiet.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_lt.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_le_quiet.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_le.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_isSignalingNaN.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_eq_signaling.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_eq.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_div.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_classify.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_add.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/vcs-version.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/mk-install-dirs.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/install.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/config.sub -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/config.guess -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/xori.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/xor.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/wfi.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/subw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sub.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/srlw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/srliw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/srli.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/srl.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sret.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sraw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sraiw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/srai.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sra.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sltu.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sltiu.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/slti.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/slt.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sllw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/slliw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/slli.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sll.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sh.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sfence_vma.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sd.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sc_w.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sc_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sb.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/remw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/remuw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/remu.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/rem.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/ori.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/or.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mulw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mulhu.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mulhsu.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mulh.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mul.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mret.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lwu.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lui.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lr_w.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lr_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lhu.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lh.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/ld.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lbu.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lb.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/jalr.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/jal.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsub_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsub_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsub_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsqrt_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsqrt_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsqrt_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsq.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjx_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjx_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjx_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjn_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjn_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjn_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnj_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnj_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnj_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsd.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmsub_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmsub_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmsub_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmadd_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmadd_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmadd_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmv_x_w.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmv_x_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmv_w_x.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmv_d_x.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmul_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmul_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmul_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmsub_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmsub_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmsub_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmin_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmin_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmin_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmax_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmax_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmax_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmadd_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmadd_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmadd_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/flw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/flt_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/flt_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/flt_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/flq.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fle_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fle_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fle_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fld.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/feq_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/feq_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/feq_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fence_i.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fence.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fdiv_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fdiv_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fdiv_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_wu_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_wu_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_wu_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_w_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_w_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_w_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_wu.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_w.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_lu.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_l.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_wu.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_w.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_lu.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_l.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_lu_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_lu_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_lu_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_l_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_l_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_l_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_wu.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_w.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_lu.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_l.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fclass_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fclass_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fclass_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fadd_s.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fadd_q.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fadd_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/ecall.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/ebreak.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/dret.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/divw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/divuw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/divu.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/div.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrwi.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrsi.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrs.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrci.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrc.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_xor.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_swsp.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_sw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_subw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_sub.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_srli.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_srai.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_slli.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_or.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_mv.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_lwsp.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_lw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_lui.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_li.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_jr.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_jalr.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_jal.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_j.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fswsp.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fsw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fsdsp.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fsd.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_flwsp.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_flw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fldsp.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fld.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_ebreak.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_bnez.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_beqz.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_andi.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_and.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_addw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_addi4spn.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_addi.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_add.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/bne.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/bltu.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/blt.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/bgeu.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/bge.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/beq.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/auipc.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/andi.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/and.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoxor_w.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoxor_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoswap_w.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoswap_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoor_w.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoor_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amominu_w.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amominu_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomin_w.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomin_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomaxu_w.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomaxu_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomax_w.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomax_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoand_w.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoand_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoadd_w.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoadd_d.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/addw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/addiw.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/addi.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/add.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/uart.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/trap.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/trap.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/tracer.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/simif.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/sim.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/sim.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/rom.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/rocc.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/rocc.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/riscv.mk.in -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/riscv.ac -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/remote_bitbang.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/remote_bitbang.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/regnames.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/processor.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/processor.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/opcodes.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/mulhi.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/mmu.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/mmu.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/memtracer.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/jtag_dtm.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/jtag_dtm.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/interactive.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insn_template.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insn_template.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/gen_icache -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/extensions.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/extension.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/extension.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/execute.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/encoding.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/dump.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/dts.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/dts.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/disasm.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/devices.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/devices.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/decode.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/debug_rom_defines.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/debug_module.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/debug_module.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/debug_defines.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/common.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/clint.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/cachesim.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/cachesim.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/bootrom.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc/dummy_rocc_test.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc/dummy_rocc.mk.in -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc/dummy_rocc.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc/dummy_rocc.ac -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom/link.ld -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom/debug_rom.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom/debug_rom.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv-spike_main.pc.in -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv-spike.pc.in -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv-softfloat.pc.in -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv-riscv.pc.in -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv-dummy_rocc.pc.in -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/configure.ac -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/configure -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/config.h.in -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/aclocal.m4 -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/Makefile.in -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/LICENSE -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/verilator.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/spike.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/sim_spike.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/sim_spike.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/remote_bitbang.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/remote_bitbang.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/msim_helper.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/msim_helper.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/elfloader.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/dromajo_cosim_dpi.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/bootrom.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/SimJTAG.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/SimDTM.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/uart.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_writeport.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_readport.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_dcache_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_amoport.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb.svh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/string_buffer.svh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/spike.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/mock_uart.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/dp_ram.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/core_mem.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/assign.svh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/SimJTAG.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/SimDTM.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/rvfi_tracer.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/rvfi_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_testharness.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_tb.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_tb.cpp -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_soc_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_peripherals.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_axi_soc_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/uart.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/uart.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/spi.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/spi.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/smp.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/sd.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/sd.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/main.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/gpt.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/gpt.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/startup.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/platform.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/linker.lds -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/gen_rom.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/linker.ld -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/gen_rom.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/bootrom.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/riscv_peripherals.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/ariane_verilog_wrap.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/include copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/include/traced_instr_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/include creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/tcl/run.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/tcl/run.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_vc707.prj -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_kc705.prj -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/tcl/run.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/tcl/run.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/tcl/run.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/tcl/run.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl/run.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl/run.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/tcl/run.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/tcl/run.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/common.mk -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/ariane_xlnx_ip.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/uart.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/uart.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/spi.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/spi.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/smp.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/sd.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/sd.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/main.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/gpt.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/gpt.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/startup.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/platform.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/linker.lds -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/gen_rom.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/cv64a6.dts -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/cv32a6.dts -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/bootrom_64.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/bootrom_64.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/bootrom_32.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/bootrom_32.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/vcu118.svh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/vc707.svh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/kc705.svh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/genesysii.svh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/fan_ctrl.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/ariane_xilinx.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/ariane_peripherals_xilinx.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/write_cfgmem.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/run.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/prologue.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/program_genesys2.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/program.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/linux_boot.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/check_fpga_boot.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/vcu118.xdc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/vc707.xdc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/kc705.xdc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/genesys-2.xdc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/ariane.xdc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/sourceme.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane_pmod_tiny.cfg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane_pmod.cfg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane.cfg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane-multi-hart.cfg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/clint copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/clint/clint.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/clint copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/clint/axi_lite_interface.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/clint copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/clint/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/clint creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/linker.ld -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/gen_rom.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/encoding.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/dromajo_bootrom.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/bootrom.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/bootrom.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/bootrom.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/ariane.dts -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/tb copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/tb/tb_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/tb copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/tb/pmp_tb.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/tb creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/src copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/src/pmp_entry.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/src copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/src/pmp.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/src creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/include/riscv.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/formal.sby -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/Bender.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/mmu_sv39 copying build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv39/tlb.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/mmu_sv39 copying build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv39/ptw.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/mmu_sv39 copying build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv39/mmu.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/mmu_sv39 creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/mmu_sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv32/cva6_tlb_sv32.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/mmu_sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv32/cva6_ptw_sv32.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/mmu_sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv32/cva6_mmu_sv32.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/mmu_sv32 creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/wt_cache_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/std_cache_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/riscv_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/instr_tracer_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cvxif_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdc_sv39_config_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv32a6_imafc_sv32_config_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv32a6_imac_sv32_config_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv32a6_imac_sv0_config_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv32a60x_config_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/axi_intf.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/ariane_rvfi_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/ariane_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/ariane_axi_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/include creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/frontend copying build/lib/pythondata_cpu_cva6/system_verilog/core/frontend/ras.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/frontend copying build/lib/pythondata_cpu_cva6/system_verilog/core/frontend/instr_scan.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/frontend copying build/lib/pythondata_cpu_cva6/system_verilog/core/frontend/instr_queue.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/frontend copying build/lib/pythondata_cpu_cva6/system_verilog/core/frontend/frontend.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/frontend copying build/lib/pythondata_cpu_cva6/system_verilog/core/frontend/btb.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/frontend copying build/lib/pythondata_cpu_cva6/system_verilog/core/frontend/bht.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/frontend creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/example_tb creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/example_tb/verilator_results copying build/lib/pythondata_cpu_cva6/system_verilog/core/example_tb/verilator_results/Vcva6_core_only_tb -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/example_tb/verilator_results creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/cvxif_example creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/cvxif_example/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example/include/cvxif_instr_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/cvxif_example/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example/instr_decoder.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/cvxif_example copying build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example/cvxif_example_coprocessor.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/cvxif_example creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_l15_adapter.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_wbuffer.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_missunit.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_mem.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_ctrl.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_cache_subsystem.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_axi_adapter.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/tag_cmp.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/std_no_dcache.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/std_nbdcache.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/std_cache_subsystem.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/miss_handler.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cva6_icache_axi_wrapper.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cva6_icache.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cache_ctrl.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/amo_alu.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/store_unit.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/store_buffer.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/serdiv.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/scoreboard.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/re_name.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/perf_counters.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/multiplier.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/mult.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/lsu_bypass.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/load_unit.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/load_store_unit.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/issue_stage.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/issue_read_operands.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/instr_realign.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/id_stage.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/fpu_wrap.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/ex_stage.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/dromajo_ram.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/decoder.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_fu.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/cva6.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/csr_regfile.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/csr_buffer.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/controller.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/compressed_decoder.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/commit_stage.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/branch_unit.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/axi_shim.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/axi_adapter.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/ariane_regfile_ff.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/ariane_regfile.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/ariane.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/amo_buffer.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/alu.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/Flist.cv64a6_imafdc_sv39_gate -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/Flist.cv64a6_imafdc_sv39 -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/Flist.cv32a6_imafc_sv32 -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/Flist.cv32a6_imac_sv32 -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/Flist.cv32a6_imac_sv0 -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/Flist.cv32a60x_gate -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/Flist.cv32a60x -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/core creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/common creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/common/local creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/tc_sram_wrapper.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/tc_sram_fpga_wrapper.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/sram.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/instr_tracer_if.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/instr_tracer.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/instr_trace_item.svh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/find_first_one.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/ex_trace_item.svh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/common/local/techlib creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl/SyncTpRam.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl/SyncSpRamBeNx64.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl/SyncSpRamBeNx32.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl/SyncSpRam.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl/SyncDpRam.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/travis-ci-emul.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/torture_make.patch -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/setup.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/riscv-mul-tests.list -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/riscv-fp-tests.list -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/riscv-benchmarks.list -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/riscv-asm-tests.list -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/riscv-amo-tests.list -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/path-setup.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/make-tmp.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/install-verilator.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/install-spike.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/install-riscvpk.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/install-fesvr.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/install-dtc.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/gitlab-ci-emul.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/get-torture.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/float.config -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/default.config -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/check-tests.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/build-riscv-tests.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/build-riscv-gcc.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/ci creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/cva6.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/core-v-verif-cva6.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/.github creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/.github/workflows copying build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows/ci.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/.github/workflows creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE copying build/lib/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE/task.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE copying build/lib/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE/bug.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE copying build/lib/pythondata_cpu_cva6/system_verilog/src_files.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/init_testharness.do -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/config_pkg_generator.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/ariane.core -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/LICENSE.SiFive -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/LICENSE.Berkeley -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/LICENSE -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/Flist.ariane -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/CONTRIBUTING.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/CODEOWNERS -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/CHANGELOG.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/Bender.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/.gitmodules -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/.editorconfig -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/__init__.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6 byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/scripts/parse_ila_trace.py to parse_ila_trace.cpython-314.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth/scripts/gate_analysis.py to gate_analysis.cpython-314.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/conf.py to conf.cpython-314.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/conf.py to conf.cpython-314.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py to testlib.cpython-314.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/ebreak.py to ebreak.cpython-314.pyc /usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:86: SyntaxWarning: "\(" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\("? A raw string is also an option. /usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:91: SyntaxWarning: "\(" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\("? A raw string is also an option. /usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:103: SyntaxWarning: "\(" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\("? A raw string is also an option. /usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/config_pkg_generator.py:97: SyntaxWarning: "\g" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\g"? A raw string is also an option. /usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/config_pkg_generator.py:111: SyntaxWarning: "\g" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\g"? A raw string is also an option. byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/gen_rom.py to gen_rom.cpython-314.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/gen_rom.py to gen_rom.cpython-314.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/gen_rom.py to gen_rom.cpython-314.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/linux_boot.py to linux_boot.cpython-314.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/gen_rom.py to gen_rom.cpython-314.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/config_pkg_generator.py to config_pkg_generator.cpython-314.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/__init__.py to __init__.cpython-314.pyc writing byte-compilation script '/tmp/tmp1ez67ij9.py' /usr/bin/python3 /tmp/tmp1ez67ij9.py /usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:86: SyntaxWarning: "\(" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\("? A raw string is also an option. /usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:91: SyntaxWarning: "\(" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\("? A raw string is also an option. /usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:103: SyntaxWarning: "\(" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\("? A raw string is also an option. /usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/config_pkg_generator.py:97: SyntaxWarning: "\g" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\g"? A raw string is also an option. /usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/config_pkg_generator.py:111: SyntaxWarning: "\g" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\g"? A raw string is also an option. removing /tmp/tmp1ez67ij9.py running install_egg_info running egg_info writing pythondata_cpu_cva6.egg-info/PKG-INFO writing dependency_links to pythondata_cpu_cva6.egg-info/dependency_links.txt writing top-level names to pythondata_cpu_cva6.egg-info/top_level.txt reading manifest file 'pythondata_cpu_cva6.egg-info/SOURCES.txt' reading manifest template 'MANIFEST.in' warning: no previously-included files matching '*.py[cod]' found anywhere in distribution warning: no previously-included files matching '__pycache__/*' found anywhere in distribution adding license file 'LICENSE' writing manifest file 'pythondata_cpu_cva6.egg-info/SOURCES.txt' Copying pythondata_cpu_cva6.egg-info to /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6-4.2.0.post435-py3.14.egg-info running install_scripts + rm -rfv /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/bin/__pycache__ + sed -i /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/ebreak.py -e 's|#!/usr/bin/python|#!/usr/bin/python3|' + /usr/lib/rpm/check-buildroot + /usr/lib/rpm/redhat/brp-ldconfig + /usr/lib/rpm/brp-compress + /usr/lib/rpm/brp-strip /bin/true + /usr/lib/rpm/brp-strip-comment-note /bin/true /usr/bin/objdump + /usr/lib/rpm/redhat/brp-strip-lto /bin/true + /usr/lib/rpm/check-rpaths + /usr/lib/rpm/redhat/brp-mangle-shebangs mangling shebang in /usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/ci/build-riscv-gcc.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/ci/build-riscv-tests.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/ci/check-tests.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/ci/get-torture.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/ci/gitlab-ci-emul.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/ci/install-dtc.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/ci/install-fesvr.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/ci/install-riscvpk.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/ci/install-spike.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/ci/install-verilator.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/ci/make-tmp.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/ci/setup.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/gen_rom.py from /usr/bin/env python3 to #!/usr/bin/python3 mangling shebang in /usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/gen_rom.py from /usr/bin/env python3 to #!/usr/bin/python3 *** WARNING: ./usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj is executable but has no shebang, removing executable bit mangling shebang in /usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/gen_rom.py from /usr/bin/env python3 to #!/usr/bin/python3 mangling shebang in /usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/gen_rom.py from /usr/bin/env python3 to #!/usr/bin/python3 mangling shebang in /usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/configure from /bin/sh to #!/usr/bin/sh *** WARNING: ./usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom/debug_rom.S is executable but has no shebang, removing executable bit mangling shebang in /usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/gen_icache from /bin/sh to #!/usr/bin/sh mangling shebang in /usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/config.guess from /bin/sh to #!/usr/bin/sh mangling shebang in /usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/config.sub from /bin/sh to #!/usr/bin/sh mangling shebang in /usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/install.sh from /bin/sh to #!/usr/bin/sh mangling shebang in /usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/mk-install-dirs.sh from /bin/sh to #!/usr/bin/sh mangling shebang in /usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/vcs-version.sh from /bin/bash to #!/usr/bin/bash *** WARNING: ./usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_classify.c is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_classify.c is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_classify.c is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/Makefile is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/Makefile is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/Makefile is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/Makefile is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/Makefile is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/scripts/parse_ila_trace.py is executable but has no shebang, removing executable bit + /usr/lib/rpm/brp-remove-la-files + /usr/lib/rpm/redhat/brp-python-rpm-in-distinfo + env /usr/lib/rpm/redhat/brp-python-bytecompile '' 1 0 -j4 Bytecompiling .py files below /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14 using python3.14 /usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/config_pkg_generator.py:97: SyntaxWarning: "\g" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\g"? A raw string is also an option. /usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/config_pkg_generator.py:111: SyntaxWarning: "\g" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\g"? A raw string is also an option. /usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/config_pkg_generator.py:97: SyntaxWarning: "\g" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\g"? A raw string is also an option. /usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/config_pkg_generator.py:111: SyntaxWarning: "\g" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\g"? A raw string is also an option. /usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:86: SyntaxWarning: "\(" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\("? A raw string is also an option. /usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:91: SyntaxWarning: "\(" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\("? A raw string is also an option. /usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:103: SyntaxWarning: "\(" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\("? A raw string is also an option. /usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:86: SyntaxWarning: "\(" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\("? A raw string is also an option. /usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:91: SyntaxWarning: "\(" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\("? A raw string is also an option. /usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:103: SyntaxWarning: "\(" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\("? A raw string is also an option. + /usr/lib/rpm/redhat/brp-python-hardlink + /usr/bin/add-determinism --brp -j4 /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/__pycache__/__init__.cpython-314.opt-1.pyc: rewriting with normalized contents /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/__pycache__/config_pkg_generator.cpython-314.opt-1.pyc: rewriting with normalized contents /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/__pycache__/gen_rom.cpython-314.opt-1.pyc: rewriting with normalized contents /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/__pycache__/linux_boot.cpython-314.opt-1.pyc: rewriting with normalized contents /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/__pycache__/gen_rom.cpython-314.opt-1.pyc: rewriting with normalized contents /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/__pycache__/gen_rom.cpython-314.opt-1.pyc: rewriting with normalized contents /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/__pycache__/gen_rom.cpython-314.opt-1.pyc: rewriting with normalized contents /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/__pycache__/ebreak.cpython-314.opt-1.pyc: rewriting with normalized contents /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/__pycache__/conf.cpython-314.opt-1.pyc: rewriting with normalized contents /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/__pycache__/conf.cpython-314.opt-1.pyc: rewriting with normalized contents /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth/scripts/__pycache__/gate_analysis.cpython-314.opt-1.pyc: rewriting with normalized contents /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/scripts/__pycache__/parse_ila_trace.cpython-314.opt-1.pyc: rewriting with normalized contents /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/__pycache__/testlib.cpython-314.pyc: replacing with normalized version /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.14/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/__pycache__/testlib.cpython-314.opt-1.pyc: replacing with normalized version Scanned 116 directories and 979 files, processed 14 inodes, 14 modified (2 replaced + 12 rewritten), 0 unsupported format, 0 errors Processing files: litex-pythondata-cpu-cva6-python3-2026.04-20260526.0.gitda8c19c8.fc43.noarch Executing(%doc): /bin/sh -e /var/tmp/rpm-tmp.Potiex + umask 022 + cd /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build + cd litex-pythondata-cpu-cva6 + DOCDIR=/builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/share/doc/litex-pythondata-cpu-cva6-python3 + export LC_ALL=C.UTF-8 + LC_ALL=C.UTF-8 + export DOCDIR + /usr/bin/mkdir -p /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/share/doc/litex-pythondata-cpu-cva6-python3 + cp -pr /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/litex-pythondata-cpu-cva6/README.md /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/share/doc/litex-pythondata-cpu-cva6-python3 + RPM_EC=0 ++ jobs -p + exit 0 Executing(%license): /bin/sh -e /var/tmp/rpm-tmp.ZoQigV + umask 022 + cd /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build + cd litex-pythondata-cpu-cva6 + LICENSEDIR=/builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/share/licenses/litex-pythondata-cpu-cva6-python3 + export LC_ALL=C.UTF-8 + LC_ALL=C.UTF-8 + export LICENSEDIR + /usr/bin/mkdir -p /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/share/licenses/litex-pythondata-cpu-cva6-python3 + cp -pr /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/litex-pythondata-cpu-cva6/LICENSE /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/share/licenses/litex-pythondata-cpu-cva6-python3 + RPM_EC=0 ++ jobs -p + exit 0 Provides: litex-pythondata-cpu-cva6-python3 = 2026.04-20260526.0.gitda8c19c8.fc43 pythondata-cpu-cva6 Requires(rpmlib): rpmlib(CompressedFileNames) <= 3.0.4-1 rpmlib(FileDigests) <= 4.6.0-1 rpmlib(PartialHardlinkSets) <= 4.0.4-1 rpmlib(PayloadFilesHavePrefix) <= 4.0-1 warning: Arch dependent binaries in noarch package Checking for unpackaged file(s): /usr/lib/rpm/check-files /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT Wrote: /builddir/build/RPMS/litex-pythondata-cpu-cva6-python3-2026.04-20260526.0.gitda8c19c8.fc43.noarch.rpm Executing(rmbuild): /bin/sh -e /var/tmp/rpm-tmp.pZIW5F + umask 022 + cd /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build + test -d /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build + /usr/bin/chmod -Rf a+rX,u+w,g-w,o-w /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build + rm -rf /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build + RPM_EC=0 ++ jobs -p + exit 0 RPM build warnings: The %py3_build macro is deprecated and will likely stop working in Fedora 44. See the current Python packaging guidelines: https://docs.fedoraproject.org/en-US/packaging-guidelines/Python/ The %py3_install macro is deprecated and will likely stop working in Fedora 44. See the current Python packaging guidelines: https://docs.fedoraproject.org/en-US/packaging-guidelines/Python/ Arch dependent binaries in noarch package Finish: rpmbuild litex-pythondata-cpu-cva6-2026.04-20260526.0.gitda8c19c8.fc43.src.rpm Finish: build phase for litex-pythondata-cpu-cva6-2026.04-20260526.0.gitda8c19c8.fc43.src.rpm INFO: chroot_scan: 1 files copied to /var/lib/copr-rpmbuild/results/chroot_scan INFO: /var/lib/mock/fedora-43-aarch64-1779852097.193724/root/var/log/dnf5.log INFO: chroot_scan: creating tarball /var/lib/copr-rpmbuild/results/chroot_scan.tar.gz /bin/tar: Removing leading `/' from member names INFO: Done(/var/lib/copr-rpmbuild/results/litex-pythondata-cpu-cva6-2026.04-20260526.0.gitda8c19c8.fc43.src.rpm) Config(child) 0 minutes 25 seconds INFO: Results and/or logs in: /var/lib/copr-rpmbuild/results INFO: Cleaning up build root ('cleanup_on_success=True') Start: clean chroot INFO: unmounting tmpfs. Finish: clean chroot Finish: run Running RPMResults tool Package info: { "packages": [ { "name": "litex-pythondata-cpu-cva6-python3", "epoch": null, "version": "2026.04", "release": "20260526.0.gitda8c19c8.fc43", "arch": "noarch" }, { "name": "litex-pythondata-cpu-cva6", "epoch": null, "version": "2026.04", "release": "20260526.0.gitda8c19c8.fc43", "arch": "src" } ] } RPMResults finished