entity toggle_demo is

port (
        clk_in : in  std_logic; -- System Clock
        data_q : out std_logic  -- Toggling Port
);

end entity toggle_demo;

architecture RTL of toggle_demo is

signal data : std_logic := '0';

begin

data_q <= data;
data_proc : process (clk_in)
begin
        if (rising_edge(clk_in)) then
                data <= not data;
        end if;
end process;

end architecture RTL;